Search Results (67)

As the deep integration of the Internet of Things (IoT) and artificial intelligence (AI) technologies has rendered traditional encryption techniques increasingly inadequate in terms of security strength, the implementation of hardware-level security solutions has been identified as a critical issue in the design of information systems. Memristors, as passive circuit components with their intrinsic stochastic switching behavior, multistate storage capability, and low power consumption, have been exploited to provide a viable approach for the construction of hardware security primitives, including true random number generators (TRNGs) and physically unclonable functions (PUFs). In this review, the latest research advances in memristor-based hardware security technologies were systematically surveyed from three perspectives, namely TRNGs, PUFs and other security schemes. With regard to TRNGs and PUFs, respectively, we have systematically summarized their characteristics, including throughput, power consumption and randomness quality, as well as uniqueness, reliability and methods, with particular attention paid to the types of entropy sources and bit-generation strategies. In addition, the potential application of other memristor-based hardware security solutions in information hiding, encrypted transmission and authentication was also analyzed. Subsequently, the principal challenges impeding the transition from laboratory research to mass production were summarized, encompassing synergistic integration with advanced CMOS processes, the balance between reliability and stochasticity, and the absence of design methodologies that integrate hardware and software. Future development trajectories were further delineated, including cross-layer optimization across devices, circuits, and systems, the design of high-security chips resistant to machine learning attacks, CMOS-compatible stable implementation schemes, and the on-chip integration of TRNGs, PUFs, and encryption engines. The present review is intended to serve as a systematic reference for the design of novel hardware security systems, thereby paving the way for the practical deployment of memristor-based security technologies. Full article

Deep learning (DL) models have achieved remarkable progress in natural language processing, computer vision, content generation, and edge intelligence; however, their rapidly increasing computational complexity, memory demand, and deployment diversity pose significant challenges for practical implementation. Field-programmable gate arrays (FPGAs) provide customized low-precision computation, spatial dataflow, on-chip data reuse, reconfigurability, and rich I/O capabilities, making them an important platform for DL inference. This paper presents a systematic review of FPGA-based DL deployment from a cross-layer perspective spanning model, compiler, architecture, runtime, and electronic design automation (EDA). Following a PRISMA-guided evidence synthesis protocol, this review analyzes DL workload characteristics, FPGA architectural optimizations, deployment toolflows, and physical implementation challenges. A unified taxonomy is proposed along the specialization–programmability continuum, including model-fixed accelerators, generator-based accelerators, template-configurable accelerators, and ISA-programmable overlays. These approaches are compared according to hardware regeneration requirements, model adaptability, operator coverage, compilation cost, and deployment flexibility. Furthermore, emerging workloads, including vision Transformers, graph neural networks, large language models, and multimodal models, are analyzed from the perspectives of computation, memory behavior, and runtime coordination. The review shows that FPGA deployment efficiency increasingly depends on memory capacity, mutable state management, operator support, and end-to-end compilation capability rather than peak multiply–accumulate throughput alone. Based on the analysis of 70 primary FPGA implementation studies, this paper highlights that reliable cross-study comparison requires careful consideration of model configuration, precision, execution phase, batch size, memory residency, FPGA platform, and evidence maturity. For multimodal generative models, the current evidence remains limited, with no identified end-to-end FPGA-based vision–language model implementation in the reviewed corpus. This review provides a systematic perspective for future FPGA-based DL deployment research, emphasizing cross-layer optimization, physically aware compilation, extensible accelerator architectures, and practical deployment efficiency. Full article

The deployment of deep learning-based vision systems on edge devices introduces a complex trade-off between computational efficiency and detection accuracy. In this work, we investigate this trade-off in the context of a multi-stage Automatic License Plate Recognition (ALPR) pipeline, evaluated in two heterogeneous edge execution environments: a general-purpose Raspberry Pi 5 single-board computer and the ARTPEC-8 system-on-chip integrated into an Axis smart camera, where neural network inference is accelerated by the on-chip DLPU. All experiments were performed using pre-recorded images loaded from the file system; neither the Axis camera sensor nor a live video stream was used. This study evaluates the impact of model architecture, numerical precision, and input resolution on both inference latency and detection performance. YOLOv5- and YOLOv8-based models were analyzed under multiple quantization schemes (FP32, FP16, dynamic, and INT8), while a cross-platform benchmark was conducted to assess the benefits and limitations of hardware acceleration. The results show that dedicated accelerators provide significant latency reduction at higher resolutions; however, this advantage is accompanied by reduced flexibility and increased sensitivity to quantization effects. In contrast, CPU-based execution enables the use of more recent and quantization-robust model architectures, which can partially compensate for the lack of hardware acceleration when combined with resolution scaling. Furthermore, the analysis hig ights the importance of hybrid-resolution processing in multi-stage pipelines, where different stages can operate at different input resolutions to balance accuracy and performance. The findings demonstrate that optimal system design requires a joint consideration of hardware characteristics, model architecture, and quantization strategy, rather than relying on a single optimization dimension. The presented results provide practical insights for the design of efficient and robust edge-based ALPR systems, with direct implications for real-world industrial deployments. Full article

The escalating accumulation of microplastics (MPs) in marine ecosystems presents a critical environmental crisis. However, current monitoring efforts rely heavily on labor-intensive, contamination-prone, and time-consuming laboratory analyses. While these conventional off-chip methods provide high accuracy, they inherently lack the throughput and autonomy required for continuous, real-time oceanic surveillance. To bridge this technological gap, microfluidic technologies (Lab-on-a-Chip) provide a viable route towards miniaturized, reagent-free in situ detection with reduced sample volumes and continuous operation capability. This review examines the transition from benchtop to field-deployable platforms and organizes the available microfluidic approaches for MP analysis into a structured overview. We examine on-chip sample manipulation and complementary separation techniques, such as acoustophoresis, dielectrophoresis, and optical tweezers, which are essential for isolating target particles from complex environmental matrices and overcoming intrinsic microfluidic challenges. Following sample preparation, we provide a comprehensive evaluation of state-of-the-art optical and spectroscopic identification methods optimized for continuous flow detection. Finally, we address current analytical limitations and discuss how the integration of machine learning with dynamic spectral libraries could enable autonomous, field-deployed monitoring networks for long-term MP surveillance. Full article

Wireless edge systems increasingly rely on on-device learning for tasks such as user localization and misuser detection, but centralized training is often infeasible because of privacy and bandwidth constraints. In this work, we study communication-efficient federated learning schemes that jointly train lightweight neural models across clients. We compare a multi-task shared-backbone strategy with mid-training backbone freezing against task-separate baselines. Using a wireless graph simulator, we prototype both multilayer perceptrons (MLPs) and an edge-aware graph neural network (GNN) encoder trained with FedAvg, and we evaluate localization error, misuser F1-score, and byte-level communication over training rounds. The results show that the GNN-Shared model achieves a 28.9% lower localization error than the MLP-Shared baseline and a 17.7% lower localization error than the GNN-Loc_only baseline, while improving the best misuser F1-score by 2.7% compared with GNN-Mis_only. In terms of communication, the GNN-Shared model reduces the total communication cost by 40.1% compared with MLP-Shared over 40 federated rounds. Additional experiments with FedProx, GraphSAGE, and GAT baselines show that the proposed federated graph-learning framework is flexible across different graph backbones. Multi-seed experiments over five random seeds further confirm the robustness of graph-based federated learning, with GraphSAGE-FedAvg achieving strong average localization and misuser detection performance. Scalability experiments with up to 20 clients, 150 nodes, and different Dirichlet non-IID parameters show that the framework remains stable under larger graph sizes, while communication cost grows mainly with the number of participating clients. To move the framework closer to edge deployment, this paper also introduces a lightweight hardware-oriented GNN-Lite inference prototype with multi-neighbor accumulation, finite-state-machine-based sequential computation, and read-only-memory-based coefficient storage. The prototype achieved timing closure on an Artix-7 field-programmable gate array with 213 LUTs, 111 FFs, 18 DSPs, 0 BRAMs, and 0.106 W estimated total on-chip power. The dynamic power was only 0.001 W, and the estimated total energy consumption was 10.6 nJ per inference. Overall, the results show that federated graph learning is a promising direction for wireless edge intelligence, and that different graph backbones can be selected depending on the target trade-off among localization accuracy, misuser detection performance, communication cost, robustness, and hardware deployment. Full article

Black tea quality is governed by aroma chemistry: terpene alcohols (linalool, geraniol, nerolidol), methyl salicylate, and short-chain aldehydes whose abundance and release kinetics from the polyphenol-rich leaf matrix shape perceived grade. Grade information lies not only in the average headspace concentration but in the temporal shape of volatile organic compound (VOC) release under controlled heating. Conventional electronic noses obscure this signal: they rely on multi-sensor arrays, compress each response into summary statistics, and report accuracy only at the level of individual measurements. Whether a single low-cost metal–oxide–semiconductor (MOS) gas sensor can recover grade-defining aroma chemistry, and whether waveform-level modeling can exploit it, was therefore investigated. A portable electronic nose built around a Bosch BME688 sensor recorded 90 time series, each comprising four directly measured channels (temperature, humidity, pressure, gas sensor resistance) and a derived indoor-air-quality (IAQ) proxy computed from them by the on-chip BSEC library, from 16 commercial Turkish black teas across three quality grades. Two representations were compared on the same data: a feature-based pipeline reducing 25 statistical descriptors to seven principal components for six classifiers (best F1-macro = 0.624, MLP), and a raw-waveform Multi-Scale 1D-CNN with Squeeze–Excitation and temporal self-attention (MS-CNN-Attention). Under product-grouped cross-validation, the deep model reached F1-macro = 0.811 (+30%) and graded 14 of 16 products correctly by majority vote, against 11 of 16 for the MLP, with the largest gain in the medium grade (F1: 0.52 → 0.79), where summary-statistic compression destroys the release-kinetic signal. The contributions are threefold: one programmable MOS sensor operated as a thermal-desorption profiler rather than a sensor array; a direct comparison of feature-based classical learning against raw-waveform deep learning on the same small, non-normally distributed dataset; and a product-level decision-consistency metric suited to batch screening. Pairing a low-cost MOS sensor with waveform-level modeling offers a rapid, non-destructive route to aroma-chemistry-based tea quality screening. Full article

Many machine learning and deep learning algorithms based on Artificial Neural Networks (ANNs) have been implemented on software platforms for handwritten digit and character recognition. However, an ANN is difficult to deploy on an embedded platform based on a Central Processing Unit (CPU) because of its large computation, complex structure, and frequent memory access. However, Field Programmable Gate Array (FPGA) devices facilitate this task and offer the capability to design fully customizable hardware architectures. Additionally, they provide high flexibility and high parallel computations based on parallel processing techniques, and they contain sufficient on-chip Digital Signal Processing (DSP) blocks useful for complicated multiplications. In this paper, we present a detailed FPGA-based implementation of a handwritten digit recognition system based on a Multi-Layer Perceptron (MLP) model. The internal modules of the network are designed using the VHSIC Hardware Description Language (VHDL) to achieve a high-level optimization on the hardware platform, and the functionality is simulated and tested using Vivado ISIM Tools. The system has been characterized to reach acceptable performance compared to previous approaches. After implementing the whole neural network on a Xilinx Pynq-Z2 board, it occupies in the device 20758 LUTs, 4426 FFs, 3.50 blocks of random-access memory (BRAM), and 42 DSPs. It reaches an execution time of 2.192 µs to recognize a handwritten number, while consuming only 0.36 Watts, and it achieves a classification accuracy of 97%. Additionally, the proposed architecture can be easily scaled on different FPGA devices thanks to its regularity. Therefore, it offers more portability of the architecture and can be used on different real embedded applications. Full article

The pervasive contamination of aquatic environments by microplastic particles necessitates the development of rapid, cost-effective and field-deployable detection methodologies to complement established but laboratory-bound spectroscopic techniques such as Fourier-transform infrared and Raman microscopy. The demand for field-suitable methods with a broad accessibility comes from researchers themselves. In this review we systematically examine recent advances in optical methods for microplastics identification with a particular emphasis on birefringence as a key diagnostic feature of partially crystalline synthetic polymers. In particular, we analyze three complementary technological directions: liquid crystal-based sensors that exploit orientational order disruptions at interfaces for label-free microplastics detection; polarization holographic imaging combined with machine learning for high-throughput particle classification; and on-chip polarization light microscopy enabling compact and portable analyzing systems. Liquid crystal platforms demonstrate exceptional sensitivity to submicron particles and enable real-time visualization of microplastics aggregation at aqueous interfaces, though they currently lack polymer-specific chemical identification. Conversely, smart polarization holography integrated with Stokes polarimetry and deep learning algorithms achieves over 90% accuracy in distinguishing microplastics from natural particles while processing up to 10,000 particles per minute. Emerging on-chip polarized light microscopy offers a pathway toward miniaturized, low-cost devices suitable for field applications. By synthesizing insights from foundational studies, this review identifies convergent interdisciplinary trends—particularly the integration of artificial intelligence with multimodal optical imaging—and outlines persistent challenges including standardization, interference from natural organic matter, and the transition from laboratory prototypes to robust field-deployable instruments. The systematization of birefringence-based approaches aims to guide future research towards integrated monitoring systems capable of addressing water quality concerns. Full article

This paper introduces a hardware/software co-designed 3D object detection pipeline based on the PointPillars architecture for low-power embedded MPSoC deployment. The proposed system accelerates the computationally intensive stages in programmable logic (PL), including ROI filtering, coordinate transformation, pillarization, centroid extraction, and INT8 neural inference, using Vitis high-level synthesis (HLS) and an integrated Deep Learning Processing Unit (DPU). Control-oriented and irregular operations, such as data acquisition, Direct Memory Access (DMA) control, lightweight Non-Maximum Suppression (NMS), visualization, and logging, remain on the processing system (PS). The design targets the AMD Kria KV260 platform and achieves an accelerated core pipeline latency of 11.4 ms per frame at 300 MHz, corresponding to 87.4 Hz throughput, with 6.842 W board-level power consumption. Including PS-side NMS, the practical end-to-end latency is approximately 12.2 ms for typical KITTI scenes. Compared with existing Field-Programmable Gate Array (FPGA)-based implementations implementations, the proposed design reduces latency by up to $33\times$. It achieves a $202\times$ improvement in on-chip BRAM efficiency across HLS optimization versions through FIFO streaming, dataflow execution, and array partitioning. Experimental validation on physical hardware confirms that the proposed PL-accelerated hardware/software co-design provides a practical and cost-effective solution for real-time 3D LiDAR perception on embedded FPGA platforms. Full article

Federated edge learning on microcontrollers (MCUs) enables privacy-preserving adaptation, but on-device training faces a hardware tradeoff: fitting backpropagation into a limited static random-access memory (SRAM) often relies on on-chip flash as auxiliary storage, while repeated parameter persistence rapidly consumes finite program/erase (P/E) endurance. This paper proposes TinySLFL, a flash-endurance-aware federated learning framework for resource-constrained MCUs. On the client, layer-wise training bounds the peak SRAM usage to one layer, and delayed aggregation keeps intermediate updates in SRAM so that each communication round incurs only one flash persistence. On the server, dynamic aggregation combines loss-aware freezing with proxy-accuracy-guided filtering to improve the robustness under non-independently and identically distributed (Non-IID) data while suppressing unnecessary rounds. Experiments on CIFAR-10 and SVHN under a severe Dirichlet label skew and on a naturally heterogeneous FEMNIST showed, in a server-side simulation, that TinySLFL reduces the cumulative protocol-level erase-block operations (EOs) required to reach a common target accuracy by 97.8–98.6% relative to sequential layer training (SLT) and improves the mean Top-1 accuracy by up to 5.24 percentage points over the same ResNet-8 backbone in a five-seed evaluation. The power, latency, SRAM, and deployment feasibility were reported from actual ESP32-S3 measurements. These results demonstrate durable federated learning for extreme-edge MCUs. Full article

Memristors, as transformative electronic devices designed to transcend the von Neumann architecture, enable the physical unification of information storage and computation, thereby offering a foundational hardware pathway toward energy-efficient, brain-inspired computing. Their intrinsic analog resistive switching, non-volatility, and history-dependent learning capabilities allow them to natively implement in-memory computing and emulate synaptic plasticity, addressing the critical bottlenecks of energy and speed in conventional systems. Notably, the evolution from electrically controlled memristors to optoelectronic memristors marks a paradigm shift from pure computing to integrated sensing-processing, opening new dimensions for high-speed, parallel, and adaptive signal processing. In recent years, significant progress has been made in the development of memristor-based neuromorphic vision and tactile systems, on-chip signal processors, and dynamic trajectory trackers, demonstrating their potential in edge intelligence, adaptive robotics, and real-time perceptual tasks. This review systematically summarizes the latest advances in memristor technology, providing a comprehensive analysis of their operating mechanisms, material and structural innovations, and cutting-edge applications in neuromorphic perception and computing. Furthermore, it discusses the key challenges and future directions for the development and integration of memristor-based systems in the post-von Neumann era. Full article

Low Earth orbit (LEO) satellite networks require real-time routing to cope with dynamic topology variations caused by continuous orbital motion. As an alternative to conventional routing approaches, deep reinforcement learning (DRL) has recently gained attention as an effective means for optimizing routing paths. To solve routing problems modeled as a grid-based Markov decision process (grid-based MDP), DRL methods such as CNN-based Dueling DQN have been proposed. However, these approaches are difficult to implement in practice. In particular, the substantial floating-point computation and memory traffic of CNN inference make real-time onboard inference challenging under the stringent power and resource constraints of satellite platforms. To address these constraints, this paper proposes an INT8 quantization and hardware–software co-design framework using heterogeneous SoC FPGA acceleration. We offload compute-intensive CNN inference to the programmable logic (PL), while the processing system (PS) orchestrates overall control and data movement, forming a collaborative PS–PL architecture. Furthermore, we integrate the NITI-style two-pass scaling with PS–PL exponent propagation to preserve end-to-end integer consistency without floating-point conversion. To demonstrate its practical onboard feasibility, we employ standard accelerator implementation choices—such as output-stationary scheduling and on-chip prefetching—and conduct an ablation study over independently tunable axes (PE array size and PS-side buffer reuse) to quantify their incremental contributions. Experimental results show that the proposed PS–PL cooperative scheme dramatically reduces computation time compared to a PS-only reference implementation on the same platform. Full article

The rapid expansion of the Internet of Things (IoT) has opened resource-limited devices to novel physical threats, such as Side-Channel Attacks (SCAs) and Hardware Trojans (HTs). Traditional security mechanisms are often not capable of standing against such hardware-based attacks, specifically on low-power System-on-Chip (SoC) where static defenses can incur 2× to 3× overhead in silicon area and power. Herein, the gap between hardware security and embedded AI is compositionally formulated for discussion. We present a comprehensive survey of the current hardware threat landscape and analyze the emergence of “Secure-by-Design” paradigms, specifically focusing on the integration of Edge AI and TinyML as active, on-chip intrusion detection mechanisms. This review presents a critical analysis of trade-offs for running lightweight ML models on hardware by comparing state-of-the-art approaches. Our analysis highlights that optimized architectures, such as Mamba-Enhanced Convolutional Neural Networks (CNNs) and Gated Recurrent Unit (GRU), can achieve detection accuracies exceeding 99% against SCA and >92% against stealthy Hardware Trojans, while offering up to 75% lower power consumption compared to standard deep learning baselines. Finally, open challenges such as adversarial attacks on defense models are briefly discussed, and the focus is put on future directions toward constructing secure chips based on robust, AI-driven technology. Full article

This work presents a 6T-SRAM-based in-memory computing (IMC) system fabricated in a 180 nm CMOS technology. A total of 128 integrated polysilicon R2R-DACs for fully analog wordline control and performance analysis are integrated into the system. The proposed architecture enables analog computation directly inside the memory array and introduces a compact 1-bit per-column comparator scheme for energy-efficient classification without requiring ADCs. A dedicated pull-down-dominant SRAM sizing and an analog activation scheme ensure stable analog discharge behavior and precise control of the computation through time-dependent bitline dynamics. The system integrates a complete sensor front-end, which allows real eddy current data to be classified directly on-chip. Measurements demonstrate a performance density of 3.2 TOPS/mm², a simulated energy efficiency of 45 TOPS/W at 50 MHz, and a measured efficiency of 3.4 TOPS/W at 5 MHz on silicon. The implemented online training mechanism further improves classification accuracy by adapting the SRAM cell states during operation. These results highlight the suitability of the presented IMC architecture for compact, low-power edge intelligence and sensor-driven machine learning applications. Full article

Microfluidic cell culture systems and organ-on-a-chip platforms provide powerful tools for modeling physiological processes, disease progression, and drug responses under controlled microenvironmental conditions. These technologies rely on diverse cell culture methodologies, including 2D and 3D culture formats, spheroids, scaffold-based systems, hydrogels, and organoid models, to recapitulate tissue-level functions and generate rich, multiparametric datasets through high-resolution imaging, integrated sensors, and biochemical assays. The heterogeneity and volume of these data introduce substantial challenges in pre-processing, feature extraction, multimodal integration, and biological interpretation. Artificial intelligence (AI), particularly machine learning and deep learning, offers solutions to these analytical bottlenecks by enabling automated phenotyping, predictive modeling, and real-time control of microfluidic environments. Recent advances also highlight the importance of technical frameworks such as dimensionality reduction, explainable feature selection, spectral pre-processing, lightweight on-chip inference models, and privacy-preserving approaches that support robust and deployable AI–microfluidic workflows. AI-enabled microfluidic and organ-on-a-chip systems now span a broad application spectrum, including cancer biology, drug screening, toxicity testing, microbial and environmental monitoring, pathogen detection, angiogenesis studies, nerve-on-a-chip models, and exosome-based diagnostics. These platforms also hold increasing potential for precision medicine, where AI can support individualized therapeutic prediction using patient-derived cells and organoids. As the field moves toward more interpretable and autonomous systems, explainable AI will be essential for ensuring transparency, regulatory acceptance, and biological insight. Recent AI-enabled applications in cancer modeling, drug screening, etc., highlight how deep learning can enable precise detection of phenotypic shifts, classify therapeutic responses with high accuracy, and support closed-loop regulation of microfluidic environments. These studies demonstrate that AI can transform microfluidic systems from static culture platforms into adaptive, data-driven experimental tools capable of enhancing assay reproducibility, accelerating drug discovery, and supporting personalized therapeutic decision-making. This narrative review synthesizes current progress, technical challenges, and future opportunities at the intersection of AI, microfluidic cell culture platforms, and advanced organ-on-a-chip systems, highlighting their emerging role in precision health and next-generation biomedical research. Full article