Search Results (47)

As semiconductor devices approach the sub-10 nm technology node, the self-heating effect (SHE) induced by confined geometries (e.g., FinFETs and nanosheet FETs) has emerged as a critical bottleneck affecting both performance and reliability. This challenge has prompted extensive research efforts to develop advanced characterization methodologies to investigate this effect and its corresponding influence on the device’s reliability issues. In this paper, we propose reflection-based ultra-fast measurement techniques for the continuous monitoring of the self-heating effect in advanced MOSFETs. With this approach, the self-heating effect-induced degradation of transistor drain current and the real-time temperature change can be continuously captured using a digital phosphor oscilloscope on a nanosecond scale. The thermal time constant of 17 ns and the thermal resistance of 34,000 K/W have been extracted for the short channel transistors used in this study with the help of this new characterization method. This reflection-based method is useful for the fast extraction of the thermal time constant and thermal resistance and for the continuous monitoring of current degradation as well as the real-time temperature. Therefore, this new characterization method is beneficial for the evaluation of the self-heating effect in advanced ultra-scaled MOSFETs. Full article

Using novel SiO₂ surface passivation and ultraviolet (UV) light anneal, a 12 nm thick SnO p-type FET (pFET) shows hole effective mobilities (µ_eff) of more than 100 cm²/V·s and 31.1 cm²/V·s at hole densities (Q_h) of 1 × 10¹¹ and 5 × 10¹² cm⁻², respectively. To further improve the on-current/off-current (I_ON/I_OFF), an ultra-thin 7 nm thick SnO nanosheet pFET shows a record-breaking I_ON/I_OFF of 6.9 × 10⁶ and remarkable µ_eff values of ~70 cm²/V·s and 20.7 cm²/V·s at Q_h of 1 × 10¹¹ cm⁻² and 5 × 10¹² cm⁻², respectively. This is the first report of an oxide semiconductor transistor achieving a hole effective mobility µ_eff that reaches 20% of that in single-crystal Si pFETs at an ultra-thin body thickness of 7 nm. In sharp contrast, the control SnO nanosheet pFET without surface passivation or UV anneal exhibits a small I_ON/I_OFF of 1.8 × 10⁴ and a µ_eff of only 6.1 cm²/V·s at 5 × 10¹² cm⁻² Q_h. The enhanced SnO pFET performance is attributed to reduced defects and improved quality in the SnO channel, as confirmed by decreased charges related to sub-threshold swing (SS) and threshold voltage (Vth) shift. Such a large improvement is further supported by the increased Sn²⁺ after passivation and UV anneal, as evidenced by X-ray photoelectron spectroscopy (XPS) analysis. The I_ON/I_OFF ratio exceeding six orders of magnitude, remarkably high hole µ_eff, and excellent two-month stability demonstrate that this pFET is a strong candidate for integration with SnON nFETs in next-generation ultra-high-definition displays and monolithic three-dimensional integrated circuits (3D ICs). Full article

As semiconductor technology and process nodes advance, three-dimensional devices like FinFET and NSFET are increasingly becoming the primary choice, replacing planar MOSFETs. However, the complex manufacturing processes and high process sensitivity of three-dimensional devices at advanced process nodes inevitably cause significant deviations from the ideal structure during actual fabrication, leading to notable changes in their electrical characteristics. This paper investigates the impact of source/drain region height fluctuations caused by etching and epitaxial growth variations on the electrical characteristics of FinFET and NSFET devices, as well as their related circuits. The electrical characteristics when height variations occur in single and multiple electrodes indicate that, although NSFET and FinFET generally exhibit similar properties such as a decrease in the ON-state current when the source/drain height is reduced, the independent nature of the nanosheets in NSFET and the unidirectional conduction of Schottky contact resistance cause significant differences in their electrical characteristics. Additionally, the related circuit-level simulations show that height fluctuations in the source/drain regions of devices can significantly impact circuit characteristics, including voltage and delay, and in severe cases, they may even lead to circuit failure. Full article

Based on the minimum conduction band edge caused by the minimum channel potential resulting from the quasi-3D scaling theory and the 3D density of state (DOS) accompanied by the Fermi–Dirac distribution function on the source and drain sides, a unified semiconductor-device-physics-based ballistic model is developed for the threshold voltage of modern multiple-gate (MG) transistors, including FinFET, Ω-gate MOSFET, and nanosheet (NS) MOSFET. It is shown that the thin silicon, thin gate oxide, and high work function will alleviate ballistic effects and resist threshold voltage degradation. In addition, as the device dimension is further reduced to give rise to the 2D/1D DOS, the lowest conduction band edge is increased to resist threshold voltage degradation. The nanosheet MOSFET exhibits the largest threshold voltage among the three transistors due to the smallest minimum conduction band edge caused by the quasi-3D minimum channel potential. When the n-type MOSFET (N-FET) is compared to the P-type MOSFET (P-FET), the P-FET shows more threshold voltage because the hole has a more effective mass than the electron. Full article

Neural network (NN)-based compact modeling methodologies are gaining attention due to the challenges of device complexity, narrow model coverage, and SPICE simulation speed in advanced semiconductor technology nodes. As device complexity increases, the number of process and structural variables also increases, which significantly increases the amount of technology computer-aided design (TCAD) simulation data required for NN-based compact modeling. This study proposes a multi-fidelity model and active learning approach to predict global and local variations of nanosheet FETs (NSFETs) with less than 1.5% error, significantly reducing the number of required TCAD simulations by more than half compared with conventional modeling techniques. In addition, the simplified NN model with a smaller training dataset significantly reduces the SPICE simulation time. Full article

The scaling of bulk Si-based transistors has reached its limits, while novel architectures such as FinFETs and GAAFETs face challenges in sub-10 nm nodes due to complex fabrication processes and severe drain-induced barrier lowering (DIBL) effects. An effective strategy to avoid short-channel effects (SCEs) is the integration of low-dimensional materials into novel device architectures, leveraging the coupling between multiple gates to achieve efficient electrostatic control of the channel. We employed TCAD simulations to model multi-gate FETs based on various dimensional systems and comprehensively investigated electric fields, potentials, current densities, and electron densities within the devices. Through continuous parameter scaling and extracting the sub-threshold swing (SS) and DIBL from the electrical outputs, we offered optimal MoS₂ layer numbers and single-walled carbon nanotube (SWCNT) diameters, as well as designed structures for multi-gate FETs based on monolayer MoS₂, identifying dual-gate transistors as suitable for high-speed switching applications. Comparing the switching performance of two device types at the same node revealed CNT’s advantages as a channel material in mitigating SCEs at sub-3 nm nodes. We validated the performance enhancement of 2D materials in the novel device architecture and reduced the complexity of the related experimental processes. Consequently, our research provides crucial insights for designing next-generation high-performance transistors based on low-dimensional materials at the scaling limit. Full article

Effective Ohmic contact between metals and their conductive channels is a crucial step in developing high-performance Ga₂O₃-based transistors. Distinct from bulk materials, excess thermal energy of the annealing process can destroy the low-dimensional material itself. Given the thermal budget concern, a feasible and moderate solution (i.e., Ar-containing plasma treatment) is proposed to achieve effective Ohmic junctions with (100) β-Ga₂O₃ nanosheets. The impact of four kinds of plasma treatments (i.e., gas mixtures SF₆/Ar, SF₆/O₂/Ar, SF₆/O₂, and Ar) on (100) β-Ga₂O₃ crystals is comparatively studied by X-ray photoemission spectroscopy for the first time. With the optimal plasma pre-treatment (i.e., Ar plasma, 100 W, 60 s), the resulting β-Ga₂O₃ nanosheet field-effect transistors (FETs) show effective Ohmic contact (i.e., contact resistance R_C of 104 Ω·mm) without any post-annealing, which leads to competitive device performance such as a high current on/off ratio (>10⁷), a low subthreshold swing (SS, 249 mV/dec), and acceptable field-effect mobility (${\mu }_{\mathrm{e}\mathrm{f}\mathrm{f}}$, ~21.73 cm² V⁻¹ s⁻¹). By using heavily doped β-Ga₂O₃ crystals (N_e, ~10²⁰ cm⁻³) for Ar plasma treatments, the contact resistance R_C can be further decreased to 5.2 Ω·mm. This work opens up new opportunities to enhance the Ohmic contact performance of low-dimensional Ga₂O₃-based transistors and can further benefit other oxide-based nanodevices. Full article

The electro-thermal performance of silicon nanosheet field-effect transistors (NSFETs) with various parasitic bottom transistor (tr_pbt)-controlling schemes is evaluated. Conventional punch-through stopper, trench inner-spacer (TIS), and bottom oxide (BOX) schemes were investigated from single-device to circuit-level evaluations to avoid overestimating heat’s impact on performance. For single-device evaluations, the TIS scheme maintains the device temperature 59.6 and 50.4 K lower than the BOX scheme for n/pFETs, respectively, due to the low thermal conductivity of BOX. However, when the over-etched S/D recess depth (T_SD) exceeds 2 nm in the TIS scheme, the RC delay becomes larger than that of the BOX scheme due to increased gate capacitance (C_gg) as the T_SD increases. A higher TIS height prevents the C_gg increase and exhibits the best electro-thermal performance at single-device operation. Circuit-level evaluations are conducted with ring oscillators using 3D mixed-mode simulation. Although TIS and BOX schemes have similar oscillation frequencies, the TIS scheme has a slightly lower device temperature. This thermal superiority of the TIS scheme becomes more pronounced as the load capacitance (C_L) increases. As C_L increases from 1 to 10 fF, the temperature difference between TIS and BOX schemes widens from 1.5 to 4.8 K. Therefore, the TIS scheme is most suitable for controlling tr_pbt and improving electro-thermal performance in sub-3 nm node NSFETs. Full article

Silicon qubits based on specific SOI FinFETs and nanowire (NW) transistors have demonstrated promising quantum properties and the potential application of advanced Si CMOS devices for future quantum computing. In this paper, for the first time, the quantum transport characteristics for the next-generation transistor structure of a stack nanosheet (NS) FET and the innovative structure of a fishbone FET are explored. Clear structures are observed by TEM, and their low-temperature characteristics are also measured down to 6 K. Consistent with theoretical predictions, greatly enhanced switching behavior characterized by the reduction of off-state leakage current by one order of magnitude at 6 K and a linear decrease in the threshold voltage with decreasing temperature is observed. A quantum ballistic transport, particularly notable at shorter gate lengths and lower temperatures, is also observed, as well as an additional bias of about 1.3 mV at zero bias due to the asymmetric barrier. Additionally, fishbone FETs, produced by the incomplete nanosheet release in NSFETs, exhibit similar electrical characteristics but with degraded quantum transport due to additional SiGe channels. These can be improved by adjusting the ratio of the channel cross-sectional areas to match the dielectric constants. Full article

Silicon nanowire field effect (SiNW-FET) biosensors have been successfully used in the detection of nucleic acids, proteins and other molecules owing to their advantages of ultra-high sensitivity, high specificity, and label-free and immediate response. However, the presence of the Debye shielding effect in semiconductor devices severely reduces their detection sensitivity. In this paper, a three-dimensional stacked silicon nanosheet FET (3D-SiNS-FET) biosensor was studied for the high-sensitivity detection of nucleic acids. Based on the mainstream Gate-All-Around (GAA) fenestration process, a three-dimensional stacked structure with an 8 nm cavity spacing was designed and prepared, allowing modification of probe molecules within the stacked cavities. Furthermore, the advantage of the three-dimensional space can realize the upper and lower complementary detection, which can overcome the Debye shielding effect and realize high-sensitivity Point of Care Testing (POCT) at high ionic strength. The experimental results show that the minimum detection limit for 12-base DNA (4 nM) at 1 × PBS is less than 10 zM, and at a high concentration of 1 µM DNA, the sensitivity of the 3D-SiNS-FET is approximately 10 times higher than that of the planar devices. This indicates that our device provides distinct advantages for detection, showing promise for future biosensor applications in clinical settings. Full article

Hafnium disulfide (HfS₂) monolayer is one of the most promising two-dimensional (2D) materials for future nanoscale electronic devices, and patterning it into quasi-one-dimensional HfS2 nanoribbons (HfS₂NRs) enables multi-channel architectures for field-effect transistors (FETs). Electronic, transport and ballistic device characteristics are studied for sub-7 nm-wide and ~15 nm-long zigzag HfS₂NR FETs using non-equilibrium Green’s functions (NEGF) formalism with density functional theory (DFT) and maximally localized Wannier functions (MLWFs). We provide an in-depth analysis of quantum confinement effects on ON-state performance. We show that bandgap and hole transport mass are immune to downscaling effects, while the ON-state performance is boosted by up to 53% but only in n-type devices. Finally, we demonstrate that HfS₂NR FETs can fulfill the industry requirements for future technology nodes, which makes them a promising solution for FET architectures based on multiple nanosheets or nanowires. Full article

The gate-all-around (GAA) nanosheet (NS) field-effect-transistor (FET) is poised to replace FinFET in the 3 nm CMOS technology node and beyond, marking the second seminal shift in device architecture across the extensive 60-plus-year history of MOSFET. The introduction of a new device structure, coupled with aggressive pitch scaling, can give rise to reliability challenges. In this article, we present a review of the key reliability mechanisms in GAA NS FET, including bias temperature instability (BTI), hot carrier injection (HCI), gate oxide (Gox) time-dependent dielectric breakdown (TDDB), and middle-of-line (MOL) TDDB. We aim to not only underscore the unique reliability attributes inherent to NS architecture but also provide a holistic view of the status and prospects of NS reliability, taking into account the challenges posed by future scaling. Full article

As the architecture of logic devices is evolving towards gate-all-around (GAA) structure, research efforts on advanced transistors are increasingly desired. In order to rapidly perform accurate compact modeling for these ultra-scaled transistors with the capability to cover dimensional variations, neural networks are considered. In this paper, a compact model generation methodology based on artificial neural network (ANN) is developed for GAA nanosheet FETs (NSFETs) at advanced technology nodes. The DC and AC characteristics of GAA NSFETs with various physical gate lengths (L_g), nanosheet widths (W_sh) and thicknesses (T_sh), as well as different gate voltages (V_gs) and drain voltages (V_ds) are obtained through TCAD simulations. Subsequently, a high-precision ANN model architecture is evaluated. A systematical study on the impacts of ANN size, activation function, learning rate, and epoch (the times of complete pass through the entire training dataset) on the accuracy of ANN models is conducted, and a shallow neural network configuration for generating optimal ANN models is proposed. The results clearly show that the optimized ANN model can reproduce the DC and AC characteristics of NSFETs very accurately with a fitting error (MSE) of 0.01. Full article

Organic cocrystals, which are assembled by noncovalent intermolecular interactions, have garnered intense interest due to their remarkable chemicophysical properties and practical applications. One notable feature, namely, the charge transfer (CT) interactions within the cocrystals, not only facilitates the formation of an ordered supramolecular network but also endows them with desirable semiconductor characteristics. Here, we present the intriguing ambipolar CT properties exhibited by nanosheets composed of single cocrystals of C₇₀/ferrocene (C₇₀/Fc). When heated to 150 °C, the initially ambipolar monoclinic C₇₀/Fc nanosheet-based field-effect transistors (FETs) were transformed into n-type face-centered cubic (fcc) C₇₀ nanosheet-based FETs owing to the elimination of Fc. This thermally induced alteration in the crystal structure was accompanied by an irreversible switching of the semiconducting behavior of the device; thus, the device transitions from ambipolar to unipolar. Importantly, the C₇₀/Fc nanosheet-based FETs were also found to be much more thermally stable than the previously reported C₆₀/Fc nanosheet-based FETs. Furthermore, we conducted visible/near-infrared diffuse reflectance and photoemission yield spectroscopies to investigate the crucial role played by Fc in modulating the CT characteristics. This study provides valuable insights into the overall functionality of these nanosheet structures. Full article

In this article, the effects of non-ideal cross-sectional shapes of stacked nanosheet FET (NSFET) and nanosheet FET with inter-bridge channel (TreeFET) are studied through calibrated 3D TCAD simulations. The impact of non-ideal cross-sectional shapes on the electrical characteristics due to insufficient/excessive etch processes are investigated in terms of inner spacer (IS), nanosheet (NS) channel, and inter-bridge (IB) channel. Simulation results show that the geometry and material of the IS have significant effects on the performance of the NSFET. Compared with the rectangular inner spacer (RIS), the low-k crescent inner spacer (CIS) enhances the gate control capability while the high-k CIS degrades the drain-induced barrier lowering ($DIBL$) and reduces the gate capacitance ($C_{gg}$). The tapered NS channel improves short-channel effects (SCEs), but sacrifices the driving current. For the TreeFET, considering the fin angle and concave arc, the IB channel can degrade the gate control capability, and SCEs degradation is severe compared to the ideal structure. Therefore, the non-ideal cross-sectional shapes have a significant impact on NSFET-based structure. This research provides development guidelines for process and structure optimization in advanced transistor technology nodes. Full article