Search Results (107)

In this work, we propose an incremental pulse-width erase (IPWE) scheme for fast and variation-tolerant gate-induced drain leakage (GIDL) erase of 3D NAND flash. For the GIDL erase operation, GIDL-generated hole accumulation is required to raise the channel potential. This requirement leads to a transient state that degrades erase speed and broadens distribution of the erased Vth. In addition, the degradation becomes more pronounced with critical-dimension (CD) variation and temperature variation. The proposed IPWE scheme increases erase pulse width progressively, rather than increasing erase voltage as in the conventional incremental step pulse erase (ISPE) scheme. Sentaurus TCAD simulations of a 3D NAND flash with a surrounded BL PAD structure demonstrate that the IPWE scheme achieves a 1.18 V larger Vth shift compared to the ISPE scheme for the same total erase time of 6.6 ms. The IPWE scheme also effectively narrows the erase Vth shift distribution, reducing it by 40 mV under a 55 nm CD variation, 0.26 V for a 10 nm CD variation between channel strings, and 2 V across a 50 K temperature variation, all within a total erase time of 6.6 ms. Full article

NAND flash memory reliability is increasingly challenged by rising data density and frequent program/erase cycles. While Error Correction Codes (ECC) are standard, the simultaneous use of ECC-embedded NAND and ECC-capable host systems is generally avoided due to the risk of unpredictable behavior and file system corruption. Existing studies on the use of dual ECC primarily focus on switching between different ECC structures or adaptive decoding based on error rates and data characteristics. In contrast, this paper introduces a novel driver-level coordination framework that enables the concurrent and integrated operation of two independent ECC mechanisms. By managing the interaction within the Memory Technology Device (MTD) layer, our approach enables the simultaneous utilization of internal NAND ECC and host-side ECC—a combination traditionally considered incompatible. Our approach improves overall system reliability and relaxes product-matching restrictions. Although the solution introduces a minor latency penalty, it is highly effective for applications where data integrity is the primary concern. Experimental results demonstrate that our solution prevents data corruption and extends the lifetime of NAND flash memory. Full article

Solid-State Drives (SSDs) have become the dominant storage medium in performance-sensitive systems due to their high throughput, reliability, and energy efficiency. However, inherent constraints in NAND flash memory—such as out-of-place writes, block-level erase operations, and data fragmentation—necessitate frequent garbage collection (GC), which can significantly degrade user I/O performance when not properly managed. This paper presents a channel-aware GC control mechanism for multi-channel SSD architectures that limits GC concurrency based on real-time storage utilization. Unlike conventional controllers that allow GC to proceed simultaneously across all channels—often leading to complete I/O stalls—our approach adaptively throttles the number of GC-active channels to preserve user responsiveness. The control logic uses a dynamic thresholding function that increases GC aggressiveness only as the SSD approaches full capacity, allowing the system to balance space reclamation with quality-of-service guarantees. We implement the proposed mechanism in an SSD simulator and evaluate its performance under a range of real-world workloads. Experimental results show that the proposed adaptive GC control significantly improves SSD responsiveness across various workloads. Across all workloads, the proposed adaptive GC control achieved an average latency improvement factor of 4.86×, demonstrating its effectiveness in mitigating GC-induced interference. Even when excluding extreme outlier cases, the method maintained an average improvement of 1.55×, with a standard deviation of 1.17, confirming its consistency and robustness across diverse workload patterns. Full article

To satisfy the superior surface quality requirements in the fabrication of HBM (High-Bandwidth Memory) and 3D NAND Flash Memory, high-efficiency Si chemical mechanical planarization (CMP) is essential. In this study, a colloidal silica abrasive-based Si-wafer CMP slurry was developed to simultaneously achieve a high polishing rate (≥10 nm/min) and low surface roughness (≤0.2 nm) without inducing CMP-induced scratches. The proposed Si-wafer CMP slurry incorporates two functional components: triammonium phosphate (TAP) as a hydrolysis reaction accelerator and hydroxyethyl cellulose (HEC) as an abrasive drag force accelerator. The polishing rate enhancement mechanism of TAP was analyzed by monitoring the OH⁻ mol concentration, surface adsorption behavior, and XPS spectra. The results showed that increasing the TAP concentration raised the OH⁻ mol concentration and converted Si–Si and Si–O–Si bonds to Si–OH via a hydrolysis reaction, thereby increasing the polishing rate. However, excessive hydrolysis also led to increased surface roughness. On the other hand, HEC influenced slurry viscosity, abrasive dispersibility, and drag force. At low HEC concentrations, increased abrasive drag force improved the polishing rate. At high concentrations, however, HEC formed a hindrance layer on the Si surface via hydrogen bonding and condensation reactions, reducing the effective contact area of abrasives and thus decreasing the polishing rate. By optimizing the concentrations of TAP (0.0037 wt%) and HEC (≤0.0024 wt%), the proposed slurry formulation achieved high-performance Si-wafer CMP, satisfying both surface roughness and polishing rate targets required for advanced memory packaging applications. Full article

To address the current limitations of spaceborne solid-state storage systems that cannot effectively support the parallel storage of multiple high-speed data streams, the throughput bottleneck of NAND FLASH-based solid-state storage systems was analyzed in relation to the high-speed data input requirements of payloads. A four-stage pipeline operation and bus parallel expansion scheme was proposed to enhance the throughput. Additionally, to support the parallel storage of multichannel data and continuity of pipeline loading, the shortcomings of existing caching schemes were analyzed, leading to the design of a storage system based on Synchronous Dynamic Random Access Memory (SDRAM). Model simulations indicate that, under extreme conditions, the proposed scheme could continuously receive and cache multiple high-speed file data streams into the SDRAM. File data were dynamically written into FLASH based on the priority and status of each partition cache autonomously, without overflow during caching. The system eventually entered a regular dynamic balance scheduling state to achieve parallel reception, caching, and autonomous scheduling of storage for multiple high-speed payload data streams. The data throughput rate of the storage system can reach 4 Gbps, thus satisfying future requirements for multichannel high-speed payload data storage in spaceborne solid-state storage systems. Full article

In this study, we propose a neuromorphic computing system based on a 3D-NAND flash architecture that utilizes analog input voltages applied through wordlines (WLs). The approach leverages the velocity saturation effect in short-channel MOSFETs, which enables a linear increase in drain current with respect to gate voltage in the saturation region. A NAND flash array with a TANOS (TiN/Al₂O₃/Si₃N₄/SiO₂/poly-Si) gate stack was fabricated, and its electrical and reliability characteristics were evaluated. Output characteristics of short-channel (L = 1 µm) and long-channel (L = 50 µm) devices were compared, confirming the linear behavior of short-channel devices due to velocity saturation. In the proposed system, analog WL voltages serve as inputs, and the summed bitline (BL) currents represent the outputs. Each synaptic weight is implemented using two paired devices, and each WL layer corresponds to a fully connected (FC) layer, enabling efficient vector-matrix multiplication (VMM). MNIST pattern recognition is conducted, demonstrated only a 0.32% accuracy drop for the short-channel device compared to the ideal linear case, and 0.95% degradation under 0.5 V threshold variation, while maintaining robustness. These results highlight the strong potential of 3D-NAND flash memory, which offers high integration density and technological maturity, for neuromorphic computing applications. Full article

NAND flash memory has been widely adopted as the primary data storage medium in data centers. However, the inherent characteristic of out-of-place updates in NAND flash necessitates garbage collection (GC) operations on NAND flash-based solid-state drives (SSDs), aimed at reclaiming flash blocks occupied by invalid data. GC processes entail additional read and write operations, which can lead to the blocking of user requests, thereby increasing the tail latency. Moreover, frequent execution of GC operations is prone to induce more pages to be written, further reducing the lifetime of SSDs. In light of these challenges, we introduce an innovative GC scheme, termed SplitGC. This scheme leverages the records of data redundancy gathered during periodic read scrub operations within the SSD. By analyzing these features of data duplication, SplitGC enhances the selection strategy for the victim block. Furthermore, it bifurcates the migration of valid data pages into two phases: non-duplicate pages follow standard relocation procedures, whereas the movement of duplicate pages is scheduled during idle periods of the SSD. The experiment results show that our scheme reduces tail latency induced by GC by 8% to 83% at the 99.99th percentile and significantly decreases the amount of valid page migration by 38% to 67% compared with existing schemes. Full article

The bandgap-engineered tunneling oxide (BE-TOX) structure has been proposed to address the incompatibility between erase efficiency and retention performance in NAND flash memory. Previous studies have primarily focused on single flash memory cells, whose architecture significantly differs from that of 3D NAND flash memory. Thus, the BE-TOX structure requires further research and optimization to improve device performance. In this study, the impact of varying proportions of the SiO₂/SiO_xN_y/SiO₂ (O1/N/O2) structure on performance is investigated using Technology Computer-Aided Design (TCAD) simulations. The results indicate that as the thickness of the N layer increases, the program/erase (P/E) speed improves, but reliability deteriorates. By adjusting the ratio of the O1 and O2 layers, the P/E speed can be optimized, and an optimal thickness can be identified. The simulation results demonstrate that the phenomenon is attributed to the combined effects of different barrier heights for charge tunneling and variations in band bending across the material layers. This study paves the way for further designing BE-TOX structures with balanced P/E performance and reliability. Full article

The rapid expansion of data has made global access easier, but it also demands increasing amounts of energy for data storage and processing. In response, neuromorphic electronics, inspired by the functionality of biological neurons and synapses, have emerged as a growing area of research. These devices enable in-memory computing, helping to overcome the “von Neumann bottleneck”, a limitation caused by the separation of memory and processing units in traditional von Neumann architecture. By leveraging multi-bit non-volatility, biologically inspired features, and Ohm’s law, synaptic devices show great potential for reducing energy consumption in multiplication and accumulation operations. Within the various non-volatile memory technologies available, flash memory stands out as a highly competitive option for storing large volumes of data. This review highlights recent advancements in neuromorphic computing that utilize NOR, AND, and NAND flash memory. This review also delves into the array architecture, operational methods, and electrical properties of NOR, AND, and NAND flash memory, emphasizing its application in different neural network designs. By providing a detailed overview of flash memory-based neuromorphic computing, this review offers valuable insights into optimizing its use across diverse applications. Full article

This work investigates a new erase scheme in NAND flash memory to improve the lifetime and performance of modern solid-state drives (SSDs). In NAND flash memory, an erase operation applies a high voltage (e.g., >20 V) to flash cells for a long time (e.g., >3.5 ms), which degrades cell endurance and potentially delays user I/O requests. While a large body of prior work has proposed various techniques to mitigate the negative impact of erase operations, no work has yet investigated how erase latency and voltage should be set to fully exploit the potential of NAND flash memory; most existing techniques use a fixed latency and voltage for every erase operation, which is set to cover the worst-case operating conditions. To address this, we propose Revisiting Erase Operation, (REO) a new erase scheme that dynamically adjusts erase latency and voltage depending on the cells’ current erase characteristics. We design REO by two key apporaches. First, REO accurately predicts such near-optimal erase latency based on the number of fail bits during an erase operation. To maximize its benefits, REO aggressively yet safely reduces erase latency by leveraging a large reliability margin present in modern SSDs. Second, REO applies near-optimal erase voltage to each WL based on its unique erase characteristics. We demonstrate the feasibility and reliability of REO using 160 real 3D NAND flash chips, showing that it enhances SSD lifetime over the conventional erase scheme by 43% without change to existing NAND flash chips. Our system-level evaluation using eleven real-world workloads shows that an REO-enabled SSD reduces average I/O performance and read tail latency by 12% and 38%, respectivley, on average over a state-of-the-art technique. Full article

The impacts of total ionizing dose (TID) were investigated in 28 nm 3D charge trapping (CT) NAND Flash memories. This study focused on the variations in the raw bit error rate (RBER) of irradiated flash across different operational modes and bias states. It was observed that the data pattern stored in Flash influences the bit error count after irradiation. The experimental findings demonstrated a dose-dependent relationship with standby current, read operation current, and threshold voltage shifts. Additionally, TID was found to affect the time required for erasure and programming operations. These results were then bench-marked against similar NAND Flash devices, revealing superior resistance to TID effects. Full article

Through detailed experimental and modeling activities, this paper investigates the origin of the temperature dependence of the Erase operation in 3D nand flash arrays. First of all, experimental data collected down to the cryogenic regime on both charge-trap and floating-gate arrays are provided to demonstrate that the reduction in temperature makes cells harder to Erase irrespective of the nature of their storage layer. This evidence is then attributed to the weakening, with the decrease in temperature, of the gate-induced drain leakage (GIDL) current exploited to set the electrostatic potential of the body of the nand strings during Erase. Modeling results for the GIDL-assisted Erase operation, finally, allow not only to support this conclusion but also to directly correlate the change with temperature of the electrostatic potential of the string body with the change with temperature of the erased threshold-voltage of the memory cells. Full article

Solid-state drives (SSDs) have become the preferred storage solution for performance-critical applications due to their high speed, durability, and energy efficiency. However, the inherent characteristics of NAND flash memory, such as block-level erasure and data fragmentation, necessitate frequent garbage collection (GC) operations to reclaim storage space. These operations, while essential, introduce significant performance overhead, particularly in modern SSD controllers (SSDCs) that utilize network-on-chip (NoC) architectures. In such architectures, GC requires substantial data transfer over interconnects for error correction, leading to increased latency and reduced throughput. This paper presents a novel GC scheme designed to minimize latency in NoC-based SSDCs. Unlike conventional methods that unconditionally transfer data for error correction, the proposed approach selectively determines the data transfer path based on the presence of errors. By leveraging the low error probability of NAND flash memory, this scheme avoids unnecessary data traversal across the interconnect, significantly reducing GC overhead. A hardware implementation using task queues ensures efficient parallelism without disrupting other operations. The experimental results demonstrate that the proposed scheme improves SSD performance across various real-world workloads, achieving up to a 26.9% reduction in average latency and a 50.0% reduction in peak latency compared to traditional GC methods. These findings highlight the potential of optimizing data traversal paths in NoC architectures, providing a scalable solution for enhancing SSD performance for diverse applications. Full article

To successfully meet the various requirements of modern storage systems, NAND flash memory should be highly optimized by precisely tuning a huge number of internal operating parameters. Although 3D NAND flash memory succeeds in increasing the capacity of storage systems, its complex architecture and unique error behavior make such optimization a more difficult and time-consuming process during NAND manufacturing. In this paper, we introduce HAIPO, a novel methodology for post-fabrication optimization of NAND flash memory, which is an essential step in the manufacturing process of modern 3D NAND flash memory to simultaneously meet various requirements on reliability, performance, yield, etc. HAIPO is based on simple machine-learning approaches that consist of (i) a lightweight deep-learning (DL) model to generate initial device parameters and (ii) an evolutionary algorithm (EA) to explore device parameters automatically. To more effectively explore device parameters, we introduce three key guidelines for each generation in the EA: (1) domain-specific rules, (2) recent optimization results, and (3) online Bayesian simulation, respectively, to enable quick optimization for a huge number of device parameters within the limited product turnaround time (TAT). In addition, we integrate two optimization modules with HAIPO to improve optimization efficiency even in environments with severe process variation. We demonstrate the feasibility and effectiveness of HAIPO using real 320 3D TLC/QLC NAND flash chips, showing significant performance and reliability improvements by up to 8.8% and 12% on average, respectively, within a quite limited optimization TAT. Full article

With vertical stacking, 3D NAND’s flash memory can achieve continuous capacity growth. However, the endurance variation between the stacked layers becomes more and more significant due to process variation, which will lead to the underutilization of many pages and seriously affect the lifetime of 3D NAND’s flash memory. We investigated the endurance variation characteristics between layers and divided the stacked layers into the top, middle, and bottom layers according to the endurance characteristics. We found that the endurance of the bottom layer pages is much weaker than that of the other two layers, which is the primary factor that affects the lifetime of 3D NAND’s flash memory. In response to this endurance variation feature, we proposed a new layer-aware write strategy, called LA-Write. First of all, the write–skip unit in LA-Write will reduce the wear pressure of the pages through write–skip operations. Secondly, LA-Write maintains a layer-aware table, which stores the probability of pages in different layers performing the write–skip operation. Setting the probability of the bottom pages to the highest value will result in more write–skip operations on the bottom layers, mitigating endurance variations between layers. We carried out our experiments of LA-Write on DiskSim, a popular SSD simulator. Compared to existing schemes, experimental results show that LA-Write can greatly increase SSD’s lifetime. Full article