Cache-Based Design of Spaceborne Solid-State Storage Systems
Abstract
:1. Introduction
2. Methodology
2.1. Overall Architecture
2.2. Storage System Functional Module Design
3. Results and Discussion
3.1. Analysis of Storage System Throughput Rate Constraints
3.2. Methods to Improve System Throughput
3.2.1. Pipeline Operation
3.2.2. Bus Parallel Expansion Technology
3.2.3. Caching Scheme Design
3.2.4. Channel Cache Scheduling and Storage Algorithm
Algorithm 1: Channel cache scheduling and storage algorithm. |
Input: ● Cache channel data transfer rates: v1, v2, …, vn. ● Data buffer status for each cache channel: s1, s2, …, sn. ● NAND FLASH working status (WAIT, PROGRAM, WRITE_BACK, ERASE). ● Minimum pipeline threshold K. Output: NAND FLASH data scheduling strategy. |
1 Initialize: Create a queue for each cache channel (vi, si). 2 Sort all cache channels by data transfer rates vi in descending order, then assign file numbers fi (i = 1,2,…,n). 3 for i = n downto 1 do // Poll cache channels from largest to smallest file number. 4 if NAND_Flash.state == FREE then 5 if Si ≥ K then 6 Choose cache channel i firstly with the highest data transfer rate. 7 Store file number fi, read data within the channel in FIFO order. 8 Buffer the data to NAND FLASH. 9 return scheduling strategy: PROGRAM scheduling. 10 else if NAND_Flash.state == WRITE_BACK then 11 Perform data playback operation. 12 return scheduling strategy: WRITE_BACK scheduling. 13 14 else if NAND_Flash.state == ERASE then 15 Perform data erase operation. 16 return scheduling strategy: ERASE scheduling. 17 else 18 Monitor NAND_Flash.state until NAND_Flash.state = FREE. 19 return scheduling strategy: WAIT scheduling. 20 end if 21 End |
3.2.5. Algorithm Complexity Analysis
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- Step 1: Initializing n queues incurs a time complexity of O (n).
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- Step 2: Sorting cache channels by transmission rates using optimal algorithms (e.g., quicksort/mergesort) requires O (n log n) time.
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- Step 3: Iterates through all n cache channels, starting from the maximum file number. Each iteration involves: constant-time conditional checks (Steps 4–18): O (1) per operation.
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- Worst-case: All channels satisfy si < K with persistent FREE NAND status, requiring full traversal: O (n).
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- Best-case: Immediate satisfaction at the first channel (si ≥ K): O (1).
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- Step 1: Queue creation per channel: O (n).
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- Step 2: Sorting auxiliary space (e.g., mergesort): O (n).
- ▪
- All other operations (status evaluation, strategy selection) use constant space: O (1)
3.3. Simulation Validation
- Four-way load with a data rate of 1.2 Gbps, 600 Mbps, 400 Mbps, and 200 Mbps;
- Setting of file number from 1 to 4;
- Continuous input of load data;
- FLASH erase time of 1.5 ms, and 1 ms pipeline write of 4 data clusters;
- No storage failure.
4. Conclusions
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
Abbreviations
SDRAM | Synchronous Dynamic Random Access Memory |
SAR | synthetic aperture radar |
MSI | multispectral imager |
HSI | hyperspectral imager |
DDR | double data rate |
DMA | direct memory access |
SPDK | storage performance development kit |
FPGA | field programmable gate array |
DCM | digital clock manager |
FIFO | First in first out |
RS | Reed–Solomon |
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Argument | Instructions | Time |
---|---|---|
Command loading time | ||
Address loading time | ||
Address to data load interval | ||
Data loading time | ||
Programming latency | 350–560 μs | |
Programming results check time |
Misson | Storage Medium | Capacity | Storage Rate |
---|---|---|---|
Sentinel-2 | NAND FLASH | 2400 Gb | 2 × 540 Mbps |
CSG | SDRAM | 1530 Gb | 2400 Mbps |
SJ-10 | NAND FLASH | 256 Gb | 512 Mbps |
ASO-S | NAND FLASH | 4 Tb | 800 Mbps |
CAS Earth | NAND FLASH | 8 Tb | 2.6 Gbps |
This Work | NAND FLASH | 8 Tb | 4 Gbps |
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Liu, C.; An, J.; Yan, Q.; Dong, Z. Cache-Based Design of Spaceborne Solid-State Storage Systems. Electronics 2025, 14, 2041. https://doi.org/10.3390/electronics14102041
Liu C, An J, Yan Q, Dong Z. Cache-Based Design of Spaceborne Solid-State Storage Systems. Electronics. 2025; 14(10):2041. https://doi.org/10.3390/electronics14102041
Chicago/Turabian StyleLiu, Chang, Junshe An, Qiang Yan, and Zhenxing Dong. 2025. "Cache-Based Design of Spaceborne Solid-State Storage Systems" Electronics 14, no. 10: 2041. https://doi.org/10.3390/electronics14102041
APA StyleLiu, C., An, J., Yan, Q., & Dong, Z. (2025). Cache-Based Design of Spaceborne Solid-State Storage Systems. Electronics, 14(10), 2041. https://doi.org/10.3390/electronics14102041