Search Results (21)

In modern Global Navigation Satellite Systems (GNSS), interleavers are essential for improving system performance. However, limited research has focused on interleaver hardware optimization specifically for GNSS, primarily due to GNSS authorities strictly adhering to Interface Control Documents (ICDs), which discourage significant deviations in hardware implementations. Traditional GNSS interleavers employ double buffering and typically require extensive hardware resources, specifically 2N registers and 2(N$-$ 1) $+$ 1 multiplexers (MUXs), leading to increased complexity, power consumption, and latency. To bridge this gap, this paper presents a novel and efficient interleaver hardware architecture optimized specifically for modern GNSS by leveraging Lifetime Analysis and Forward–Backward Register Allocation. Lifetime Analysis precisely identifies the minimum number of registers necessary, and Forward–Backward Register Allocation ensures efficient utilization of these resources under continuous operation. Experiments were conducted for all seven currently used GNSS interleaving configurations. Synthesis results, obtained using a standard 28 nm Complementary Metal-Oxide Semiconductor (CMOS) process, demonstrate significant reductions in chip area (38.82% reduction), power consumption (52.01% reduction), and latency (25.05% improvement) compared to conventional architectures. These benefits become increasingly critical as the interleaver data length N continues to grow, providing a practical, ICD-compliant solution for resource-constrained satellite payloads and receiver designs. Full article

Molecular quantum-dot cellular automata (QCA) are attracting much attention as an alternative that can improve the problems of digital circuit design technology represented by existing CMOS technology. In particular, they are well suited to the upcoming nanoquantum environment era with their small size, fast switching speed, and low power consumption. In this study, we propose a 5 × 5 × 1 ultra-slim vertical panel type multi-layer 2-to-1 multiplexer (Mux) using molecular QCA, departing from conventional multi-layer formats, and show its expansion to 4-to-1 Mux and application to vertical panel type D-latch and RAM cells. In addition, the polarization phenomenon of cells is physically proven using the potential energy, distance among electrons, and the relative positions of cells, and the secure RAM design takes noise elimination and polarization of the output signal into consideration. The circuits are simulated in terms of operation and performance using QCADesigner 2.0.3 and QCADesignerE, and the proposed multi-layer 2-to-1 Mux shows a significant improvement of at least 1473% and 277% in two representative standard design costs compared to the state-of-the-art multi-layer Muxes. Full article

An energy- and area-efficient non-return-to-zero (NRZ) transmitter with feedforward equalization (FFE) is proposed for an extra-short-reach (XSR) data interface in chiplet-based system in packages (SiPs) and multi-chip modules (MCMs). At the system level, the final-stage 2:1 multiplexer (MUX) in the transmitter is combined with the driver to reduce the hardware and power consumption; at the circuit level, charge-steering-based moderate-swing signal processing further reduces the circuit power consumption and inter-symbol interference. Fabricated in a 28 nm CMOS process with a core area of 0.032 mm², the prototype NRZ transmitter demonstrates an energy efficiency of 0.42 pJ/b at a data rate of 50 Gb/s with an insertion loss of 10 dB, which makes it a promising candidate for XSR die-to-die (D2D) interfaces. Full article

Graph Contrastive Learning (GCL) seeks to learn nodal or graph representations that contain maximal consistent information from graph-structured data. While node-level contrasting modes are dominating, some efforts have commenced to explore consistency across different scales. Yet, they tend to lose consistent information and be contaminated by disturbing features. We propose MUX-GCL, a novel cross-scale contrastive learning framework that addresses these key challenges in GCL by leveraging multiplex representations as effective patches to enhance information consistency. Our method introduces a soft-negative contrasting strategy based on positional affinities to reduce false negatives, thereby minimizing information loss during multi-scale contrasts. While this learning mode minimizes contaminating noises, a commensurate contrasting strategy using positional affinities further avoids information loss by correcting false negative pairs across scales. Extensive downstream experiments demonstrate that MUX-GCL yields multiple state-of-the-art results on public datasets. Our theoretical analysis further guarantees the new objective function as a stricter lower bound of mutual information of raw input features and output embeddings, which rationalizes this paradigm. Full article

Leveraging the rapid carrier recovery times and minimal polarization sensitivity of carrier-reservoir semiconductor optical amplifiers (CR-SOAs), this study embeds them in a Mach–Zehnder interferometer (MZI) setup to emulate a 2x1 multiplexer (MUX) operating at 120 Gb/s. The focus is on incorporating AND logic gate functionalities into the CR-SOAs-based MZI structure to facilitate high-quality multiplexing. The proposed methodology utilizes the intrinsic gain and phase modulation capabilities of CR-SOAs-based MZI to effectively manipulate data streams. This innovative approach capitalizes on the unique properties of CR-SOAs, such as fast response times and low polarization sensitivity, to achieve optimal signal transmission quality and efficient multiplexing. To assess MUX performance, a quality factor metric is introduced as a comprehensive measure of signal integrity. Through exhaustive simulations and meticulous analysis, the study demonstrates the feasibility of achieving the desired data rate while maintaining superior signal transmission quality. The results underscore the efficacy of CR-SOAs-based MZI as versatile modules for high-speed multiplexing applications, offering unparalleled performance and efficiency. This research represents a significant advancement in understanding optical communication systems and provides valuable insights for optimizing signal quality and mitigating interference in practical real-world scenarios. Full article

Several types of silicon-nanowire-based optical demultiplexers (DeMUXs) for use in short-reach targeted datacenter applications were proposed and their spectral responses were experimentally verified. First, a novel 100-GHz-spaced 16λ polarization-diversified optical DeMUX consisting of 2λ delayed interferometer (DI) type interleaver and 8λ arrayed waveguide gratings will be discussed in the spectral regimes of C-band, together with experimental characterizations showing static and dynamic spectral properties. Second, a novel 800-GHz-spaced 8λ optical DeMUX was targeted for use in LR (long reach) 400 Gbps Ethernet applications. Based on multiple cascade-connected DIs, by integrating the extra band elimination cutting area, discontinuous filtering response was analytically identified with a flat-topped spectral window and a low spectral noise of <−20 dB within an entire LR-8 operating wavelength range. Finally, a 20-nm-spaced 4λ coarse wavelength division multiplexing (CWDM)-targeted optical DeMUX based on polarization diversity was experimentally verified. The measurement results showed a low excessive loss of 1.0 dB and a polarization-dependent loss of 1.0 dB, prominently reducing spectral noises from neighboring channels by less than −15 dB. Moreover, TM-mode elimination filters were theoretically analyzed and experimentally confirmed to minimize unwanted TM-mode-oriented polarization noises that were generated from the polarization-handling device. The TM-mode elimination filters functioned to reduce polarization noises to much lower than −20 dB across the entire CWDM operating window. Full article

Wearable medical devices (WMDs) that continuously monitor health conditions enable people to stay healthy in everyday situations. A wristband is a monitoring format that can measure bioelectric signals. The main part of a wearable device is its analog front end (AFE). Wearables have issues such as low reliability, high power consumption, and large size. A conventional AFE device uses more analog-to-digital converters, amplifiers, and filters for individual electrodes. Our proposed MUX-based AFE design requires fewer components than a conventional AFE device, reducing power consumption and area. It includes a single-ended differential feedback operational transconductance amplifier (OTA) and n-pass MUX-based AFE circuits which are related to the emergence of low power, low area, and low cost AFE-integrated chips that are required for wearable biomedical applications. The proposed 6T n-pass multiplexer measures a gain of −68 dB across a frequency range of 100 kHz with a 136.5 nW power consumption and a delay of 0.07 ns. The design layout area is approximately 9.8 µm² and uses 45 nm complementary metal oxide semiconductor (CMOS) technology. Additionally, the proposed single-ended differential OTA has an obtained input referred noise of 0.014 µV_rms, and a gain of −5.5 dB, while the design layout area is about 2 µm² and was designed with the help of the Cadence Virtuoso layout design tool. Full article

Mode multiplexers/demultiplexers (MUX/deMUX) are key components in mode division multiplexing. A silica waveguide mode MUX consisting of four cascaded directional couplers is experimentally demonstrated. The beam propagation method is used in the device design and optimization. Thermal oxidation, plasma-enhanced chemical vapor deposition, and ultraviolet photolithography are adopted in the silica waveguide mode MUX fabrication. The measurement results prove that the input E₀₀ mode can be selectively converted to E₁₀ mode, E₂₀ mode, and E₃₀ mode. Within the wavelength range of 1500 to 1620 nm, the insertion loss is less than 12.2 dB. The proposed mode MUX has good potential in on-chip MDM applications. Full article

Ion-sensitive field-effect transistors (ISFETs) are used as elementary devices to build many types of chemical sensors and biosensors. Organic thin-film transistor (OTFT) ISFETs use either small molecules or polymers as semiconductors together with an additive manufacturing process of much lower cost than standard silicon sensors and have the additional advantage of being environmentally friendly. OTFT ISFETs’ drawbacks include limited sensitivity and higher variability. In this paper, we propose a novel design technique for integrating extended-gate OTFT ISFETs (OTFT EG-ISFETs) together with dual-gate OTFT multiplexers (MUXs) made in the same process. The achieved results show that our OTFT ISFET sensors are of the state of the art of the literature. Our microsystem architecture enables switching between the different ISFETs implemented in the chip. In the case of sensors with the same gain, we have a fault-tolerant architecture since we are able to replace the faulty sensor with a fault-free one on the chip. For a chip including sensors with different gains, an external processor can select the sensor with the required sensitivity. Full article

This work concentrates on the problem of optimizing the cost of a passive wavelength division multiplexing (WDM) optical network used as a transport network for carrying the xHaul packet traffic between a set of remote radio sites and a central hub in a 5G radio access network (RAN). In this scope, we investigate the flexible use of optical add-drop multiplexers (OADMs) for the aggregation of traffic from a number of remote sites, where the type/capacity of optical devices—OADMs and optical multiplexers (MUXs)—is selected in accordance with the traffic demand. The approach is referred to as Flex-O. To this end, we formulate the xHaul network planning problem consisting in the joint provisioning of transmission paths (TPs) between the remote sites and the hub with optimized selection and placement of OADMs on the paths and proper selection of MUXs at the ends of the TPs. The problem formulation takes into accounts the optical power budget that limits the maximum transmission distance in a function of the amount and type of optical devices installed on the TPs. The network planning problem is modeled and solved as a mixed-integer linear programming (MILP) optimization problem. Several network scenarios are analyzed to evaluate the cost savings from the flexible (optimized) use of OADMs. The scenarios differ in terms of the availability of OADMs and the capacity of the WDM devices applied on the TPs. The numerical experiments performed in three mesh networks of different size show that the cost savings of up to between 35 and 45% can be achieved if the selection of OADMs is optimized comparing to the networks in which either single-type OADMs are used or the OADMs are not applied. Full article

This study proposes, designs, and simulates a unique plasmonic Y-shaped MIM waveguide based 2 × 1 multiplexer (MUX) structure utilising opti-FDTD software. Two plasmonic Y-shaped waveguides are positioned facing one another inside a minimum wafer size of 6 µm × 3.5 µm in the 2 × 1 MUX configurations that is being described. The design parameters are adjusted until the plasmonic multiplexer performs as required under optimal conditions. Extinction ratio and insertion loss are two performance metrics that are calculated for performance analysis of the design, which indicate the potential to be applied in plasmonic integrated circuits. Full article

This paper presents a dedicated digital signal process (DSP) for four pulse amplitude modulation (PAM4) SerDes receivers. It is targeted to implement data recovery and adaptive equalization under ultra-high-speed and large channel attenuation with a small area and high power efficiency. The DSP consists of a clock data recovery (CDR), a 16-tap feed forward equalizer (FFE), a 1-tap decision feedback equalizer (DFE), and an automatic adaptation engine. An adaptive least mean square (LMS) algorithm is utilized to make the system more intelligent in calculating tap coefficients of the FFE and DFE. To address the timing limitation associated with traditional digital DFE that cannot handle large amounts of parallel data at a high speed, speculative techniques and a customized 4-to-1 multiplexer (MUX) unit are employed to remove the summation time and reduce the selection time, respectively. A first-order sigma-delta modulator is used to replace the traditional moving average to calculate average voltages, which could prominently save the hardware resources and power consumption. Additionally, the influence of input quantization resolution on the equalization ability is analyzed. Implemented in a 28-nm CMOS, the DSP could compensate for up to 33-dB loss at 100 Gb/s with a power consumption of 7.22 pJ/bit. Full article

This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks—an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm². The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it. Full article

We have simulated a monolithic three-dimensional inverter (M3DINV) structure by considering the interfacial trap charges generated thermally during the monolithic three-dimensional integration process. We extracted the SPICE model parameters from M3DINV structures with two types of inter-layer dielectric thickness T_ILD (=10,100 nm) using the extracted interface trap charge distribution of the previous study. Logic circuits, such as inverters (INVs), ring oscillators (ROs), a 2 to 1 multiplexer (MUX), and D flip-flop and 6-transistor static random-access memory (6T SRAM) containing M3DINVs, were simulated using the extracted model parameters, and simulation results both with and without interface trap charges were compared. The extracted model parameters reflected current reduction, threshold voltage increase, and subthreshold swing (SS) degradation due to the interface trap charge. HSPICE simulation results of the fanout-3 (FO3) ring oscillator considering the interface trap charges showed a 20% reduction in frequency and a 30% increase in propagation delay compared to those without the interface trap charges. The propagation delays of the 2 × 1 MUX and D flip-flop with the interface trap charges were approximately 78.2 and 39.6% greater, respectively, than those without the interface trap charges. The retention static noise margin (SNM) of the SRAM increased by 16 mV (6.4%) and the read static noise margin (SNM) of SRAM decreased by 43 mV (35.8%) owing to the interface trap charge. The circuit simulation results revealed that the propagation delay increases owing to the interface trap charges. Therefore, it is necessary to fully consider the propagation delay of the logic circuit due to the generated interface trap charges when designing monolithic 3D integrated circuits. Full article

Although conventional global navigation satellite systems (GNSS) receivers were originally designed for single signals, studies on multi-signal receiver design have recently been actively conducted to achieve high accuracy, precision, and reliability. However, in order for a multi-signal receiver to support various codes, the receiver should support the generation of individual codes. Therefore, the resulting problem of increased complexity must be solved. This paper proposes a hardware structure for an area-efficient linear feedback shift register (LFSR)-based multi-frequency universal code generator. Whereas the existing universal code generators were configured so that feedback polynomials, output registers, and initial values can be selected by placing read-only memories (ROMs), multiplexers (MUXs), and exclusive ORs (XORs) by register bit, in the case of the proposed universal code generator; the circuit was implemented by applying the hardwiring technique to those register bits that have fixed values. According to the results of field programmable gate array (FPGA) implementation, the proposed LFSR-based universal code generator can improve look up table (LUT) by up to 37% and register by up to 78% when compared to conventional code generators, and LUT by up to 36% when compared to the previous universal code generator. Therefore, the proposed universal code generator is a good candidate for implementing multi-frequency receivers to achieve high precision and high reliability. Full article