Search Results (152)

With the increasing demand for miniaturization, multi-channel RF transceiver capability, and high-speed digital processing in unmanned aerial vehicles, satellite remote sensing, and anti-jamming communication systems, conventional board-level discrete integration schemes face significant limitations in terms of interconnect length, parasitic effects, volume and weight, and electromagnetic compatibility. This paper proposes a high-density integrated RF microsystem packaging scheme based on a 12-layer ABF organic substrate. Within a package size of 37.5 mm × 37.5 mm, the microsystem integrates a digital processing chip, two DDR3 memories, two Flash memories, two broadband RF transceiver chips, and passive components, thereby realizing a 4-receiver/4-transmitter MIMO architecture. Compared with a conventional discrete PCB-based integration scheme, the proposed microsystem reduces the board-level occupied area by approximately 70% and decreases the weight by more than 30%. To address the non-reworkable nature of the in-package DDR3 address/command/clock links and their sensitivity to high-speed signal integrity, a field-circuit co-simulation method combining three-dimensional electromagnetic S-parameter extraction with IBIS models is adopted to optimize the transmission-line impedance and termination parameters under a fly-by topology. The results show that by optimizing the DDR3 clock-line impedance from the conventional 100 Ω differential impedance to 80 Ω differential impedance, and the address/control-line impedance from the conventional 50 Ω single-ended impedance to 40 Ω single-ended impedance, together with 40 Ω and 120 Ω terminations, respectively, overshoot and ringing can be effectively suppressed. The DDR3 eye width is improved from 0.89 ns to 0.92 ns. To address impedance discontinuities in the vertical interconnects of RF channels, a refined structure combining enlarged antipads and accompanying ground vias is proposed. As a result, the worst-case return loss of the RF channel is improved from below 16 dB to 19.69 dB, the maximum insertion loss is reduced from above 0.5 dB to 0.35 dB, and the worst-case inter-channel isolation is improved from below 60 dB to 73.42 dB. To mitigate thermal coupling and localized thermal isolation caused by thickness differences among multiple chips, a locally recessed copper heat spreader is designed, reducing the junction-to-case thermal resistance of the RF chip from 1.25 °C/W to 0.50 °C/W, corresponding to a reduction of approximately 60%. Preliminary hardware-in-the-loop frequency-hopping tests based on the proposed microsystem demonstrate that the system can achieve an analog frequency-hopping rate exceeding 4000 hops/s and a hybrid frequency-hopping rate exceeding 10,000 hops/s. The results indicate that the proposed packaging scheme provides a feasible engineering implementation path for high-density, multi-channel RF microsystem design. Full article

This paper proposes a three-layer adaptive Kalman filter-based multi-source time fusion method for constructing a high-precision, continuous, and robust chip-level time reference. A digitally temperature-compensated TCXO is used as the short-term local time reference, and the Allan variance is introduced to characterize oscillator frequency stability and model the process-noise covariance. For medium-term correction, BeiDou observations are fused with oscillator prediction through an adaptive Kalman filter. A reliability score based on $C/N_0$, DOP, pseudo-range residuals, and other quality indicators is used to dynamically adjust the observation-noise covariance and Kalman gain. When BeiDou signals become unreliable or unavailable, eLoran is introduced as a backup timing source to maintain continuous output. In addition, Kalman filter residuals are fed back to the TCXO temperature-compensation module, forming a closed-loop correction mechanism to suppress residual frequency drift and accumulated timing errors. Experimental results show that the proposed method significantly reduces timing errors and improves continuity, stability, and recovery capability under BeiDou degradation and outage conditions. Full article

Gliomas, and glioblastoma in particular, remain difficult to model because molecular heterogeneity, diffuse invasion, blood–brain and blood–tumour barrier effects, immune suppression and repeated therapeutic escape converge in the same disease. Two-dimensional cultures, glioma stem cell (GSC) systems, acute tumour slices and animal models remain indispensable for mechanistic research, pharmacology and in vivo validation. Glioma organoids are complementary research platforms, not components of routine diagnostic or treatment procedures. This review links model construction, microenvironmental validation, treatment perturbation and evidence-graded interpretation. We compare patient-derived glioma organoids, GSC-derived organoids, brain organoid–glioma co-cultures, genetically engineered brain tumour organoids, and vascular-associated, immune-cell-containing and chip-based platforms. We distinguish phenotypic resemblance from physiological fidelity, tumour-intrinsic drug sensitivity from delivery competence, and proof-of-concept activity from demonstrated clinical utility. We also examine temozolomide resistance, radiotherapy, targeted and combination therapy, antiangiogenic treatment, tumour-treating fields, immune-cell therapy, oncolytic viruses, multi-omic quality control and prospective validation. Organoids should not substitute for animal models or clinical trials. Their most defensible role is to provide a patient-derived functional layer between mechanism, regimen ranking and molecular tumour-board interpretation, with claims limited by assay reproducibility, clinically achievable exposure and outcome linkage. Full article

A plasmonic waveguide coupling cavity structure is proposed, consisting of a bus metal–insulator–metal (MIM) waveguide-coupled single/double D-shaped resonant cavity. The transmission properties, magnetic field distribution, and refractive index sensing performance are simulated using the finite element method (FEM). A clear multi-Fano resonance phenomenon is observed in the transmission spectra. The Fano resonances arise from the interaction between the discrete states of the D-shaped resonant cavity and the continuum state of the bus MIM waveguide. The influence of various structural parameters on the Fano resonance is investigated. Furthermore, the refractive index sensing properties based on the Fano resonance are studied by varying the refractive index of the insulator layer. Maximum sensitivities of 1130 nm/RIU and 1150 nm/RIU are achieved at the fourth Fano resonance dip for the single and double D-shaped resonator cavities, respectively. And a maximum figure of merit of 171 is achieved by the single D-shaped cavity structure. This research can provide new avenues for the design of high-sensitivity sensors as well as novel on-chip sensing structures. Full article

Main memory carries data outside the processor’s trust boundary, so commodity systems-on-chip (SoCs) increasingly encrypt it; yet, in-line memory encryption engine itself becomes a differential power analysis (DPA) target whose key, if recovered, unlocks all of dynamic random-access memory (DRAM). We present PACE, a page-adaptive, cache-anchored memory encryption engine for RISC-V that makes nth-order DPA resistance practical and keeps cryptographic latency off the cache eviction critical path. PACE inserts a TileLink adapter between the last-level cache and the memory port and applies, per physical page, one of four policies (plaintext/confidentiality/confidentiality+integrity/+masking-order-d) selected from RISC-V page table bits through a memory-mapped control plane. Confidentiality uses counter mode whose per-line keystream is precomputed during cache residency; integrity is tree-free at the embedded operating point via on-chip counters and tags, with a live split counter block-MAC Bonsai Merkle tree for scale-out. DPA resistance is layered: ISAP-style fresh re-keying caps the data complexity per key at $q\approx 1$, and domain-oriented masking (DOM, d + 1 shares) protects the sole key processing block to order d. We implement PACE in Chisel on a Rocket SoC (Chipyard) and evaluate it with open-source tooling. A deterministic TileLink-level harness proves ciphertext-in-memory and detects tamper/replay/splice, and the live Tier-B engine (DRAM counters and per-line message authentication codes (MACs) plus an on-chip-rooted block-MAC tree) is validated from end to end on full Rocket and BOOM SoCs and on the FPGA; the masked Ascon-p S-box is proven order-d secure (d = 1, 2) under a glitch- and transition-aware model by three independent formal tools (COCO, PROLEAD, and SILVER, the last also deciding the full composability lattice and confirming exact glitch-robust order-2 probing security), with COCO extending the exact verdict to the highest synthesized order d = 3 (secure at probing orders 1–3); a simulated trace correlation power analysis (CPA) recovers the full key from an unprotected core and is defeated by masking, with a mutual information analysis confirming the $N\propto {\sigma }^{2(d+1)}$ trace amplification law. We further realize PACE on field-programmable gate array (FPGA) silicon: the engine plus an on-chip ring oscillator power sensor is placed, routed, timing-closed at 100 MHz, and programmed on a Xilinx XC7Z020, and we drive a fixed-vs-random Test Vector Leakage Assessment (TVLA) campaign read back entirely over a JTAG (Joint Test Action Group). A multi-core configuration and a Linux control-plane driver are likewise validated. Across synthetic access patterns and named application kernels (AES, SHA-256, matrix multiplication, pointer chasing) on both in-order Rocket and out-of-order BOOM, application-level overhead is within measurement noise of plaintext for cache resident workloads (masking, in particular, is cycle-identical to plain confidentiality), and we characterize the cost of each policy, masking order, and re-keying interval, demonstrating side-channel-hardened memory encryption on open RISC-V hardware. Full article

The microstructure of ternary precursors significantly influences the electrochemical performance of ternary cathode materials and, consequently, the overall performance of lithium-ion batteries. In industrial production utilizing traditional co-precipitation methods, Scanning Electron Microscopy (SEM) is typically employed for particle detection. However, this approach is limited by offline sampling lag, poor representativeness, cumbersome sample preparation, and low efficiency, failing to achieve real-time quality feedback on production lines. To enable high-throughput particle detection, this study proposes a multi-layer PDMS chip designed for three-dimensional (3D) hydrodynamic focusing. The sheath fluid compressed the sample flow in horizontal and vertical directions, respectively, to form a flat ribbon flow passing through the detection area. High-fidelity raw images are captured for automated particle microstructure analysis. Firstly, a chemical pretreatment protocol was optimized to ensure stable precursor solution transport. Secondly, a three-layer composite microchannel featuring a sequential horizontal and vertical sheath-flow compression mechanism was designed, with its geometry optimized via Computational Fluid Dynamics (CFD) simulations. Subsequently, experimental optimizations of flow rate ratios were performed using sodium fluorescein, followed by validation with ternary precursor solutions. The results indicate that the microchannel achieves flattened monolayer focusing of randomly distributed precursor particles, compressing the sample stream height to approximately 15.44 μm, thereby maintaining the particle stream within the microscope’s depth of field and analyzing particle microstructure efficiently based on a microscopic image. Moreover, it is confirmed that the focused stream dimensions are primarily governed by the flow rate ratio, allowing for a flexible increase in detection throughput by adjusting the total flow rate. Different from static offline particle analyzers, this platform captures dynamic particle morphology under continuous flow, providing real-time data to guide co-precipitation reaction adjustment. Full article

To address the challenge of balancing junction temperature prediction accuracy and computational efficiency for high-power multi-chip IGBT modules in automotive applications during complex electro-thermal conversion processes, this study proposes an improved three-dimensional thermal network model based on equivalent power loss injection. Firstly, the effective heat conduction area of each packaging layer under actual heat flow distribution is extracted through three-dimensional finite element simulation, and the single-chip self-heating network parameters are constructed. Secondly, targeting the thermal cross-coupling effect among multiple chips, an elliptical thermal diffusion model is applied to accurately define the thermal coupling region, and a dynamic equivalent power loss compensation mechanism is introduced. Efficient decoupling of multi-heat-source interference is achieved without increasing the state-space dimension of the model. An experimental benchmarking results comparison indicates that the absolute error of junction temperature prediction by this model under steady-state operating conditions is 0.5 °C. Further comparative analysis under the full CLTC-P (China Light-duty Vehicle Test Cycle for Passenger Car) cycle verifies that the improved model not only overcomes the shortcomings of the traditional Foster model, which severely underestimates the transient peak junction temperature and alternating stress amplitude, but also effectively filters out non-physical overshoots caused by short-term ultra-narrow pulses, thus reasonably estimating the device’s maximum junction temperature within the real physical boundary. This method provides efficient theoretical support for accurate dynamic junction temperature predictions and reliability evaluations of electric vehicles under complex operating conditions. Full article

The power density of modern high-power integrated processors keeps rising rapidly. Among them, chiplet-based high-power AI accelerators exhibit local peak heat flux exceeding 1 kW/cm², which leads to concentrated hotspots, severe internal temperature gradients, device performance degradation and reliability deterioration. Conventional heat dissipation approaches are limited by the bottleneck of series interfacial thermal resistance and fail to meet the cooling demands of complex integrated architectures. Chip-level thermal management serves as a core method to suppress hotspots near heat sources and reduce overall system thermal resistance, which guarantees long-term stable operation of high-power integrated processors and plays a vital role in improving the energy efficiency and service life of computing platforms. This paper systematically reviews mainstream chip-level thermal management technologies for high-power integrated processors, covering heterogeneous integration of high-thermal-conductivity substrates, embedded microchannel liquid cooling, solid-state active heat pumps, multi-physics co-design and advanced packaging manufacturing processes. The basic working principles and state-of-the-art research progress of each cooling technology are elaborated in detail. The common engineering bottlenecks, including ultra-high heat flux endurance, packaging process compatibility, fluid leakage risks and multi-layer interfacial thermal resistance, are summarized, and the future development trends of this field are clarified. This review can provide comprehensive theoretical guidance for structural design and large-scale engineering implementation of near-junction thermal management solutions for various high-power integrated processors, especially high-computing-power AI accelerators. Full article

We propose a three-dimensional (3D) integrated optical switch that leverages liquid crystal (LC) birefringence to achieve reconfigurable light routing for particular suitability for quantum optical communication. In our design, the large refractive index contrast between an LC’s ordinary (n_o) and extraordinary (n_e) indices is exploited by using n_o as an effective cladding and n_e as the core of voltage-controlled waveguides. This allows dynamic waveguide formation not only in-plane (horizontal routing on chip) but also vertically through stacked polymer layers, realizing a 3D switching architecture beyond traditional planar photonic circuits. A prototype multi-layer structure on a silicon substrate is described, incorporating alternating polymer cladding and core films with embedded LC cells that act as switchable waveguide segments. Simulations confirm that the LC switch can confine and direct light between different layers with low loss, enabling compact 3 × 3 and potentially up to 10 × 10 port-count switching matrices. The device is electrically driven (no moving parts) and can be operated at low voltages, ensuring compatibility with photonic integrated circuit fabrication. The simulated LC response time on ON/OFF is on the order of 1.1 ms/45 ms, which is slower than MEMS or electro-optic switches, but, however, sufficient for quantum key distribution and other quantum network applications where ultrafast switching is not required. Overall, this LC cell-based 3D optical switch offers a promising route toward scalable, low-loss photonic switching nodes for next-generation quantum communication networks. Full article

DRAM-based in-memory computing integrates computational regions into the main memory, enabling local data processing within the memory, thereby achieving faster and more efficient data computation. However, enhancing system performance requires addressing a critical challenge: achieving more general and sufficiently powerful data processing capabilities within DRAM-PIM. Existing DRAM-PIM implementations often suffer from limited computational capabilities due to the shared standard DRAM package area between memory cells and computational circuits or because the operator circuits are overly customized, which limits their ability to meet required data processing demands. To address this issue, in this paper, we propose a Super Memory Processing Unit (SMPU). The SMPU uses Hybrid Bonding technology to 3D-stack DRAM and many-core computational clusters, enabling large-bandwidth (0.25 TB/s per-bank, 2 TB/s for 8-bank system bandwidth) on-chip data transmission between DRAM and the computational cluster via copper interconnects, effectively breaking the memory wall bottleneck of existing computing architectures. The SMPU constructs a dual-channel fine-grained computational cluster at the logical computing layer, providing flexible and ample computility for various AI models, such as ResNet50 and Llama2. The SMPU uses standard DDR protocols and integrates a new memory space allocation and parsing controller to ensure system compatibility without modifying the host-end hardware, facilitating the integration and invocation of computility in memory particles. Additionally, the SMPU features an independent dual-channel memory-management mechanism within the memory particles, enabling simultaneous multi-channel, multi-modal AI model inference. We compared a CPU system equipped with an SMPU to current computing systems using FPGA simulations. The FPGA simulation results show that, under the same computational configuration, the system with the SMPU improves the performance of ResNet50-v1.5 by up to 5.1× and Llama by up to 27.43× compared to the base system, while reducing system power consumption by 71.6% (ResNet50-v1.5) to 77.8% (Llama 7B). Full article

Radiation monitoring with SRAM-based FPGAs traditionally relies on offset-histogram analysis, which requires a chip-specific calibration campaign at an accelerator before multiple-cell upsets (MCUs) can be discriminated from coincident single-cell upsets (SCUs). The cost and complexity of such calibration restrict the approach to dedicated, beam-test-funded programs. We propose an AI-based on-board classifier that achieves MCU/SCU discrimination directly, without any chip-specific calibration. A lightweight Multi-Layer Perceptron (MLP), trained entirely on synthetic data covering five representative bit-interleaving layouts, is integrated on an AMD Artix-7 XC7A200T FPGA together with per-detection-element telemetry aggregation. The classifier achieves F1 = 0.92–0.97 on structured BRAM layouts when per-chip calibration data are available (calibrated ceiling) and, without any chip-specific calibration, retains F1 up to 0.81 ± 0.02 (held-out, mean over five seeds) on previously unseen layouts with near-perfect recall. A sensitivity analysis across a $20\times$ range of SEU rates and a $4\times$ range of MCU fractions confirms the robustness of the proposed approach. A feature-ablation study identifies an indispensable feature subset, while a comparative evaluation of four alternative classifier architectures (decision tree, support vector machine (SVM), two MLP variants) establishes the reference MLP as the optimal choice. Post-implementation results on the Artix-7 200T show that the MLP-enhanced and calibrated-histogram designs occupy nearly identical FPGA footprints, reframing the choice between them as an operational decision driven by calibration availability rather than by hardware cost. Full article

Field-programmable gate array (FPGA)-based reconfigurable system-on-chip (SoC) platforms are increasingly deployed in safety-critical domains such as autonomous driving and industrial automation, yet the existing literature lacks a systematic assessment of how these designs address functional safety requirements. This paper presents a systematic review of 36 peer-reviewed studies (core period 2010–2024, with historical context from 1998) on FPGA-based reconfigurable parallel processing SoCs, analyzed through three frameworks: a convergence–divergence analysis (CDA) that provides a structured exploratory lens for identifying research trajectory trends and informing hypothesis generation; a safety-critical gap analysis benchmarked against a three-layer standard framework comprising ISO 26262 (functional safety), ISO 21448/SOTIF (safety of the intended functionality), and ISO/PAS 8800 (AI safety properties); and a four-dimensional design space taxonomy spanning reconfigurability granularity, parallelism exploitation, design automation level, and safety criticality. The analysis reveals that 33 of the 36 surveyed studies (92%) ignore safety certification entirely. While recent work has begun establishing worst-case execution time (WCET) bounds for FPGA SoC platforms, none of the surveyed FPGA-based AI accelerator studies provide WCET bounds, although recent analytical models for multi-DPU architectures demonstrate the feasibility of such analysis. FPGA CNN accelerators achieve energy efficiencies of up to 60 GOPS/W, and dynamic partial reconfiguration (DPR) yields 2–5× throughput improvements, yet these gains remain unsupported by the formal verification or uncertainty quantification mandated for safety certification. The CDA framework reveals strong convergence between DPR, network-on-chip (NoC), and high-level synthesis research threads (scores 0.72–0.91), indicating maturation toward integrated design flows. We identify conformal prediction as a distribution-free hardware-compatible framework for uncertainty quantification on resource-constrained FPGAs, motivated by requirements from ISO 21448 (triggering event identification) and ISO/PAS 8800 (runtime confidence monitoring), and propose a prioritized research agenda to bridge the gap between FPGA performance optimization and safety-certified deployment in transportation systems. Full article

Smart manufacturing, Industry 4.0, and cyber-physical systems (CPSs) require sensing architectures capable of resolving both spatially distributed asset behavior and highly localized process states. This review examines optical fiber sensors (OFSs) and integrated photonic sensors for industrial monitoring through a deployment-oriented, multi-scale perspective. The discussion covers five major application regimes: continuous infrastructure surveillance, structural health monitoring (SHM) of load-bearing composites, dynamic condition monitoring of machinery, in situ observability in advanced manufacturing, and localized chemical or gas sensing. Extended fiber-optic networks, including distributed fiber-optic sensing (DFOS) based on Rayleigh, Raman, and Brillouin scattering, together with multiplexed fiber Bragg grating (FBG) sensors, provide passive, embeddable, and remotely interrogated monitoring for large-scale assets and harsh environments. Photonic integrated circuits (PICs) shift transduction to compact node-level devices for localized thermal, mechanical, refractive-index, absorption, vibration, and inertial measurements, while plasmonic and dielectric nanophotonic sensors extend optical monitoring toward surface-selective and chemically specific detection. Across these platforms, digital signal processing (DSP), machine learning (ML), sensor fusion, and digital-twin (DT) coupling are treated as artificial-intelligence-enabled (AI-enabled) layers for signal recovery, inverse mapping, uncertainty reduction, and predictive maintenance. The review argues that scalable industrial adoption is less limited by sensing physics than by the complete deployment chain: packaging, fiber–chip interfacing, calibration stability, interrogation robustness, and AI-enabled data interpretation. This manuscript is structured as a deployment-oriented narrative review of optical fiber and integrated photonic sensors for industrial monitoring and smart manufacturing. Full article

This paper presents a fully integrated E-band (83/95 GHz) diplexer realized in STMicroelectronics’ BiCMOS 55 nm technology. The design directly addresses the critical trade-off between miniaturization and the performance required for high-frequency on-chip systems. The key innovation is a novel patch resonator optimally exploiting the multi-layer structure of the technology’s Back-End-Of-Line. It achieves significant compactness by jointly combining two distinct miniaturization techniques: slotted structures and mushroom-type capacitive loading. This method results in an impressive 77% size reduction compared to conventional designs. Furthermore, we introduce precisely controlled transmission zeros (TZs) to maximize inter-band isolation. The fabricated diplexer achieves a remarkably narrow fractional bandwidth (FBW) of 8.2%—the lowest reported to date for integrated BiCMOS/CMOS E-band implementations—and a robust inter-band isolation exceeding 25 dB, while demonstrating excellent return loss (better than 25 dB). Hence, this work validates a highly compact and scalable approach for integrated E-band transceivers, paving the way for future 6G front-end applications. Full article

Many machine learning and deep learning algorithms based on Artificial Neural Networks (ANNs) have been implemented on software platforms for handwritten digit and character recognition. However, an ANN is difficult to deploy on an embedded platform based on a Central Processing Unit (CPU) because of its large computation, complex structure, and frequent memory access. However, Field Programmable Gate Array (FPGA) devices facilitate this task and offer the capability to design fully customizable hardware architectures. Additionally, they provide high flexibility and high parallel computations based on parallel processing techniques, and they contain sufficient on-chip Digital Signal Processing (DSP) blocks useful for complicated multiplications. In this paper, we present a detailed FPGA-based implementation of a handwritten digit recognition system based on a Multi-Layer Perceptron (MLP) model. The internal modules of the network are designed using the VHSIC Hardware Description Language (VHDL) to achieve a high-level optimization on the hardware platform, and the functionality is simulated and tested using Vivado ISIM Tools. The system has been characterized to reach acceptable performance compared to previous approaches. After implementing the whole neural network on a Xilinx Pynq-Z2 board, it occupies in the device 20758 LUTs, 4426 FFs, 3.50 blocks of random-access memory (BRAM), and 42 DSPs. It reaches an execution time of 2.192 µs to recognize a handwritten number, while consuming only 0.36 Watts, and it achieves a classification accuracy of 97%. Additionally, the proposed architecture can be easily scaled on different FPGA devices thanks to its regularity. Therefore, it offers more portability of the architecture and can be used on different real embedded applications. Full article