On-Chip Diplexer at E-Band 83/95 GHz

Abstract

This paper presents a fully integrated E-band (83/95 GHz) diplexer realized in STMicroelectronics’ BiCMOS 55 nm technology. The design directly addresses the critical trade-off between miniaturization and the performance required for high-frequency on-chip systems. The key innovation is a novel patch resonator optimally exploiting the multi-layer structure of the technology’s Back-End-Of-Line. It achieves significant compactness by jointly combining two distinct miniaturization techniques: slotted structures and mushroom-type capacitive loading. This method results in an impressive 77% size reduction compared to conventional designs. Furthermore, we introduce precisely controlled transmission zeros (TZs) to maximize inter-band isolation. The fabricated diplexer achieves a remarkably narrow fractional bandwidth (FBW) of 8.2%—the lowest reported to date for integrated BiCMOS/CMOS E-band implementations—and a robust inter-band isolation exceeding 25 dB, while demonstrating excellent return loss (better than 25 dB). Hence, this work validates a highly compact and scalable approach for integrated E-band transceivers, paving the way for future 6G front-end applications.

1. Introduction

Diplexers are fundamental components in RF transceiver systems, enabling simultaneous signal transmission and reception with a single antenna. This capability is critical for optimizing the use of communication channels. Diplexers implementation is well-established below 10 GHz, primarily relying on high-performance SAW and BAW filters, which offer excellent quality factors [1].

In contrast, the E-band (60–90 GHz) and beyond present significant challenges. At these frequencies, the physical scaling required for SAW and BAW filters becomes unfeasible due to the limitations of acoustic wavelength and material attenuation. Other traditional solutions, such as metallic waveguide and Low-Temperature Co-fired Ceramic (LTCC) filters are typically employed. Metallic waveguide filters offer high quality factors but they are bulky, heavy, and difficult to integrate with planar technologies like CMOS circuits. This poor compatibility leads to extra interconnection losses. While LTCC is a more cost-effective alternative, its dimensional stability degrades above 50 GHz, making it unsuitable for high-frequency applications. Like waveguides, it also presents integration challenges with CMOS technology [2].

A highly desirable solution is to build diplexers directly into CMOS technology. This allows them to work seamlessly with other CMOS-based parts. Consequently, the design of CMOS-compatible RF filters has become an important research focus. Various strategies have been explored to mitigate the inherent losses of the silicon substrate, including the use of porous Si as a specialized substrate material to enhance RF passive integration [3].

Despite this interest, only a limited number of designs operate effectively beyond 60 GHz [4,5,6,7,8,9,10,11,12,13,14,15]. This is mainly due to the limited quality factor of on-chip transmission lines and the increased difficulty in controlling unwanted electrical effects (parasitic) at such high frequencies. To reduce the inherent losses of the silicon substrate, various distributed and semi-lumped strategies have been explored to implement on-chip millimeter-wave filters. Several designs rely on standard 180 nm and 130 nm CMOS technologies, utilizing shielding techniques such as shielded coplanar waveguides (S-CPW) [4], Thin-Film Microstrip (TFMS) structures [5], and open-loop resonators [9] to isolate electromagnetic fields from the lossy bulk. While the TFMS approach in [5] achieves a highly selective 10% fractional bandwidth (FBW) at 77 GHz, it suffers from a high insertion loss of 9.3 dB. To reduce the physical footprint while maintaining lower insertion losses (2.6–4.1 dB), slow-wave S-CPW topologies [4], grounded pedestal stepped-impedance resonators (SIRs) [6,10,12], and slotted-ground slow-wave structures [11] have been successfully integrated. However, these compact CMOS approaches universally yield much wider bandwidths, typically ranging from 17% to 27%. To navigate this performance trade-off, SiGe BiCMOS technologies have been leveraged. Fully lumped-element configurations utilizing spiral inductors [8] and dual-mode ring resonators with capacitive loading [15] have achieved moderate bandwidths of 15.5% and 11.9%, respectively. More recent advanced BiCMOS designs utilizing spiral resonators with defected ground structures (DGSs) [7], on-chip dual-mode resonators (OCDMRs) [13], and coupled slow-wave coplanar waveguides (CS-CPWs) operating beyond 100 GHz [14] exhibit excellent integration; nonetheless, they inherently result in wide fractional bandwidths spanning 18% to over 29%. Consequently, realizing an E-band filter that simultaneously achieves extreme miniaturization, moderate insertion loss, and a highly selective narrow bandwidth (<10%)—as demonstrated by the 8.2% FBW in this work—remains a significant challenge within a fully integrated silicon process.

Given these challenges, this paper investigates the feasibility of implementing E-band filters (operating between 83 and 95 GHz) using CMOS-compatible patch structures. Patch-based filters have emerged as a promising solution for high-frequency applications, particularly when fabricated with technologies featuring a favorable BEOL process, like STMicroelectronics BiCMOS 55 nm (B55) [16,17,18,19]. The primary limitation of these patch structures is their size; they are about half a guided wavelength long.

While the authors have previously utilized asymmetrical crossed slots to reduce the footprint of standalone dual-mode patch filters at higher sub-terahertz frequencies (e.g., 200 GHz) with a limited size reduction of 25% [17], integrating such resonators into highly selective E-band diplexer architectures requires further architectural evolution. To address the stringent size and isolation constraints of these systems, this paper presents a fully integrated 83/95 GHz diplexer in 55 nm BiCMOS technology that significantly expands upon prior patch resonator designs. The primary contribution of this work is the co-integration of mushroom-type capacitive loading alongside a structurally modified patch resonator within a BiCMOS diplexer architecture. Building upon conventional slotted patch topologies [17], this design modifies the foundational structure by reversing the orientation of the crossed slots and introducing a specific structural perturbation (ΔL). This deliberate breaking of the resonator’s symmetry generates precisely controlled transmission zeros (TZs), which are strategically leveraged to maximize inter-band isolation between the closely spaced TX and RX channels. Furthermore, while the miniaturization in prior slot-only designs [17] was limited to approximately 25%, the first-time introduction of mushroom-type capacitive loading in this diplexer effectively overcomes this constraint. This loading methodology securely confines the physical footprint without perturbing the fundamental even and odd mode field distributions. To achieve the specific 83/95 GHz diplexer integration, these miniaturized TX and RX filters are co-integrated using an optimized matching T-junction. The crucial role of this T-junction is to mathematically ensure proper impedance matching and prevent inter-branch signal leakage between the two closely spaced E-band channels. Ultimately, this system-level integration achieves a core area reduction of approximately 77% compared to a conventional unloaded patch resonator, while satisfying the strict selectivity requirements of the E-band by achieving a fractional bandwidth (FBW) below 10%.

The paper is organized as follows: Section 2 outlines the target specifications, E-band applications, and the overall technology and design methodology. Section 3 presents a comparative performance analysis between patch elements and microstrip lines, along with the detailed diplexer design process. Section 4 discusses the experimental measurement results and loss mechanisms. Finally, conclusions are provided in Section 5.

2. Methodology and Requirements

2.1. Target Specifications and Constraints

The primary objective of this work is to design a fully integrated on-chip diplexer that directly addresses the stringent requirements of E-band transceiver architectures. Operating at millimeter-wave frequencies on a silicon substrate presents inherent challenges, particularly regarding insertion loss and footprint. Therefore, the target specifications are established to achieve a precise balance between miniaturization and high-frequency performance:

• Frequency Spacing: The design must accommodate a 10% to 15% frequency difference between the transmit (TX) channel at 83 GHz and the receive (RX) channel at 95 GHz.
• Inter-band Isolation: To prevent receiver desensitization, the diplexer must guarantee a robust isolation exceeding 25 dB.
• Selectivity: The filters must achieve a narrow fractional bandwidth (FBW) of less than 10%.
• Impedance Matching: A return loss better than 20 dB is required across both channels.

2.2. Applications

The E-band (60–90 GHz and beyond) is a highly attractive spectrum for next-generation communication systems due to the vast amount of available contiguous bandwidth. The diplexer proposed in this work is specifically tailored for future 6G front-end applications, where full CMOS integration is highly desirable to eliminate the cost and interconnection losses associated with hybrid waveguide or LTCC assemblies. Potential deployment scenarios include:

• Ultra-high-capacity wireless backhaul links for 5G/6G cellular networks.
• High-resolution millimeter-wave automotive radar systems.
• High-data-rate point-to-point satellite communications.

2.3. Technology and Design Methodology

The diplexer design is governed by a systematic, multi-stage co-simulation framework utilizing STMicroelectronics’ (Crolles, France) 55 nm BiCMOS (B55) technology, shown in Figure 1. The methodology integrates full-wave 3D electromagnetic (EM) analysis (Ansys HFSS, version 2024 R2, Ansys, Inc., Canonsburg, PA, USA) for passive component synthesis, circuit-level co-simulation (Keysight ADS, version 2025, Keysight Technologies, Inc., Santa Rosa, CA, USA) for system integration, and physical implementation (Cadence Virtuoso, version 2025, Cadence Design Systems, Inc., San Jose, CA, USA) for foundry compliance.

To achieve the target specifications, the design framework establishes the following sequential methodology:

• Resonator Profiling and Selection

  ○

  Establish a baseline: Determine the fundamental building block through comparative electromagnetic (EM) profiling.

  ○

  Construct 3D models: Build competing topologies—specifically, a standard 50 Ω microstrip line and a patch resonator—utilizing the top aluminum layer (AP) and the M6z ground plane.

  ○

  Evaluate performance metrics: Extract the unloaded quality factor (Qu) by sweeping the dielectric height (sub_h) across theoretical limits.

  ○

  Select core topology: Designate the structure yielding the highest Qu within the foundry’s fixed 10 µm BEOL stack as the core resonator.

• Filter Miniaturization Strategy

  ○

  Apply geometric transformations: Implement a two-fold structural modification to the selected patch to satisfy strict footprint constraints.

  ○

  Extend current paths: Force an extension of the surface current path via the parameterization of internal crossed slots.

  ○

  Integrate capacitive loading: Strategically position mushroom-type capacitive structures at the resonator boundaries.

  ○

  Exploit metallization layers: Maximize capacitive loading using the topmost layers (M9v and the thin SiO₂ dielectric), carefully sizing the structures to avoid perturbing the fundamental even and odd mode field distributions.

• Transmission Zero (TZ) Synthesis

  ○

  Break physical symmetry: Synthesize transmission zeros (TZs) for high-isolation filtering by deliberately reversing the slot orientations and introducing an asymmetric geometric perturbation.

  ○

  Couple degenerate modes: Sweep the geometric perturbation parameter to couple degenerate modes within the structure.

  ○

  Shift TZs: Precisely align the resulting TZs to coincide with the adjacent channel’s frequency, maximizing out-of-band rejection.

• Diplexer Integration and Co-Simulation

  ○

  Formulate the network: Execute system-level synthesis via S-parameter co-simulation by importing the EM models of the independently designed TX and RX filters into a circuit simulator.

  ○

  Integrate via T-junction: Connect the filter components using a matching T-junction network.

  ○

  Optimize access lines: Analytically size the connecting access lines to an electrical length of l/4 at their respective center frequencies to ensure proper impedance matching and mitigate inter-branch signal leakage.

• Physical Implementation and Verification Framework

  ○

  Map to physical layout: Enforce physical foundry compliance by translating the optimized schematic into a complete physical layout.

  ○

  Satisfy density rules: Generate the required passive dummy metal fills to adhere to stringent foundry design regulations.

  ○

  Validate physical accuracy: Execute a final, comprehensive 3D EM extraction on the fully populated layout to guarantee that all required specifications hold true under realistic fabrication constraints prior to tape-out.

Having established the target specifications and the overarching co-simulation framework, the following section details the practical execution of this methodology, beginning with an evaluation of the B55 technology’s passive components and culminating in the synthesis of the complete E-band diplexer.

3. Diplexer Design

3.1. Technology Performance

To evaluate the capabilities of STMicroelectronics’ BiCMOS 55 nm (B55) technology for E-band applications, a single patch resonator designed at 90 GHz (Figure 2) was simulated. Its performance was compared to an on-chip 50 Ω microstrip line. Both components were implemented on the aluminum top metal layer (AP) and grounded at the M6z metallic layer. The dielectric height (sub_h) between these layers was used as a key design parameter.

The patch resonator was designed to be weakly coupled to its 50 Ω access lines to minimize loading effects. This setup allowed for the measurement patch’s unloaded quality factor $Q_u$ using (1).

$$Q_u=Q_L={\displaystyle \frac{f_c}{BW}}$$

(1)

where f_c is the center frequency, $Q_L$ is the loaded quality factor, and BW is the 3 dB bandwidth. Similarly, the quality factor of the on-chip 50 Ω microstrip line was calculated using (2):

$$Q_{Tline}={\displaystyle \frac{1}{2}} \times {\displaystyle \frac{\beta }{\alpha }}$$

(2)

where α and β are the attenuation constant and the propagation constant, respectively.

Figure 3 illustrates the simulated quality factors of both the patch resonator and the microstrip line as a function of $su{b}_h$, at 90 GHz. This comparison shows that for $su{b}_h$ below approximately 8 µm, the quality factors of both patch resonator and microstrip line are comparable. However, at greater thickness, the patch resonator exhibits a significantly higher quality factor. The B55 technology used in this study uses a fixed dielectric thickness of 10 µm. The patch’s superior quality factor (17% higher) confirms its effectiveness and justifies its selection for the E-band filter implementation for the diplexer realization.

3.2. TX/RX Patch Filter Design

The conventional patch filter design from [17] was adopted in this work. The design is highly flexible due to the presence of crossed slots. The slots provide both a significant degree of miniaturization and the ability to control the filter’s response [20]. As shown in Figure 4, the original configuration was modified by reversing the orientation of the crossed slots (length $L_s$ and width $W_s$) and introducing a perturbation (${∆}_L$) along line BB’. These modifications were specifically implemented to break the symmetry of the resonator, which, in turn, creates TZs. The TZs were strategically used to enhance the isolation between the channels.

In order to understand the fundamental behavior of the conventional patch resonator, its E-field distribution was analyzed. As illustrated in Figure 5, the even and odd mode field distribution of the conventional patch resonator are concentrated on the edges. This characteristic—the E-field concentration at the edges—is crucial for effective capacitive loading. To achieve further miniaturization, the proposed filter was symmetrically loaded at all four edges with mushroom-type structures (Figure 4). These mushrooms function as identical loading capacitances. The mushroom structures, which have a side length of $L_m$, were carefully implemented to minimize mode perturbation. To maximize the loading capacitance, the top copper layer (M9v) was selected for the mushroom plate, leveraging the thin SiO₂ dielectric layer between the AP and M9v layers, to enhance the capacitance value.

Figure 6 illustrates the simulated filter response. When no mushroom loading is applied ($L_m$ = 0 μm), the filter exhibits an insertion loss of 3 dB with a fractional bandwidth of 10%. In this initial configuration, two transmission zeros (TZs) provide an out-of-band rejection of more than 30 dB. As $L_m$ is varied from 0 to 35 μm, the entire filter response is tuned from a center frequency of 95 GHz down to 83 GHz. This continuous tunability allows for the fabrication of both the transmit (TX) and receive (RX) filters with identical physical dimensions, thereby conserving valuable on-wafer area. The overall filter area is 0.16 mm². Ultimately, the combined effect of the slotted patch and the mushroom-type loading achieves an overall miniaturization with respect to conventional 833 µm patch of:

$$\% Area Reduction = \left(1-{\displaystyle \frac{0.16 {\mathrm{m}\mathrm{m}}^2}{0.694 {\mathrm{m}\mathrm{m}}^2}}\right)\times 100=77\%.$$

(3)

3.3. Proposed E-Band Diplexer

The diplexer was designed to accommodate future E-band applications by incorporating a 13.5% frequency difference between its two channels. The upper channel, Filter 1 (RX), operates at 95 GHz, and the lower channel, Filter 2 (TX), operates at 83 GHz. Both filters were designed to achieve a FBW less than 10% and return loss better than 20 dB.

The final dimensions of the optimized filters constituting the diplexer are: $L_p$ = 400 µm, $L_s$ = 385 µm, ${∆}_L$ = 25 µm and $W_s$ = 10 µm. Both filters have the same physical dimensions. In order to operate at different frequencies without reoptimizing the TX filter dimension, Filter 2 (TX) is capacitively loaded with proposed grounded mushroom while the Filter 1 (RX) does not incorporate any mushrooms. The size of the used mushroom in Filter 2 is $L_m$ = 35 µm. Figure 7 shows the layout of the fabricated diplexer. The design utilizes a T-junction along with access lines designed for an electrical length of λ/4 at $f_{TX}$ and $f_{RX}$, respectively. These elements were optimized to connect the RX and TX branches and maximize inter-band isolation. The overall die area of the diplexer, excluding the measurement pads, is 0.7 mm².

4. Measurement Results and Discussion

On-wafer 4-ports measurements were conducted using Ground-Signal-Ground-Signal-Ground (GSGSG) pads at the input (Port 1 and Port 3) and output ports (Port 2 and Port 4). For the presented diplexer, only single ended input port (Port 1) is activated, while Port 3 is terminated to ground. The output signals are captured such that the TX channel corresponds to Port 4, and the RX channel corresponds to Port 2. Consequently, the measured S-parameters are explicitly defined as follows: the overall input return loss is represented by S11; the TX path insertion and return losses are given by S41 and S44, respectively; and the RX path insertion and return losses are given by S21 and S22, respectively. Finally, the inter-band isolation is evaluated via the transmission coefficient between the two output branches (S24).

A 4-port on-wafer Through-Reflect-Line (TRL) calibration was performed on an Anritsu VectorStar^® ME7838A4 (Anritsu, Atsugi, Japan) Vector Network Analyzer (VNA), covering a frequency range from 70 kHz to 220 GHz. The custom-made TRL calibration kit is shown in Figure 8. The 50-ohm access lines are of length equal to 100 μm. After calibration, those access lines are de-embedded, and the new reference plane is shown in Figure 7 (see black dotted line). The other interconnections are considered part of the diplexer measurements.

The comparison between simulated and measured S-parameters is presented in Figure 9. The measured center frequencies of the TX and RX channels exhibit a 12 GHz separation. This corresponds to a relative separation of approximately 13.5% (relative to the average center frequency), which successfully satisfies the targeted 10–15% design specification. The simulation does not accurately incorporate the extensive dummy metal structures required by the 55 nm BiCMOS technology’s density rules, which is critical for a precise comparison. The measured center frequencies are slightly lower than the simulated values. More notably, a systematic discrepancy in insertion loss of approximately 2 dB can be noted between the measured and simulated results. This loss discrepancy is commonly attributed in the state-of-the-art literature to model inaccuracies of the passive devices at mm-wave frequencies and the unaccounted surface roughness and oxidation of the top metal layer. Several studies, particularly those focused on highly scaled CMOS processes, indicate that the surface roughness of the top metal layers (such as M9v) and the metallization corners can significantly increase conductor losses beyond what standard simulation models (like the simple finite conductivity model used in HFSS) predict at E-band [21]. Furthermore, variations in the effective conductivity of the top metal layer due to thin native oxide layers or process variations can further contribute to the observed discrepancy.

In our case, to rigorously identify the dominant loss mechanisms contributing to the total insertion loss at E-band and to investigate the loss discrepancy, a post-measurement systematic loss breakdown study was conducted using 3D EM simulations in Ansys HFSS.

First, an ideal baseline was established by assigning Perfect Electric Conductor (PEC) boundaries to the patch and vias, excluding all dummy metal fills. Under these ideal conditions, the simulated insertion loss is nearly negligible (approximately 0.08 dB), confirming that the dielectric and substrate losses inherently contribute very little to the overall attenuation.

Second, when the foundry’s nominal copper conductivities are applied to the patch and vias (still excluding dummy fills), the insertion loss increases significantly to 5.2 dB (which is almost the same value obtained in simulation during the pre-layout design phase and plotted as the baseline in Figure 9). This value clearly indicates that finite metallization conductivity and skin-effect losses dominate the filter’s attenuation profile at these frequencies.

Finally, the introduction of the mandatory floating dummy metal fills—which are strictly required to satisfy the B55 technology’s density Design Rule Checks (DRCs)—further increases the simulated insertion loss to 7.5 dB, closely bridging the gap to our measured results. The presence of these dense dummy structures inevitably introduces additional parasitic capacitive loading and localized eddy currents. To minimize these parasitic penalties in the final physical simulation layout, the floating dummies were strategically generated without overlap and restricted to the maximum allowable distance from the active via arrays, adhering closely to DRC limits. Furthermore, the via arrays themselves were rigorously modeled to accurately replicate the fabricated physical structure, ensuring that the final post-measurement EM simulations reliably captured these complex high-frequency loss mechanisms.

Despite the noted insertion loss discrepancy, the measured diplexer exhibits good performance characteristics. Both filters demonstrate robust matching, with the return loss consistently exceeding 25 dB at their respective center frequencies. This excellent matching confirms the efficacy of the proposed mushroom loading and T-junction optimization. The relative bandwidth for both filters is consistently 8.2%. The measured insertion loss is 7.1 dB for the TX path (83 GHz) and 6.4 dB for the RX path (95 GHz). The isolation between the two frequency bands is also robust, measured at better than 25 dB, validating the effectiveness of the T-junction and the controlled transmission zeros (TZs) in separating the two channels.

Direct comparison with published mm-wave diplexers is challenging due to their scarcity in the literature. Therefore, the performance evaluation was conducted against both filters operating above 60 GHz and diplexers fabricated using alternative technologies [22,23,24,25,26], as summarized in

Table 1. CMOS/BiCMOS filters state-of-the-art.

Ref.	Technology	${\mathit{f}}_{\mathit{c}}$ (GHz)	Size (mm2)	IL (dB)	FBW (%)	${\mathit{Q}}_{\mathit{u}}$
[4]	130 nm CMOS	60	0.29	4.1	17	23
[5]	180 nm CMOS	77	0.11	9.3	10	18
[6]	180 nm CMOS	65	0.074	3.4	18.5	14
[7]	130 nm BiCMOS	70.65	0.028	3.1	29.3	18
[8]	130 nm BiCMOS	77.3	-	6.4	15.5	17
[9]	180 nm CMOS	77	0.385	3.5	18.1	26
[10]	130 nm CMOS	79.2	0.081	3.9	22.7	18
[11]	180 nm CMOS	77	0.328	2.9	23	25
[12]	180 nm CMOS	77	0.072	2.9	27	21
[13]	130 nm BiCMOS	75.5	0.072	2.7	38.4	16
[14]	55 nm BiCMOS	115	0.07	7.1	18	17
[15]	250 nm CMOS	61.2	0.32	5	11.9	22
[16]	55 nm BiCMOS	50	0.08	5	23	14
This Work	55 nm BiCMOS	83	0.16	7.1	8.2	27
		95		6.4		31

and

Table 2. mm-wave diplexers state-of-the-art.

Ref.	Technology	${\mathit{f}}_{\mathit{c}}$ (GHz)	Size (mm2)	IL (dB)	FBW (%)
[22]	Liquid Crystal Polymer (LCP)	57/68	22.7	2.5/3	12/15
[23]	SIW	25/27	>1600	2	5.4
[24]	High Precision-Milled	81/95.6	>20	1/1.3	11.6/10.8
[25]	Miller-Machining	61/66	>20	1.1/1.37	2.8
[26]	Metalic Nanowire Membrane (MnM)	67/77	1.2	2.6	13
This Work	55 nm BiCMOS	83/95	0.7	7.1/6.4	8.2

, respectively.

For a more detailed filter comparison, Table 1 summarizes key performance metrics—operating frequency $f_c$ (GHz), size (mm²), relative fractional bandwidth FBW, insertion loss IL (dB), and unloaded quality factor $Q_u$—for several CMOS/BiCMOS filters operating beyond 60 GHz. Usually, $Q_u$ is calculated using the formula proposed in [27] for filters of Butterworth responses as in (4):

$$Q_u=4.343{\displaystyle \frac{\left({\sum }_{i=1}^n{g}_i\right)}{FB{W}_{3\mathrm{dB}}·IL}}$$

(4)

where $g_i$ are the elements of the low-pass prototype of Butterworth filter, $FB{W}_{3\mathrm{dB}}$ is the fractional 3 dB bandwidth, and IL is the insertion loss at mid-band frequency. It should be noted that applying this method for calculating the unloaded quality factor $Q_u$ of the filters referenced in Table 1 is not rigorous, because we must assume concerning the type of filtering function used (it was decided to consider a function of Butterworth type when the function was not indicated by the authors), but also because this type of extraction method has never been used for multi-mode filters, to the authors’ best knowledge. Thus, the unloaded quality factors calculated in this paper must be considered as a simple indicator making it possible to provide additional information to the insertion loss, making it possible to consider the relative bandwidth. Most published works rely on transmission line topologies, which generally feature smaller footprints than patch-based designs. For instance, ref. [13] reported a dual-mode resonator using slow-wave structured microstriplines operating at 77 GHz with a low insertion loss of 2.9 dB but a high FBW of 27%. Similarly, ref. [15] reported an insertion loss of 5 dB and a FBW of 11.9% for a dual-mode ring resonator at 61.2 GHz. In contrast, the filters presented in this article achieve a notably low FBW of 8.2% (for an IL of 7.1 dB (TX) and 6.4 dB (RX), respectively). Achieving such a narrow FBW, which is a primary requirement for E-band diplexers, is inherently challenging and comes at the expense of increased IL. Moreover it records competitive calculated ${\mathrm{Q}}_{\mathrm{u}}$ of 27 and 31 for TX and RX, respectively. With the lowest FBW previously reported for silicon-based integrated millimeter-wave filters being 10% [5] (with an IL of 9.3 dB), the proposed diplexer demonstrates highly competitive selectivity. While certain off-chip and hybrid technologies (such as those referenced in Table 2) can achieve narrower bandwidths, doing so in a fully integrated BiCMOS process presents a significantly greater challenge due to the inherent substrate losses and lower quality factors of on-chip passives.

The core advantage of the proposed work is CMOS integration. Unlike the solutions presented in Table 2, based on SIW, liquid crystal polymer, LTCC or MnM, which require costly hybrid integration interfaces that significantly increase insertion loss, the proposed on-chip CMOS design enables full transceiver integration.

5. Conclusions

This work presents the design and characterization of an E-band diplexer realized in 55 nm BiCMOS technology. To the best of the authors’ knowledge, it marks the first reported CMOS integrated diplexer of its kind. The design utilizes patch-type filters, which provide a higher quality factor compared to microstrip lines. The integration of slot and mushroom structures facilitates dual-mode operation and enables significant patch size reduction. The experimental results show good agreement with EM simulations, although increased insertion loss was observed. These results demonstrate the potential for diplexers at mm-wave frequencies, benefiting from the increase in quality factor.

In terms of future perspectives, patch resonator simulations have been carried out at 150 GHz, i.e., in the D-band. It turns out that the unloaded quality factor $Q_u$ of the patch resonator is significantly improved, reaching 43. This implies that a diplexer designed at 150 GHz would exhibit better performance in terms of insertion loss. Moreover, considering that interconnection with waveguide-type technologies would be even more challenging in the D-band, it appears that the prospect of integrating diplexers such as the one presented in this work is highly relevant for future mm-wave applications starting from the D-band.