FPGA-Based Reconfigurable SoCs for Safety-Critical AI Inference: A Systematic Literature Review

Abstract

Field-programmable gate array (FPGA)-based reconfigurable system-on-chip (SoC) platforms are increasingly deployed in safety-critical domains such as autonomous driving and industrial automation, yet the existing literature lacks a systematic assessment of how these designs address functional safety requirements. This paper presents a systematic review of 36 peer-reviewed studies (core period 2010–2024, with historical context from 1998) on FPGA-based reconfigurable parallel processing SoCs, analyzed through three frameworks: a convergence–divergence analysis (CDA) that provides a structured exploratory lens for identifying research trajectory trends and informing hypothesis generation; a safety-critical gap analysis benchmarked against a three-layer standard framework comprising ISO 26262 (functional safety), ISO 21448/SOTIF (safety of the intended functionality), and ISO/PAS 8800 (AI safety properties); and a four-dimensional design space taxonomy spanning reconfigurability granularity, parallelism exploitation, design automation level, and safety criticality. The analysis reveals that 33 of the 36 surveyed studies (92%) ignore safety certification entirely. While recent work has begun establishing worst-case execution time (WCET) bounds for FPGA SoC platforms, none of the surveyed FPGA-based AI accelerator studies provide WCET bounds, although recent analytical models for multi-DPU architectures demonstrate the feasibility of such analysis. FPGA CNN accelerators achieve energy efficiencies of up to 60 GOPS/W, and dynamic partial reconfiguration (DPR) yields 2–5× throughput improvements, yet these gains remain unsupported by the formal verification or uncertainty quantification mandated for safety certification. The CDA framework reveals strong convergence between DPR, network-on-chip (NoC), and high-level synthesis research threads (scores 0.72–0.91), indicating maturation toward integrated design flows. We identify conformal prediction as a distribution-free hardware-compatible framework for uncertainty quantification on resource-constrained FPGAs, motivated by requirements from ISO 21448 (triggering event identification) and ISO/PAS 8800 (runtime confidence monitoring), and propose a prioritized research agenda to bridge the gap between FPGA performance optimization and safety-certified deployment in transportation systems.

1. Introduction

Deploying artificial intelligence in safety-critical systems, from autonomous vehicles to medical devices, demands more than raw performance. It requires provable guarantees that the system will behave correctly under all operating conditions, including worst-case scenarios [1,2]. Yet the overwhelming majority (over 91%) of FPGA-based AI accelerator studies in our survey ignore safety certification entirely, focusing on average-case throughput rather than the worst-case execution time bounds mandated by functional safety standards. This gap is assessed against a three-layer standard framework: ISO 26262 [1] for functional safety, ISO 21448 [2] for safety of the intended functionality (SOTIF), and ISO/PAS 8800 [3] for AI safety properties—the latter two addressing the unique challenges that neural network inference poses to traditional safety argumentation.

Field-programmable gate arrays (FPGAs) offer a compelling platform for such deployments due to their reconfigurable logic fabric, which enables hardware specialization without the long lead times of application-specific integrated circuits (ASICs). Modern FPGA-based system-on-chip (SoC) designs integrate embedded processors, custom accelerators, and high-bandwidth interconnects on a single device, supporting dynamic partial reconfiguration (DPR) to swap hardware modules at runtime [4]. However, this flexibility introduces verification challenges that traditional software testing cannot address. When hardware changes dynamically, proving functional correctness becomes substantially harder, yet existing surveys treat FPGAs as generic computing platforms rather than safety-critical components requiring systematic analysis [5,6].

The challenge intensifies with convolutional neural network (CNN) inference, where prediction confidence matters as much as accuracy. A driver drowsiness detection system achieving 99% accuracy still fails if it cannot signal uncertainty about edge cases [7,8]. Conformal prediction offers a rigorous framework for uncertainty quantification with finite-sample coverage guarantees [9,10], yet no surveyed work connects this theory to FPGA-based inference. This disconnect between statistical rigor and hardware implementation represents a critical opportunity for research at the intersection of machine learning assurance and reconfigurable computing.

1.1. Research Questions

This review synthesizes evidence from 36 peer-reviewed studies (core period 2010–2024, with historical context from 1998) to address four research questions. These questions were derived from the gap analysis in the FPGA survey literature: existing surveys address individual aspects (DPR architectures [11], CNN acceleration [12], or NoC design [13]) in isolation, but none examines the intersection of reconfigurability, parallel architecture, AI acceleration, and safety certification as a unified design space. RQ1 targets design methodology, RQ2 targets the reconfigurability–verifiability tension unique to DPR-based systems, RQ3 addresses performance–efficiency trade-offs across application domains, and RQ4 connects performance metrics to the safety certification requirements that motivate this work. Together, they span the four dimensions of our design space taxonomy (Section 10). Future reviews could extend this framework with additional questions addressing cybersecurity for reconfigurable hardware, multi-chiplet FPGA architectures, and analog AI accelerators—topics that emerged during our search but fell outside the present inclusion criteria.

• RQ1: What design methodologies enable effective reconfigurable parallel SoCs for safety-critical applications?
• RQ2: How do reconfiguration mechanisms, particularly dynamic partial reconfiguration, facilitate runtime adaptability while maintaining verifiability?
• RQ3: What parallel architectures achieve optimal performance–efficiency trade-offs across CNN acceleration, signal processing, and control applications?
• RQ4: What performance metrics and benchmarks demonstrate the advantages of reconfigurable SoCs, and how do they relate to safety certification requirements?

1.2. Contributions

This review makes three primary contributions and three supporting analyses that, taken together, advance beyond the descriptive summaries offered by existing surveys:

1.

Convergence–Divergence Analysis (CDA) Framework: We present a systematic quantitative framework that maps how different research threads (DPR, NoC, HLS, and CNN acceleration) are evolving toward convergence or diverging into specialization. This framework provides a structured exploratory lens for identifying research trajectory trends and informing hypothesis generation, with confidence levels attached to each convergence classification.

2.

Safety-Critical Gap Analysis: We systematically analyze the surveyed literature against a three-layer functional safety framework (ISO 26262, ISO 21448/SOTIF, and ISO/PAS 8800), identifying that the overwhelming majority of studies ignore safety certification entirely. While recent work has begun establishing WCET bounds for FPGA SoC platforms, none of the surveyed AI accelerator studies provide WCET bounds required for ASIL certification.

3.

Uncertainty Quantification Opportunity: We propose a novel research direction connecting conformal prediction with FPGA-based CNN accelerators for safety-critical inference with calibrated confidence estimates, addressing a gap at the intersection of statistical learning theory and hardware implementation.

4.

Design Space Taxonomy: We organize the surveyed architectures into a four-dimensional taxonomy spanning reconfigurability granularity, parallelism exploitation, design automation level, and safety criticality, providing a structured framework for design decisions and technology selection.

5.

Quantified Research Agenda: We provide a prioritized research agenda with specific problems, proposed approaches, estimated complexity (person-months), and realistic timelines, transforming this survey from passive summary to active research guidance.

6.

Application Case Study: We ground the analysis in a concrete application—driver drowsiness detection—demonstrating how the identified gaps and proposed research directions apply to a real-world safety-critical deployment scenario.

Table 1. Comparison with existing FPGA surveys.

Survey	SoC	DPR	AI/ML	Safety	Studies
Kuon & Rose [6]	✓	–	–	–	N/A
Compton & Hauck [5]	✓	✓	–	–	N/A
Nechi et al. [14]	✓	✓	✓	–	N/A
Capra et al. [12]	–	–	✓	–	N/A
This review	✓	✓	✓	✓	36

positions this review relative to existing FPGA surveys, highlighting the gaps in scope that motivate our work.

Unlike prior surveys that treat FPGAs as generic computing platforms or focus on individual design aspects in isolation, this review systematically benchmarks the literature against functional safety requirements while introducing a quantitative convergence analysis framework.

1.3. Paper Organization

The remainder of this paper is organized as follows. Section 2 establishes the architectural foundations and verification gaps that determine FPGA suitability for safety-critical AI. Section 3 describes our systematic review protocol. Section 4 presents the characteristics of the included studies, including temporal, geographic, and platform distributions. Section 5 provides a thematic analysis across four design dimensions: reconfigurability, interconnect architectures, design automation, and CNN acceleration. Section 6 synthesizes the quantitative performance findings across the surveyed studies. Section 7 provides the safety-critical gap analysis against a three-layer safety framework (ISO 26262, ISO 21448/SOTIF, and ISO/PAS 8800), including the conformal prediction opportunity for uncertainty-aware hardware. Section 8 interprets the principal findings, examines FPGA versus GPU trade-offs, and identifies threats to validity. Section 9 introduces the convergence–divergence analysis framework. Section 10 presents our four-dimensional design space taxonomy. Section 11 proposes a prioritized research agenda with specific problem statements, approaches, and timelines. Section 12 summarizes the key findings and outlines directions for certifiable FPGA-based AI in safety-critical systems.

2. Background: FPGAs for Safety-Critical Systems

This section establishes the architectural foundations and verification challenges that determine FPGA suitability for safety-certified AI deployment. We organize the discussion into two temporal layers—historical context (1998–2009), providing foundational background on DPR and NoC evolution, and core analysis (2010–2024), focusing on the modern AI accelerator era that is the primary subject of this review. For comprehensive FPGA surveys, we direct readers to established references [5,6,14].

2.1. Reconfigurable Architectures and the Safety Context

Field-programmable gate arrays have evolved from simple programmable logic devices into heterogeneous SoC platforms integrating hard processor cores, programmable logic, and dedicated accelerators, driven by the convergence of energy-efficient edge AI, runtime hardware adaptability, and functional safety requirements [14,15]. Figure 1 presents the research timeline from 1999 to 2024 across three distinct phases: early multiprocessor exploration, DPR and NoC maturation, and the current AI/ML acceleration era. Importantly, the early phase (1998–2009) predates both the modern deep learning revolution and the release of ISO 26262 in 2011; these studies are treated as historical context for DPR and NoC evolution rather than evaluated against safety standards that did not exist at the time of their publication.

The 36 surveyed studies (Appendix A) predominantly target AMD Xilinx platforms (72%), with the Zynq UltraScale+ MPSoC being the most common deployment target [16]. The remaining studies target Intel (Altera) FPGAs (11%) [11] or general platforms (17%) [17,18]. Figure 2 illustrates this evidence distribution.

Reconfigurable computing in the surveyed literature operates at three granularity levels. Static architectures (17%) offer no runtime adaptation [19,20]. DPR-enabled architectures (46%) support accelerator swapping [21,22,23]. Multi-grained architectures (37%) combine coarse module swapping with fine-grained overlay updates [23,24,25]. DPR achieves latency reductions up to 90% over full reconfiguration [11]. Yet only 2 of 36 studies address timing isolation requirements mandated by ISO 26262 [26].

2.2. Design Automation and Verification Challenges

The transition to high-level synthesis (HLS) represents a significant productivity shift, achieving 80–100% of manual RTL performance with 3–10× development time reduction [27,28]. Post-2018, the majority of CNN accelerator studies in our corpus employ HLS-based flows (see Section 6). However, HLS abstracts timing details that are essential for worst-case execution time (WCET) analysis. While recent work has begun to address WCET estimation for FPGA SoC platforms [29,30,31], no HLS tool provides built-in WCET guarantees, and adoption by accelerator designers remains limited [32].

Functional safety standards mandate rigorous verification across a three-layer framework: Layer 1—system-level functional safety (ISO 26262 and IEC 61508), addressing hardware faults and systematic failures; Layer 2—performance-level safety of the intended functionality (ISO 21448/SOTIF), addressing specification insufficiencies and performance limitations; and Layer 3—AI-specific safety properties (ISO/PAS 8800), addressing neural network verification, data quality, and runtime confidence monitoring. Verification requirements are amplified by configuration-dependent behavior under DPR, timing variability at reconfigurable region boundaries, and fault propagation from single-event upsets in configuration memory [11,32,33,34]. Our survey quantifies this gap in Section 7.

2.3. Connection to Driver Monitoring Systems

Safety-critical drowsiness detection systems [7,8] must detect drowsiness within 100 ms [35], maintain calibrated confidence across diverse conditions, and operate under strict power budgets (<5 W).

These requirements motivate our analysis of uncertainty quantification methods and their FPGA implementation feasibility, developed in Section 7.

3. Systematic Review Protocol for FPGA-Based Reconfigurable SoC Literature

PRISMA compliance. This systematic review was conducted and reported in accordance with the Preferred Reporting Items for Systematic Reviews and Meta-Analyses (PRISMA) 2020 statement [36]. The completed PRISMA 2020 27-item checklist is provided as Supplementary Material. The review protocol was registered on the Open Science Framework (OSF) prior to formal data extraction. No ethics approval was required as this study is a literature review without human or animal subjects.

3.1. Search Strategy

We performed a comprehensive search using a two-phase strategy. An initial broad discovery phase used Semantic Scholar and OpenAlex databases (covering over 220 million academic papers) with hybrid semantic and keyword-based retrieval to identify candidate search terms and assess the literature landscape. The formal systematic search was then conducted across four electronic databases: Scopus, IEEE Xplore, Web of Science, and ACM Digital Library, selected for their comprehensive coverage of FPGA, embedded systems, and hardware design literature. The formal database search was conducted between 15 January and 28 February 2025. The review protocol was registered retrospectively on the Open Science Framework (OSF) due to the exploratory nature of the initial literature discovery phase.

Search Queries

The following search queries were used to identify relevant studies:

• “FPGA reconfigurable parallel processing SoC design implementation dynamic partial reconfiguration AMD Xilinx Zynq”;
• “FPGA multiprocessor systems reconfigurable architecture parallel computing embedded systems”;
• “dynamic reconfiguration FPGA SoC parallel processing acceleration high-performance computing”;
• “FPGA-based reconfigurable CNN accelerator parallel processing edge computing”;
• “modular FPGA multiprocessor reconfigurable systems-on-chip heterogeneous computing”.

3.2. Inclusion Criteria

Studies were included if they met all of the following criteria:

• Published in peer-reviewed venues (conferences, journals, or technical reports);
• Focus on FPGA-based reconfigurable parallel processing SoC designs;
• Include empirical evaluation or architectural contributions;
• Published between 1999 and 2024;
• Available in English.

3.3. Exclusion Criteria

Studies were excluded if they met any of the following criteria:

• No FPGA implementation (simulation-only or purely theoretical work without hardware results).
• Focused exclusively on software or CPU/GPU implementations without reconfigurable hardware contribution.
• Insufficient architectural detail for data extraction (e.g., missing resource utilization, clock frequency, or target device).
• Duplicate or overlapping studies reporting identical results under different titles.
• Wrong publication type (editorials, tutorials, or non-peer-reviewed preprints).
• Non-English publications.

These criteria were applied sequentially: title/abstract screening used criteria 2, 5, and 6; full-text assessment applied all criteria.

Scope limitation. The requirement for FPGA hardware implementation (criterion 1) excludes simulation-based safety research and formal verification studies that address safety certification without deploying on physical hardware. This scope decision was intentional. Our focus is on design and implementation practices in reconfigurable SoC research, but it may undercount the broader community’s engagement with safety, particularly in the formal methods and simulation-based verification literature. We discuss the implications of this selection bias in Section 12 (Threats to Validity).

3.4. Study Selection

Figure 3 presents the PRISMA 2020 flow diagram summarizing the study selection process.

3.4.1. Identification Phase

The initial search across Scopus (n = 312), IEEE Xplore (n = 268), Web of Science (n = 187), and ACM Digital Library (n = 80) identified a total of 847 records. After removing 203 duplicates, 644 unique records remained for screening.

3.4.2. Screening Phase

Two reviewers (Y.M.H. and R.F.H.) independently screened 644 records at the title and abstract level using the inclusion/exclusion criteria as a shared checklist. Records were excluded if they clearly fell outside the scope (e.g., pure software implementations, non-FPGA hardware, or non-English publications). After screening, 521 records were excluded, leaving 123 articles for full-text assessment.

3.4.3. Eligibility Phase

Each of the 123 full-text articles was independently evaluated by both reviewers against all the inclusion and exclusion criteria. Table 2 summarizes the reasons for exclusion.

3.4.4. Inclusion Phase

A total of 25 papers met all the initial inclusion criteria. An extended search identified 11 additional studies meeting the criteria, including recent work on WCET estimation [30] and time-predictable DNN acceleration [37], bringing the final corpus to 36 studies.

Figure 3. PRISMA 2020 flow diagram showing the study selection process across four phases: identification, screening, eligibility, and inclusion.

Figure 3. PRISMA 2020 flow diagram showing the study selection process across four phases: identification, screening, eligibility, and inclusion.

Table 2. Reasons for full-text exclusion.

Exclusion Reason	Count
No FPGA implementation/simulation only	31
Software or CPU/GPU only (no reconfigurable hardware)	24
Insufficient architectural detail	22
Duplicate or overlapping studies	13
Wrong publication type	8
Total excluded	98

Table 2. Reasons for full-text exclusion.

Exclusion Reason	Count
No FPGA implementation/simulation only	31
Software or CPU/GPU only (no reconfigurable hardware)	24
Insufficient architectural detail	22
Duplicate or overlapping studies	13
Wrong publication type	8
Total excluded	98

3.5. Data Extraction Framework

Data extraction focused on the following variables:

• Design Approach: Describe the specific FPGA-based design methodology, including tools, languages (e.g., VHDL and Verilog), and high-level synthesis used for the reconfigurable SoC.
• Reconfiguration Mechanism: Detail how reconfiguration is achieved, such as dynamic partial reconfiguration (DPR), runtime adaptability, or modular architectures in the parallel processing system.
• Parallel Processing Architecture: Outline the parallel processing elements, such as multiprocessor cores, accelerator units, or task partitioning, implemented on the FPGA SoC.
• Implementation Details: Extract key implementation aspects like target FPGA device (e.g., AMD Xilinx Zynq or Intel (Altera) Stratix), resource utilization (LUTs, BRAM, or DSP), clock frequency, and area efficiency.
• Performance Evaluation: Summarize performance metrics, including throughput, latency, and speedup, compared to non-reconfigurable systems and any benchmarks used.
• Applications and Challenges: Identify targeted applications (e.g., signal processing and AI acceleration) and discuss challenges addressed or limitations in the reconfigurable parallel SoC design.
• Key Findings: Highlight the main contributions, innovations, and conclusions from the paper regarding FPGA-based reconfigurable parallel processing SoCs.

3.6. Synthesis Approach

Thematic analysis was employed to identify patterns and synthesize findings across studies. Evidence strength was assessed based on:

• Consistency of findings across multiple studies;
• Number of supporting studies for each theme;
• Quality of empirical validation;
• Relevance to current FPGA architectures and tools.

Evidence confidence levels were assigned as follows:

• Strong: Consistent findings across 5+ studies with high design quality;
• Moderate: Consistent findings across 2–4 studies with reasonable validation;
• Tentative: Limited evidence or inconsistent findings requiring further research.

3.7. Quality Assessment

Each included study was assessed for methodological quality using a seven-item checklist adapted from established systematic review guidelines:

• Research design clarity: Is the hardware architecture clearly described with implementation details?
• Empirical validation: Does the study include experimental results on physical hardware (not simulation only)?
• Reproducibility: Are sufficient implementation details provided (target device, resource utilization, and clock frequency)?
• Comparison baseline: Is performance evaluated against a meaningful baseline or alternative approach?
• Metric completeness: Are standard metrics reported (throughput, latency, resource utilization, and power)?
• Limitation acknowledgment: Does the study discuss limitations and assumptions?
• Safety relevance: Does the study address or acknowledge safety certification requirements?

Each item was scored as adequate (1), partial (0.5), or inadequate (0), yielding a composite quality score from 0 to 7. Studies scoring below 3.5 were flagged for sensitivity analysis, but none were excluded based on quality alone, consistent with best practices for scoping reviews in engineering. The mean quality score across the 36 included studies was 4.9 (SD = 1.2), indicating moderate overall quality, with particular weakness in safety relevance (mean score 0.4 on item 7).

3.8. Inter-Rater Reliability

Study selection and data extraction were performed independently by two reviewers (Y.M.H. and R.F.H.). Title and abstract screening used the inclusion criteria as a shared checklist, with disagreements resolved through discussion. Full-text assessment was cross-validated: each reviewer independently evaluated all 123 full-text articles against the inclusion criteria, achieving a Cohen’s $\kappa$ of 0.84, indicating strong agreement. Discrepancies (19 cases) were resolved through consensus discussion, with the third reviewer (R.F.C.) serving as arbiter. Data extraction sheets were pilot-tested on a random subset of 5 studies and refined before full extraction. The convergence–divergence analysis scores (Section 9) were independently computed by both extractors, yielding a Pearson correlation of $r=0.96$ across all thread pairs.

4. Results

This section presents a systematic synthesis of the 36 included studies, organized into four subsections: characteristics of the study corpus, thematic findings across five analytical dimensions, cross-study comparative analysis, and evidence quality assessment. Together, these subsections address research questions RQ1–RQ3 by characterizing the design landscape, identifying the dominant approaches and gaps, and evaluating the strength of the available evidence.

4.1. Overview of Study Characteristics

The 36 studies span 25 years of research (1999–2024), reflecting the evolution of FPGA-based reconfigurable parallel systems from early multiprocessor prototypes to modern AI acceleration platforms. Section 6 summarizes the key characteristics of each included study.

The temporal distribution of publications reveals three distinct research phases. During the early phase (1999–2009), studies established fundamental design patterns for FPGA-based multiprocessors and reconfigurable computing, demonstrating feasibility through prototypes for molecular dynamics, embedded systems, and industrial control applications [17,18,19]. The middle phase (2010–2018) saw maturation of dynamic partial reconfiguration (DPR) techniques and network-on-chip (NoC) integration, with increasing emphasis on runtime adaptability, standardized design flows, and coarse-grained reconfigurable architectures [11,21,23,25]. The recent phase (2019–2025) marks a pronounced shift toward AI and machine learning acceleration, edge computing, and energy efficiency optimization, with multiple studies targeting CNN inference, object detection, and deep learning workloads on Zynq-class heterogeneous platforms [16,38,39,40,41,42].

The research contributions span a geographically diverse set of institutions. Approximately 35% of the primary contributions originate from North America, 30% from Europe, and 30% from the Asia-Pacific region, with the remaining 5% distributed across other regions. Major contributing institutions include universities with established FPGA research programs, national laboratories, and industry research divisions from AMD/Xilinx and Intel/Altera. This geographic breadth mitigates potential regional bias, although the predominance of well-resourced institutions suggests that the findings may underrepresent constraints faced by smaller research groups.

The target platform distribution, summarized in

Table 3. Target platform distribution (36 studies).

Platform	Representative Studies	Count	Percentage
AMD Xilinx Virtex family	[19,25]	5	14%
AMD Xilinx Zynq family	[16,22,30,37,41,42,43,44,45,46,47,48,49]	21	58%
Intel (Altera) FPGA	[11]	4	11%
General/unspecified	[17,18,40]	6	17%

, confirms the dominance of AMD Xilinx devices in the reconfigurable computing research ecosystem. The Zynq family alone accounts for 58% of the studies, reflecting the widespread adoption of heterogeneous SoC architectures that combine ARM processors with programmable logic. Intel/Altera platforms represent 11% of the studies, while general or unspecified FPGA targets account for 17%.

4.2. Thematic Findings

4.2.1. Design Approaches for Reconfigurable Parallel SoCs

Design methodologies across the corpus emphasize modular architectures that integrate hardware accelerators, embedded processors, and interconnect networks to exploit multi-level parallelism. The spectrum of approaches range from register-transfer-level (RTL) design for maximum efficiency [19,50] to high-level synthesis (HLS) flows using OpenCL for task-specific partitioning [51], with hybrid approaches combining both paradigms to balance development productivity against performance [16]. Comprehensive FPGA design methodology reviews cover design flows, HLS toolchains, and IP reuse strategies for industrial control [18], while frameworks for modeling and simulating coarse-grained reconfigurable architectures enable early-stage design space exploration [25]. Multi-grained reconfiguration strategies, which combine coarse (full accelerator), medium (overlay), and fine (LUT-level) reconfiguration, have emerged as a particularly versatile design paradigm, exemplified by tools such as IMPRESS for Xilinx 7 Series devices [23]. In the domain of neural network acceleration, resource-multiplexing techniques minimize area overhead while maintaining throughput by time-sharing computational resources across CNN layers [39].

4.2.2. Reconfiguration Mechanisms and Runtime Adaptability

Dynamic partial reconfiguration (DPR) is the dominant mechanism for achieving runtime adaptability in FPGA-based SoCs. DPR enables selective updates to configurable regions—ranging from entire fabric partitions to individual lookup tables—without disrupting the remainder of the system, achieving latency reductions of up to 90% compared to full reconfiguration [11]. In optimized implementations, DPR latency has been reduced to under 10 ms while maintaining steady-state throughput [21]. Modular architectures facilitate runtime adaptability by enabling the swapping of hardware accelerators or the tuning of computational behaviors through overlay-based reconfiguration [22,23]. The use of the Internal Configuration Access Port (ICAP) or processor-controlled DPR provides a flexible mechanism for runtime hardware tailoring [21]. For CNN accelerators specifically, DPR enables adaptive configurations that support mode switching across different network architectures and workload profiles [22,24]. However, despite these demonstrated capabilities, none of the surveyed DPR studies provide worst-case execution time (WCET) analysis of the reconfiguration process itself, a critical omission for safety-critical deployments requiring ASIL-compliant timing guarantees.

4.2.3. Parallel Processing Architectures

Parallel architectures in the reviewed studies feature heterogeneous multiprocessors with task partitioning across processor cores, hardware accelerators, and on-chip interconnect networks, supporting execution granularities from fine- to coarse-grained for diverse workloads [17,19]. NoC-interconnected multiprocessor systems have demonstrated approximately $3\times$ speedup over single-processor baselines [19]. The architectural evolution shows a trajectory from single-FPGA multiprocessors to multi-FPGA clusters employing global interconnect networks for functional unit access in coarse-grained reconfigurable arrays [25]. In AI applications, parallel architectures multiplex resources across CNN layers, enabling concurrent convolution operations through DSP-optimized compute kernels [38,39]. At the distributed scale, systems of up to 12 interconnected Zynq-7020 boards have been configured to execute pipelined neural networks across nodes [16]. While parallel speedup is well established across these studies, the scaling trends are predominantly demonstrated on CNN inference workloads with favorable data-level parallelism. Generalization to irregular workloads or safety-critical task schedules with stringent timing constraints remains largely untested. Sestito et al. extended parallel architectural thinking to systolic arrays with their TrIM architecture for CNN acceleration [40], while Peccia et al. demonstrated the Gemmini accelerator framework on ZCU102 platforms for YOLOv7-based object detection [41].

4.2.4. Implementation Details and Resource Utilization

Implementation targets are concentrated on Xilinx device families, with resource utilization and clock frequencies varying considerably by application domain and device generation. Multiprocessor implementations on Virtex-II Pro devices consume approximately 65% of available LUTs, 40% of BRAM, and 30% of DSP slices at clock frequencies of 100 MHz [19]. DPR-based systems typically utilize 10–50% of LUT resources, with BRAM allocated for buffering and DSP slices dedicated to arithmetic operations, operating at 100–300 MHz depending on the complexity of the reconfigurable region [11]. Resource-multiplexed CNN processors achieve 200 MHz clock rates with per-prediction latencies as low as 340.7 μs [39]. Multi-chip module (MCM) implementations on Zynq UltraScale+ platforms sustain 10 Gbps intra-module link bandwidth [52]. Capsule network accelerators on PYNQ-Z1 platforms demonstrate that emerging neural architectures beyond conventional CNNs can be efficiently mapped to low-cost FPGA boards [42]. Restuccia and Biondi addressed the timing predictability challenge directly, proposing time-predictable DNN execution on Zynq UltraScale+ platforms suitable for ADAS applications where deterministic inference latency is paramount [37]. Despite this variety, quantitative resource reporting remains inconsistent across the corpus, with several studies providing only partial utilization metrics or omitting clock frequency information.

4.2.5. Performance Evaluation and Metrics

Performance evaluation across the included studies reveals substantial speedups and energy efficiency advantages for reconfigurable SoCs over conventional computing platforms, although the heterogeneity of reported metrics complicates direct cross-study comparison. CNN accelerators report throughput in the range of 10–200 GOPS with energy efficiencies of 10–60 GOPS/W depending on model complexity and quantization strategy [38]. DPR-based designs achieve 2–5× speedup over statically configured implementations [11], while task-specific partitioning approaches yield up to 2.8× throughput improvement in multi-tasking scenarios [51]. NoC-interconnected multiprocessors deliver approximately $3\times$ speedup over single-processor systems [19]. However, a notable gap is the absence of standardized inference latency reporting across AI-focused studies, with several works reporting throughput without corresponding latency measurements [38]. This inconsistency in metric selection and reporting granularity limits the feasibility of meta-analytic comparisons and represents a methodological weakness in the field.

4.3. Cross-Study Comparative Analysis

4.3.1. Comparison of Design Approaches

The four principal design approaches observed across the corpus reveal clear trade-offs between productivity and efficiency. RTL-based methods yield the highest performance efficiency at the cost of extended development cycles, whereas HLS-based approaches accelerate design iteration but often sacrifice peak performance. Hybrid strategies that combine HLS for dataflow kernels with RTL for control logic offer a pragmatic middle ground, although they introduce integration complexity. CGRA-based approaches provide computational flexibility through spatial programmability but incur area overhead from the reconfigurable interconnect.

4.3.2. Reconfiguration Granularity Analysis

The reconfiguration granularity employed by a design fundamentally determines the trade-off between flexibility and reconfiguration overhead. The three granularity levels observed across the corpus range from fine-grained parameter tuning to coarse-grained application swapping. Fine-grained reconfiguration at the LUT level enables parameter tuning with reconfiguration times of 1–5 ms but incurs high configuration data overhead. Medium-grained overlay-based approaches balance reconfiguration time (5–20 ms) with algorithm-level flexibility, while coarse-grained module swapping supports application-level changes at the cost of longer reconfiguration latencies (20–100 ms). The choice of granularity is typically driven by the target application’s runtime adaptation requirements: signal processing systems favor fine-grained tuning, while AI inference accelerators tend to employ coarse-grained module switching between network architectures.

4.4. Assessment of Evidence Quality

The methodological rigor of the included studies varies considerably across five quality dimensions: implementation completeness, performance evaluation methodology, reproducibility, comparison baselines, and timing analysis coverage.

Table 4. Study quality assessment framework.

Dimension	High	Medium	Low
Implementation completeness	Working prototype	Simulation only	Conceptual
Performance evaluation	Real measurements	Simulated results	No evaluation
Reproducibility	Open source	Sufficient detail	Insufficient detail
Comparison baseline	Multiple platforms	Single baseline	No comparison

summarizes the quality assessment framework applied to each study.

Applying this framework to the 36 studies reveals a broadly consistent pattern. Studies on DPR mechanisms and parallel architectures generally achieve high marks for implementation completeness as most report working prototypes with measured performance on physical hardware [11,16,19,21]. AI acceleration studies exhibit greater variability: while several report complete implementations with throughput and energy measurements [38,39,41], others provide only simulated results or partial evaluations. Reproducibility remains a persistent concern across the corpus, with only a minority of studies releasing source code or complete design files. The most significant quality gap concerns timing analysis: despite the relevance of FPGA-based systems to real-time and safety-critical applications, only one study [37] provides rigorous WCET analysis for DNN inference, and none of the DPR studies characterize the worst-case timing of the reconfiguration process itself.

The overall confidence in findings varies by thematic area. DPR effectiveness and parallel speedup achieve strong confidence ratings, supported by consistent evidence across eight or more studies with working prototypes. CNN acceleration and energy efficiency findings carry moderate confidence as the evidence is consistent in direction but heterogeneous in measurement methodology. Scalability claims carry only tentative confidence as they are supported by fewer than five studies, most of which evaluate scaling under favorable workload conditions.

5. Thematic Analysis: Design Dimensions

This section synthesizes the findings across four design dimensions—reconfigurable architectures, interconnect topologies, design automation, and AI acceleration—based on the 36 primary studies surveyed in this review. Rather than cataloging individual contributions, we analyze how approaches compare, where trade-offs emerge, and what safety-critical gaps persist.

5.1. Reconfigurability and Runtime Adaptation

Dynamic partial reconfiguration (DPR) enables runtime modification of selected FPGA regions while the remainder continues uninterrupted operation, fundamentally changing deployment models for adaptive systems [11]. Figure 4 illustrates the DPR pipeline from module synthesis through partial bitstream generation to runtime configuration management. However, the surveyed literature reveals a significant gap between demonstrated capabilities and safety-critical requirements.

5.1.1. Reconfiguration Latency and Infrastructure Overhead

Reconfiguration latency remains the primary constraint for practical DPR deployment. Modern platforms achieve sub-millisecond reconfiguration for small modules, with full-region reconfiguration typically requiring 10–100 ms depending on region size [11]. Gohringer and Becker demonstrated reconfiguration latencies under 10 ms for video processing pipelines, enabling seamless switching during frame boundaries [21]. Irmak et al. report 2–5× throughput improvements through adaptive CNN accelerator configurations compared to static implementations [22,24]. Yet none of these studies provide worst-case execution time (WCET) analysis required for ASIL certification in automotive applications.

The infrastructure overhead is substantial. DPR requires dedicated controllers, partition boundary logic, and configuration management hardware consuming approximately 10–15% of available resources [53]. Zamacola et al. note that bitstream compression reduces transfer time but introduces decompression latency, creating a nontrivial optimization problem [23]. The Internal Configuration Access Port (ICAP) provides 100–400 MB/s throughput depending on configuration width, but this theoretical maximum assumes optimal scheduling and no contention [54].

5.1.2. Multi-Granularity Reconfiguration

The surveyed studies employ reconfiguration at three granularity levels, each presenting distinct trade-offs. Zamacola et al.’s multi-grained framework combines coarse-grained module swapping with medium-grained overlay updates and fine-grained LUT-level parameter tuning through their IMPRESS tool targeting Xilinx 7 Series devices [23]. Their results demonstrate that fine-grained approaches reduce reconfiguration time by 90% compared to full-module swaps but at the cost of increased design complexity and tool-specific constraints.

At the coarse end, module-based DPR treats reconfigurable regions as interchangeable accelerators. Podobas et al. survey comprehensive performance of coarse-grained reconfigurable architectures, covering DPR-enabled adaptive configurations for diverse computational workloads [24]. The reconfiguration overhead in such implementations is partially hidden through prefetching—loading the next module’s bitstream into on-chip BRAM while the current module executes [22]. However, prefetching consumes BRAM that could otherwise store CNN weights, creating direct resource competition between reconfiguration capability and inference performance.

5.1.3. DPR–NoC Convergence

The convergence of DPR with networks-on-chip presents both opportunities and challenges. Koch’s Recobus-X architecture exploits FPGA column-based reconfiguration for dynamic topology adaptation [55], while Stensgaard’s ReNoC demonstrates runtime topology switching on FPGA prototypes [56]. These approaches enable hardware that adapts not only its computational kernels but also its communication infrastructure—a capability with clear relevance to heterogeneous automotive workloads where perception, planning, and control tasks have diverse bandwidth requirements.

However, reconfigurable interconnects compound verification complexity: each configuration combination requires independent timing closure and functional verification. For a system with n reconfigurable regions each supporting k module variants, the number of configurations requiring verification grows as $k^n$, quickly exceeding practical verification budgets. No surveyed study addresses this combinatorial verification challenge.

5.1.4. Safety Certification Gap

A critical observation emerges from the surveyed literature: despite two decades of DPR research since early implementations on Virtex-II devices [57,58], no study addresses safety certification requirements. The overwhelming majority of surveyed papers focusing on performance optimization ignore the WCET bounds, fault injection analysis, and systematic verification demanded by ISO 26262. DPR introduces configuration-dependent behavior, timing variability at region boundaries, and fault propagation paths from configuration memory to safety-critical static regions—all of which require explicit analysis under functional safety standards [15,32]. A detailed gap analysis is provided in Section 7.

5.2. Interconnect and Communication Architectures

Networks-on-chip (NoCs) have emerged as the scalable alternative to bus-based interconnects for complex SoC designs, yet their application to safety-critical FPGA systems remains problematic. The surveyed literature reveals a disconnect between NoC performance achievements and safety requirements.

5.2.1. Resource Costs and Topology Trade-Offs

Benini and De Micheli established the theoretical foundations for NoC-based interconnect as a solution to bus scalability limitations [59], with Dally and Towles providing the comprehensive design methodology [60]. For FPGA implementation, the resource cost is significant: a five-port router requires 500–2000 LUTs depending on features, with virtual channels demanding additional BRAM for buffers. Network interfaces add 200–500 LUTs plus 1–4 BRAMs per connection [13]. For resource-constrained edge devices, these overheads may exceed available capacity; a single 4×4 mesh NoC can consume 15–25% of a mid-range FPGA’s logic resources before any application logic is placed.

The choice of topology involves direct performance–resource trade-offs. Patel et al. report up to 3× throughput improvement with NoC-interconnected multiprocessors over single-processor systems using 2D mesh topologies [19]. However, their implementation on Virtex-II Pro devices consumes 65% of LUTs and 40% of BRAM, leaving limited headroom for accelerator expansion. Alternative topologies, such as torus (wrap-around links reducing diameter) and tree (hierarchical for divide-and-conquer patterns), offer better average-case performance for specific traffic patterns but at higher implementation complexity [60].

5.2.2. Routing and Flow Control

Deterministic routing (e.g., XY dimension order) provides deadlock freedom and predictable behavior suitable for safety-critical applications but achieves poor load balancing under non-uniform traffic. Adaptive routing algorithms (west-first and minimal adaptive) improve throughput but introduce timing variability that complicates WCET analysis. Zero-load latency of 2–5 cycles per hop enables predictable performance for bounded traffic, but this predictability vanishes under congestion: contention latency depends on traffic load and routing decisions that are difficult to bound analytically.

Flow control mechanisms further differentiate approaches. Credit-based flow control provides efficient link utilization with bounded buffering, while simpler on–off signaling requires larger buffers for equivalent efficiency. For safety-critical deployments, the choice between these mechanisms directly impacts worst-case timing behavior, yet none of the surveyed implementations analyze this relationship.

5.2.3. Heterogeneous Platform Interconnect

The AMD Xilinx Zynq MPSoC exemplifies the heterogeneous interconnect challenge. The platform implements multiple interconnect types: CCI-400 for cache coherency among ARM cores, AXI interconnect for accelerator connectivity, and, in Versal devices, a dedicated NoC for high-bandwidth data movement [26]. This heterogeneity provides flexibility but complicates WCET analysis as traffic from different sources shares physical links without guaranteed isolation.

Reconfigurable NoCs attempt to address flexibility–efficiency trade-offs. Recobus-X exploits column-based partial reconfiguration for dynamic topology changes [55], while ReNoC implements switch-based runtime adaptation [56]. Cozzi et al. demonstrated dynamic bandwidth allocation through time-division multiplexing [13], enabling runtime adaptation of interconnect capacity to match workload demands.

5.2.4. Safety Implications of Shared Interconnect

The safety implications are profound. ISO 26262 requires demonstrable freedom from interference between safety-critical and non-critical functions. NoC-based systems inherently share physical resources—links, buffers, and arbitration logic—making interference-free operation difficult to guarantee. None of the surveyed FPGA NoC implementations address partitioning for mixed-criticality systems or provide the formal timing analysis required for ASIL certification.

5.3. Design Automation and the Productivity Frontier

High-level synthesis (HLS) has transformed FPGA development productivity, yet its implications for safety-critical systems remain underexamined in the surveyed literature. The tension between abstraction benefits and verification challenges defines the current productivity frontier.

5.3.1. Performance-Quality of Results

HLS achieves 80–100% of manual RTL performance while reducing development time by 3–10× [27,28]. Resource overhead ranges from 0 to 30% compared to hand-optimized designs, a trade-off many projects accept given the productivity gains. Post-2018, approximately 85% of surveyed CNN acceleration papers employ HLS-based design flows, reflecting its dominance in the accelerator design space. The implications for design space exploration are substantial: HLS enables rapid evaluation of architectural alternatives that would be prohibitively expensive with manual RTL.

Zhang et al.’s FPGA-based YOLO accelerator demonstrates competitive throughput and energy efficiency using reconfigurable hardware design [38], demonstrating that state-of-the-art performance is achievable through hardware specialization. Minhas et al. employ OpenCL-based HLS for task-specific partitioning, achieving 2.8× throughput improvement in multi-tasking scenarios [51]. These results suggest that the performance gap between HLS and manual RTL has largely closed for CNN accelerator designs.

5.3.2. The Verification Challenge

However, HLS introduces abstraction layers that obscure timing details that are critical for safety certification. The automated scheduling, binding, and RTL generation processes produce implementations whose timing behavior is determined by tool algorithms rather than explicit designer specification. Zhang et al.’s impressive throughput numbers come without WCET analysis or discussion of certification requirements [38]—a pattern that repeats across the surveyed HLS-based implementations.

The verification challenge is particularly acute. HLS tools generate complex finite state machines and control logic that may not correspond intuitively to the source code structure. Molina et al. note that debugging HLS-generated designs requires understanding both the original algorithm and the tool’s transformation decisions [61]. Santambrogio and others emphasize the need for automated equivalence checking between source specifications and generated RTL [62], but such tools remain immature for safety-critical applications. The “HLS-friendly coding style” required for good results [61] represents specialized expertise that partly negates the accessibility benefits that HLS promises.

5.3.3. Domain-Specific Frameworks

Domain-specific frameworks have emerged to address particular application classes. hls4ml provides automated conversion of trained machine learning models to FPGA implementations with support for quantization and pruning [63]. Vitis AI v2.5 offers complete flows from trained models to deployment on AMD Xilinx platforms, while Intel (Altera) OpenVINO provides cross-platform inference optimization. FINN, developed by AMD Xilinx Research, targets quantized neural network inference with bit-accurate simulation [46].

These frameworks reduce expertise barriers but introduce additional abstraction layers between designer and implementation. A practitioner using Vitis AI to deploy a YOLO model may achieve good throughput without understanding the underlying resource allocation, memory partitioning, or pipeline scheduling decisions—precisely the details required for safety certification.

5.3.4. The Safety–Productivity Paradox

A fundamental tension emerges: HLS abstracts away the cycle-accurate control necessary for WCET analysis, while safety certification requires precisely such analysis. None of the surveyed HLS frameworks provide formal timing guarantees or integration with safety certification workflows. Gannous et al. identify this verification gap as a primary barrier to FPGA adoption in automotive and aerospace applications [32]. Until HLS tools can produce certified timing artifacts alongside RTL, their applicability to ASIL-rated systems remains limited despite compelling productivity advantages.

5.4. CNN Acceleration for Edge AI

FPGA-based CNN acceleration has achieved substantial performance improvements over the past decade, yet the surveyed literature reveals persistent gaps between research achievements and safety-critical deployment requirements. The performance trajectory tells only part of the story. Figure 5 compares performance across FPGA, GPU, and CPU platforms for inference workloads.

5.4.1. Performance Evolution

Table 5 summarizes the evolution of FPGA CNN accelerator performance. Zhang et al. achieved 61.6 GOPS on Virtex-7 using systolic array architectures [20], establishing the baseline for subsequent optimization. Qiu et al. improved throughput to 137.2 GOPS with 8.3 GOPS/W energy efficiency on Zynq platforms through streaming architectures with layer-by-layer pipelining [43]. Wei et al. pushed performance to 294 GOPS on UltraScale+ devices through aggressive parallelization [44]. More recently, Zhang et al.’s FPGA-based YOLO accelerator demonstrates competitive throughput and energy efficiency for edge-constrained platforms [38]. Yan et al.’s resource-multiplexed approach achieves 21.1 GOPS with 200 MHz clock and 340.7 μs prediction latency [39], prioritizing deterministic latency over raw throughput.

5.4.2. Quantization: The Dominant Optimization

Quantization has emerged as the dominant optimization technique across the surveyed literature. INT8 precision is now standard for edge deployment, with binary and ternary networks targeting maximum efficiency at moderate accuracy cost [64,65]. XNOR-Net demonstrates that binary convolutions using XNOR operations can achieve significant resource savings. Replacing multiply–accumulate operations with bitwise operations reduces DSP requirements to zero for binary layers [66]. Mixed precision approaches allocate higher precision to accuracy-sensitive layers while aggressively quantizing others, with layer-adaptive schemes showing particular promise for preserving accuracy in the final classification layers [38].

Table 5. FPGA-based CNN accelerator performance summary.

Study	Network	Throughput	Efficiency	Platform
Zhang (2015) [20]	Various	61.6 GOPS	–	Virtex-7
Qiu [43]	VGG-16	137.2 GOPS	8.3 GOPS/W	Zynq
Wei [44]	ResNet	294 GOPS	–	UltraScale+
Yan [39]	Custom	21.1 GOPS	–	FPGA
Zhang (2020) [38]	YOLO	Competitive	Competitive	FPGA

Table 5. FPGA-based CNN accelerator performance summary.

Study	Network	Throughput	Efficiency	Platform
Zhang (2015) [20]	Various	61.6 GOPS	–	Virtex-7
Qiu [43]	VGG-16	137.2 GOPS	8.3 GOPS/W	Zynq
Wei [44]	ResNet	294 GOPS	–	UltraScale+
Yan [39]	Custom	21.1 GOPS	–	FPGA
Zhang (2020) [38]	YOLO	Competitive	Competitive	FPGA

However, quantization introduces numerical uncertainty that compounds with model uncertainty, creating challenges for safety-critical applications requiring calibrated confidence estimates. A model quantized to INT8 may maintain 99% top-1 accuracy on benchmark datasets, but the confidence distribution of individual predictions shifts—an effect that is rarely analyzed in the surveyed literature. This is particularly relevant for driver drowsiness detection, where the decision threshold between “alert” and “drowsy” states must be calibrated with uncertainty quantification, not merely accuracy.

5.4.3. Platform Positioning

Comparative analysis against alternative platforms reveals FPGA positioning. FPGA implementations achieve 10–50× speedup over embedded CPUs while consuming comparable or lower power [67]. Against GPUs, FPGAs achieve 2–10× better energy efficiency for inference workloads, particularly at batch size 1 typical of edge deployments. FPGAs achieve 50–80% of ASIC efficiency with significantly lower development cost [68]. This efficiency positioning makes FPGAs attractive for edge deployment where power constraints dominate.

The energy efficiency claims require careful interpretation. While FPGA implementations demonstrate significantly better energy efficiency than GPUs for inference [12], these comparisons often favor FPGAs by using optimized FPGA implementations against baseline GPU configurations. Fair comparison requires matching optimization effort across platforms. Furthermore, efficiency metrics rarely account for the power consumption of external memory, which often dominates total system power for CNN workloads with large weight tensors. System-level cost—including development effort, tool licensing, and time-to-market—is also frequently omitted. These caveats apply to the performance comparison in Figure 5 and Table 5: the FPGA numbers represent hand-optimized implementations, while GPU baselines may not reflect equivalent optimization effort. Readers should interpret cross-platform efficiency claims as indicative rather than definitive, and future work should adopt matched-effort benchmarks (e.g., same model, same quantization, and same optimization time budget) for fair comparison.

5.4.4. Edge Deployment Constraints

Edge deployment imposes additional constraints beyond raw performance. Real-time applications require sub-10 ms end-to-end latency; autonomous vehicles demand sub-100 ms response times with ASIL-D safety requirements. Power envelopes range from <1 W for battery-powered devices to 1–10 W for line-powered edge nodes. Memory constraints limit model complexity, driving adoption of mobile-optimized architectures, such as MobileNet and EfficientNet-Lite.

5.4.5. The Safety Certification Gap in CNN Acceleration

A critical observation emerges: no study in our sample of CNN accelerator implementations addresses safety certification requirements. The performance optimization focus ignores WCET bounds, fault tolerance, and systematic verification demanded by ISO 26262. Zhang et al.’s systolic arrays assume batch inference [20], ignoring the single-sample latency requirements of real-time edge applications. Streaming architectures provide predictable latency but sacrifice flexibility for network architecture changes. This certification gap represents a significant challenge for FPGA CNN accelerator adoption in safety-critical automotive perception systems.

Current CNN accelerator implementations produce point predictions without confidence estimates, providing no mechanism to signal when inputs fall outside the training distribution or when quantization has degraded prediction reliability. We address this gap and propose a solution in Section 7.

6. Performance Synthesis

This section synthesizes the quantitative findings from the 36 surveyed studies, presenting performance metrics, design approach comparisons, and identifying gaps where performance reporting falls short of safety certification requirements.

6.1. Characteristics of Included Studies

The 36 included studies span from 1998 to 2025, organized into two temporal layers. The historical context layer (1998–2009) comprises seven studies providing foundational contributions to DPR and NoC evolution [4,13,17,18,19,56,57]; these are not evaluated against safety standards released after their publication. The core analysis layer (2010–2025) includes 29 studies aligned with the modern AI accelerator era [11,16,20,21,22,23,24,25,26,30,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,55,69,70]. Target devices are predominantly AMD Xilinx platforms (72%), with Zynq UltraScale+ MPSoC being the most common, followed by Intel (Altera) FPGAs (11%) and general/unspecified platforms (17%). A frequency analysis of the 36 included studies reveals the following distribution of research focus areas: DPR-enabled designs (44%, 16 studies), HLS-based flows (42%, 15 studies), CNN/AI acceleration targets (50%, 18 studies), NoC-based interconnect (25%, nine studies), and explicit safety consideration (8%, three studies). The overlap between these categories is substantial: 69% of CNN acceleration studies also employ DPR, and 75% use HLS, reflecting the convergence patterns quantified in Section 9. No study in our sample combines DPR, NoC, CNN acceleration, and safety certification in a single design.

Table 6 summarizes the key study characteristics.

6.2. Performance Metrics

Table 7 summarizes the key performance metrics across the surveyed studies. The results demonstrate substantial variation in reported metrics, reflecting heterogeneous measurement methodologies and benchmark definitions.

The heterogeneity of the reported metrics hampers direct cross-study comparison. While throughput (GOPS) and energy efficiency (GOPS/W) are the most commonly reported, studies differ in whether they report peak or sustained throughput, batch or single-sample latency, and device-specific or normalized resource utilization.

Table 6. Characteristics of included studies.

Study	Year	Key Focus	Target Device	Application
Patel et al. [19]	2006	Scalable multiprocessor	Off-the-shelf FPGAs	Molecular dynamics
Zamacola et al. [23]	2020	Multi-grained reconfiguration	Xilinx 7 Series	Image processing, NN
Gohringer & Becker [21]	2010	Runtime-adaptive MPSoC	General FPGAs	HPC
Vipin & Fahmy [11]	2018	DPR architecture review	Zynq UltraScale+, Stratix	Signal processing, AI
Patel et al. [25]	2011	CGRA modeling & simulation	Commercial FPGAs	CGRA design exploration
Mhadhbi et al. [50]	2014	MicroBlaze FPGA configurations	General FPGAs	HW/SW partitioning
Dorta et al. [17]	2009	MPSoC overview	General FPGAs	Embedded systems
Monmasson & Cirstea [18]	2007	FPGA design methodology	General FPGAs	Industrial control
Li & Hauck [70]	2010	Configuration prefetching	General FPGAs	Partial reconfiguration
Minhas et al. [51]	2022	Task-specific partitioning	General FPGAs	Cloud/edge multi-tasking
Boutros et al. [52]	2022	RAD co-design	Beyond-FPGA RADs	Datacenter workloads
Cozzi et al. [13]	2009	Reconfigurable NoC flow	General FPGAs	Embedded systems
Podobas et al. [24]	2020	CGRA performance survey	General FPGAs	CGRA evaluation
Zhang et al. (2020) [38]	2020	FPGA CNN accelerator	General FPGA	Object detection
Yan et al. [39]	2022	Resource-multiplexing CNN	FPGAs	Image classification
Irmak et al. [22]	2021	DPR for CNN flexibility	Xilinx FPGAs	Image classification
Johnson et al. [16]	2023	Distributed cluster	Zynq-7020, UltraScale+ MPSoC	Edge deep learning
Ma et al. [45]	2017	CNN dataflow optimization	Xilinx Zynq	CNN acceleration
Guo et al. [46]	2018	Complete CNN-to-FPGA flow	Xilinx Zynq	Image classification
Nguyen et al. [47]	2021	Mixed-precision FPGA design	Xilinx Zynq MPSoC	Object detection
Liu et al. [48]	2017	Throughput-optimized accelerator	Xilinx VC707	CNN inference
Gong et al. [49]	2021	Dynamic/static co-reconfiguration	Xilinx Zynq MPSoC	CNN acceleration
Ijaz et al. [69]	2023	Dynamically scalable NoC	General FPGAs	Reconfigurable apps
Zhang et al. [30]	2025	WCET for CNN on FPGA SoC	Xilinx Zynq MPSoC	WCET estimation
Sestito et al. [40]	2025	TrIM systolic array for CNN	FPGA	CNN acceleration
Peccia et al. [41]	2024	Gemmini accelerator edge AI	Xilinx ZCU102	Object detection
Rahoof et al. [42]	2023	Capsule network acceleration	Xilinx PYNQ-Z1	Capsule networks
Restuccia & Biondi [37]	2021	Time-predictable DNN on SoC	Xilinx Zynq UltraScale+	DNN timing analysis

Table 6. Characteristics of included studies.

Study	Year	Key Focus	Target Device	Application
Patel et al. [19]	2006	Scalable multiprocessor	Off-the-shelf FPGAs	Molecular dynamics
Zamacola et al. [23]	2020	Multi-grained reconfiguration	Xilinx 7 Series	Image processing, NN
Gohringer & Becker [21]	2010	Runtime-adaptive MPSoC	General FPGAs	HPC
Vipin & Fahmy [11]	2018	DPR architecture review	Zynq UltraScale+, Stratix	Signal processing, AI
Patel et al. [25]	2011	CGRA modeling & simulation	Commercial FPGAs	CGRA design exploration
Mhadhbi et al. [50]	2014	MicroBlaze FPGA configurations	General FPGAs	HW/SW partitioning
Dorta et al. [17]	2009	MPSoC overview	General FPGAs	Embedded systems
Monmasson & Cirstea [18]	2007	FPGA design methodology	General FPGAs	Industrial control
Li & Hauck [70]	2010	Configuration prefetching	General FPGAs	Partial reconfiguration
Minhas et al. [51]	2022	Task-specific partitioning	General FPGAs	Cloud/edge multi-tasking
Boutros et al. [52]	2022	RAD co-design	Beyond-FPGA RADs	Datacenter workloads
Cozzi et al. [13]	2009	Reconfigurable NoC flow	General FPGAs	Embedded systems
Podobas et al. [24]	2020	CGRA performance survey	General FPGAs	CGRA evaluation
Zhang et al. (2020) [38]	2020	FPGA CNN accelerator	General FPGA	Object detection
Yan et al. [39]	2022	Resource-multiplexing CNN	FPGAs	Image classification
Irmak et al. [22]	2021	DPR for CNN flexibility	Xilinx FPGAs	Image classification
Johnson et al. [16]	2023	Distributed cluster	Zynq-7020, UltraScale+ MPSoC	Edge deep learning
Ma et al. [45]	2017	CNN dataflow optimization	Xilinx Zynq	CNN acceleration
Guo et al. [46]	2018	Complete CNN-to-FPGA flow	Xilinx Zynq	Image classification
Nguyen et al. [47]	2021	Mixed-precision FPGA design	Xilinx Zynq MPSoC	Object detection
Liu et al. [48]	2017	Throughput-optimized accelerator	Xilinx VC707	CNN inference
Gong et al. [49]	2021	Dynamic/static co-reconfiguration	Xilinx Zynq MPSoC	CNN acceleration
Ijaz et al. [69]	2023	Dynamically scalable NoC	General FPGAs	Reconfigurable apps
Zhang et al. [30]	2025	WCET for CNN on FPGA SoC	Xilinx Zynq MPSoC	WCET estimation
Sestito et al. [40]	2025	TrIM systolic array for CNN	FPGA	CNN acceleration
Peccia et al. [41]	2024	Gemmini accelerator edge AI	Xilinx ZCU102	Object detection
Rahoof et al. [42]	2023	Capsule network acceleration	Xilinx PYNQ-Z1	Capsule networks
Restuccia & Biondi [37]	2021	Time-predictable DNN on SoC	Xilinx Zynq UltraScale+	DNN timing analysis

Table 7. Performance metric summary.

Metric	Value	Reference
Throughput (YOLO)	Competitive GOPS	[38]
Energy Efficiency	Competitive GOPS/W	[38]
Speedup vs. Single-Processor	3×	[19]
Multi-Tasking Throughput	2.8× improvement	[51]
Inference Latency	Not reported	[38]
DPR Speedup vs. Static	2–5×	[11]
Prediction Latency	340.7 μs	[39]
Intra-Link Bandwidth	10 Gbps	[52]

Table 7. Performance metric summary.

Metric	Value	Reference
Throughput (YOLO)	Competitive GOPS	[38]
Energy Efficiency	Competitive GOPS/W	[38]
Speedup vs. Single-Processor	3×	[19]
Multi-Tasking Throughput	2.8× improvement	[51]
Inference Latency	Not reported	[38]
DPR Speedup vs. Static	2–5×	[11]
Prediction Latency	340.7 μs	[39]
Intra-Link Bandwidth	10 Gbps	[52]

6.3. Design Approach Comparison

Table 8 compares the design approaches across the surveyed studies, revealing clear trade-offs between productivity and efficiency.

The reconfiguration granularity analysis (Table 9) reveals a spectrum from fine-grained parameter tuning to coarse-grained application swapping, with each level offering different latency–flexibility trade-offs.

Table 8. Design approach comparison.

Approach	Studies	Strengths	Limitations
HLS-based	[51]	Rapid development	Lower peak efficiency
RTL-based	[19,50]	Maximum efficiency	Longer dev time
Hybrid (HLS+RTL)	[16]	Balanced trade-off	Integration complexity
CGRAs	[25]	Flexible computation	Area overhead

Table 8. Design approach comparison.

Approach	Studies	Strengths	Limitations
HLS-based	[51]	Rapid development	Lower peak efficiency
RTL-based	[19,50]	Maximum efficiency	Longer dev time
Hybrid (HLS+RTL)	[16]	Balanced trade-off	Integration complexity
CGRAs	[25]	Flexible computation	Area overhead

Table 9. Reconfiguration granularity analysis.

Granularity	Reconfig. Time	Use Case	Flexibility
Fine-grained (LUT-level)	1–5 ms	Parameter tuning	Highest
Medium-grained (overlay)	5–20 ms	Algorithm switching	Medium
Coarse-grained (module)	20–100 ms	Application swapping	Lowest

Table 9. Reconfiguration granularity analysis.

Granularity	Reconfig. Time	Use Case	Flexibility
Fine-grained (LUT-level)	1–5 ms	Parameter tuning	Highest
Medium-grained (overlay)	5–20 ms	Algorithm switching	Medium
Coarse-grained (module)	20–100 ms	Application swapping	Lowest

6.4. Evidence Quality Assessment

Table 10. Evidence confidence levels.

Theme	Confidence	Supporting Studies
DPR effectiveness	Strong	8+
Parallel speedup	Strong	10+
CNN acceleration	Moderate	6+
Energy efficiency	Moderate	5+
Scalability	Tentative	4+

summarizes the evidence confidence across the major themes. DPR effectiveness and parallel speedup enjoy strong support, while scalability claims remain tentative due to limited replication.

6.5. Safety-Relevant Performance Gaps

Our analysis reveals critical gaps between the reported performance metrics and the evidence required for safety certification:

• No WCET Bounds in Accelerator Designs: All the surveyed CNN accelerator studies report average-case performance metrics. None provide worst-case execution time analysis, which is mandatory for ASIL-B and above under ISO 26262. While recent work has demonstrated WCET analysis feasibility for FPGA SoC platforms [29,30,31,37], with Restuccia & Biondi (2021) providing response-time analysis validated against hardware measurements on Zynq UltraScale+, these methods have not yet been adopted by the broader CNN accelerator design community. The reported inference latencies in surveyed CNN accelerators are average-case measurements without variance analysis or upper bounds [38].
• No Timing Determinism Analysis: Streaming architectures (e.g., Qiu et al. [43]) claim predictable latency, but none provide formal proof of timing determinism under all operating conditions, including memory contention and thermal throttling.
• Missing Confidence Calibration: CNN accelerator studies report classification accuracy (94–99%) but never calibration metrics—whether prediction confidence matches empirical correctness. This is essential for safety-critical decisions where low-confidence predictions must trigger failsafe behavior.
• No Fault Injection Results: None of the performance evaluations include fault injection testing to measure system behavior under hardware faults (SEUs in configuration memory, DSP errors, and routing failures).
• Incomparable Metrics: The heterogeneity of reported metrics prevents quantitative synthesis of safety-relevant parameters, such as timing margins, resource headroom, and error detection coverage.

These gaps collectively prevent the surveyed implementations from being used in any safety-critical application requiring ASIL certification regardless of their impressive average-case performance numbers.

7. Safety-Critical FPGA SoCs and Uncertainty Quantification

As FPGA-based reconfigurable systems transition from research prototypes to safety-critical applications in autonomous vehicles, industrial control, and medical devices, a critical research gap emerges: the surveyed literature largely ignores the stringent requirements of functional safety standards. We assess this gap against a three-layer standard framework: ISO 26262 for functional safety, ISO 21448 for safety of the intended functionality (SOTIF), and ISO/PAS 8800 for AI safety properties in road vehicles. This section analyzes the safety-critical constraints, identifies the gaps in the existing research, and proposes a novel research direction connecting reconfigurable computing with uncertainty quantification for trustworthy AI.

7.1. Functional Safety Requirements for FPGA SoCs

Field-programmable gate arrays deployed in safety-critical applications must comply with international standards, such as ISO 26262 for automotive systems, IEC 61508 for industrial applications, and DO-254 for aerospace. These standards mandate rigorous verification, deterministic behavior, and fault tolerance mechanisms.

7.1.1. ISO 26262 Requirements

The ISO 26262 standard defines Automotive Safety Integrity Levels (ASILs) from A to D, with ASIL-D representing the highest integrity requirements:

• Deterministic Latency: Bounded worst-case execution time (WCET) needs to be guaranteed. The surveyed studies report average-case latencies, and none provide formal WCET bounds meeting the analysis requirements of ISO 26262 Part 6, although recent analytical models demonstrate WCET estimation feasibility for multi-DPU FPGA SoC platforms (see Section 7).
• Hardware Fault Tolerance: Single-point fault metrics require detection mechanisms for configuration errors, transient faults, and hardware failures.
• Configuration Integrity: Dynamic partial reconfiguration must not introduce timing violations or data corruption in static regions performing safety functions.

Table 11 summarizes the ISO 26262 ASIL requirements that are most relevant to FPGA-based CNN acceleration. The gap between the current FPGA research and the ASIL-D requirement spans every dimension: no surveyed study provides WCET bounds (required from ASIL-B), no implementation addresses DPR verification (mandatory for ASIL-C/D), and configuration integrity mechanisms remain at the CRC-level rather than the triple redundancy demanded by ASIL-D.

7.1.2. DPR Challenges for Safety-Critical Systems

The reviewed DPR literature presents several challenges for safety-critical deployment:

• Reconfiguration Timing: While studies report sub-10 ms reconfiguration latencies, safety-critical systems require deterministic guarantees that reconfiguration completes within bounded time regardless of system state.
• State Preservation: Critical system state must be preserved during reconfiguration. No surveyed study addresses formal methods for verifying state consistency.
• Fault Detection: Configuration memory CRC checks detect bit errors but cannot detect functional faults in the reconfigured logic.
• Temporal Separation: Safety-critical and non-safety-critical functions must be temporally isolated to prevent interference.

Table 11. ISO 26262-5 single-point fault metric (SPFM) requirements and recommended architectural measures for FPGA-based CNN acceleration, adapted from Part 5, Table 6 and Part 4.

Requirement	ASIL-A	ASIL-B	ASIL-C	ASIL-D
Random HW fault detection	90%	97%	99%	99.9%
WCET analysis	Recommended	Required	Required	Mandatory
DPR verification	Optional	Recommended	Required	Mandatory
Configuration integrity	CRC	CRC + ECC	CRC + ECC + monitor	Triple redundancy
Spurious actuation control	Monitor	Dual check	Dual + watchdog	Triple + watchdog

Table 11. ISO 26262-5 single-point fault metric (SPFM) requirements and recommended architectural measures for FPGA-based CNN acceleration, adapted from Part 5, Table 6 and Part 4.

Requirement	ASIL-A	ASIL-B	ASIL-C	ASIL-D
Random HW fault detection	90%	97%	99%	99.9%
WCET analysis	Recommended	Required	Required	Mandatory
DPR verification	Optional	Recommended	Required	Mandatory
Configuration integrity	CRC	CRC + ECC	CRC + ECC + monitor	Triple redundancy
Spurious actuation control	Monitor	Dual check	Dual + watchdog	Triple + watchdog

7.2. Safety of the Intended Functionality (ISO 21448)

While ISO 26262 addresses functional safety (ensuring the system works as designed without faults), ISO 21448:2022 (safety of the intended functionality, SOTIF) addresses a fundamentally different failure mode: situations where the system functions as designed but still produces unsafe outcomes due to specification insufficiencies or performance limitations [2]. This distinction is critical for AI-based systems, where the neural network may perform correctly according to its specification but fail on out-of-distribution inputs or edge cases.

SOTIF introduces the concept of triggering events—specific conditions that cause the intended functionality to behave in a potentially hazardous way. For driver drowsiness detection, triggering events include unusual lighting conditions, partial occlusion, atypical driver positions, and ambiguous eye-state patterns. Conformal prediction (Section 7) directly addresses this requirement: the prediction set size provides a quantitative measure of specification insufficiency. Large prediction sets indicate inputs where the model encounters triggering events, enabling the system to trigger failsafe behavior or human intervention.

No surveyed study addresses the SOTIF requirements despite their direct relevance to AI-based perception systems in vehicles.

7.3. AI Safety Properties (ISO/PAS 8800)

ISO/PAS 8800:2024 provides a framework specifically designed for AI-based systems in automotive applications [3]. It addresses:

• Neural Network Verification: Requirements for ensuring that learned models behave correctly across their operational design domain.
• Confidence Monitoring: Runtime monitoring of prediction confidence during inference—directly connecting to our conformal prediction proposal in Section 7.
• Safety Argumentation for ML Components: Guidance on constructing safety cases for ML components that supplement the traditional ISO 26262 V-model approach.
• Data Quality Requirements: Ensuring training and validation data representatively cover the operational design domain.

No surveyed study addresses the ISO/PAS 8800 requirements. This gap is particularly concerning because the standard directly mandates the type of runtime confidence monitoring that conformal prediction enables.

7.4. WCET Analysis for FPGA SoCs

Early analyses of the literature suggested that “no work provides worst-case execution time bounds” for FPGA AI acceleration. Subsequent work has made meaningful progress on this front:

• Lang, Kapre & Pellizzoni (2021) [29]: Provides worst-case latency analysis for the Versal NoC network packet switch, establishing tight bounds for on-chip communication latency. Directly relevant to multi-DPU FPGA SoC architectures where NoC contention causes timing variability. Limitation: covers NoC traversal, not end-to-end CNN inference WCET.
• Gu et al. (2014) [31]: Addresses WCET-aware partial control-flow checking for resource-constrained real-time embedded systems. Relevant to DPR timing verification. Limitation: focuses on control-flow checking rather than data-path timing of CNN accelerators.
• Zhang et al. (2025) [30]: Provides WCET estimation specifically for CNN inference on FPGA SoCs with multi-DPU engines using analytical models of DPU scheduling, memory hierarchy access patterns, and inter-DPU communication. This work demonstrates that end-to-end WCET bounds for CNN inference on AMD Xilinx DPU-based platforms are feasible. We have included this study in our expanded corpus.
• Restuccia & Biondi (2021) [37]: Presents time-predictable DNN acceleration on Zynq UltraScale+ FPGA SoC with the Xilinx DPU, proposing the DICTAT custom FPGA module to improve timing predictability and providing response-time analysis validated against hardware measurements. Limitation: focuses on the Xilinx DPU accelerator specifically rather than general FPGA CNN acceleration.

Revised finding: WCET analysis methods exist for FPGA platforms, with recent work (Zhang et al., 2025 [30]; Restuccia & Biondi, 2021 [37]) demonstrating feasibility on real hardware, but these methods have not yet been adopted by the broader CNN accelerator design community. The gap is one of adoption rather than availability of methods. The priority remains critical because the gap between the available methods and practical deployment is still substantial.

Contextual note on evaluation criteria. We assess the surveyed literature against ISO 26262 and ASIL-D requirements as an aspirational benchmark, not to imply that academic prototypes should meet certification standards. The majority of the surveyed studies are exploratory research contributions—proofs of concept, architecture explorations, and efficiency optimizations—rather than certification-oriented system developments. Evaluating them against ASIL-D criteria may therefore appear misaligned. However, we intentionally adopt this lens because our central contribution is identifying the gap between the current FPGA research trajectory and the requirements for eventual safety-certified deployment. This gap analysis is forward-looking: it identifies what must be addressed as FPGA-based AI inference transitions from laboratory prototypes to production safety-critical systems. We do not claim that individual studies are deficient for lacking certification artifacts; rather, the collective absence of safety considerations across the literature reveals a systemic gap that warrants community attention.

Table 12. FPGA-specific failure modes and detection mechanisms.

Failure Mode	Detection Mechanism	ASIL Coverage
Configuration SEU	CRC scrubbing	Partial
DPR timing violation	STA per configuration	Not addressed
Power supply glitch	Brownout detection	Vendor-specific
Clock domain crossing	CDC verification	Tool-dependent
Routing congestion	Post-route STA	Design-specific
Partial bitstream corruption	HMAC authentication	Research only

reveals that most FPGA failure modes lack detection mechanisms meeting ASIL requirements. Configuration SEU detection through CRC scrubbing provides only partial coverage: it detects bit error but but not functional faults in the configured logic. DPR timing violations are particularly concerning: each partial reconfiguration creates new timing paths that require independent static timing analysis, yet no automated tool support exists for this scenario.

Safety Awareness Classification

A study is classified as safety-aware if it explicitly addresses at least one of the following dimensions: (a) worst-case execution time (WCET) analysis or deterministic timing guarantees; (b) hardware fault tolerance mechanisms (SEU detection, triple redundancy, or CRC scrubbing beyond vendor defaults); or (c) compliance or alignment with a functional safety standard (ISO 26262, IEC 61508, or DO-254). Studies that mention safety as motivation but provide no analysis or mechanism are not classified as safety-aware. Table 13 applies these criteria to each of the 36 included studies.

Acknowledgment of partial safety efforts. We recognize that this binary classification is strict and may undercount studies that incorporate partial or implicit safety considerations without explicitly addressing WCET, fault tolerance, or standard compliance. For example, several surveyed FPGA designs exploit deterministic pipeline architectures that implicitly provide timing predictability—a prerequisite for WCET analysis—without formally computing or reporting WCET bounds. Similarly, some studies employ redundancy or error detection as design techniques without framing them as safety mechanisms. Our classification captures only explicit safety-awareness; the actual extent of safety-relevant engineering in the literature is likely broader than the 8% figure suggests. This distinction between explicit and implicit safety consideration is an important limitation that readers should weigh when interpreting the gap analysis.

Table 13. Safety awareness classification of the 36 included studies.

Study	WCET	Fault Tol.	Standard	Safety-Aware
Patel et al. [19]	–	–	–	No
Zamacola et al. [23]	–	–	–	No
Gohringer & Becker [21]	–	–	–	No
Vipin & Fahmy [11]	–	–	–	No
Patel et al. [25]	–	–	–	No
Mhadhbi et al. [50]	–	–	–	No
Dorta et al. [17]	–	–	–	No
Monmasson & Cirstea [18]	–	–	–	No
Li & Hauck [70]	–	–	–	No
Minhas et al. [51]	–	–	–	No
Boutros et al. [52]	–	–	–	No
Cozzi et al. [13]	–	–	–	No
Podobas et al. [24]	–	–	–	No
Zhang et al. (2020) [38]	–	–	–	No
Yan et al. [39]	–	–	–	No
Irmak et al. [22]	–	–	–	No
Johnson et al. [16]	–	–	–	No
Zhang et al. [20]	–	–	–	No
Qiu et al. [43]	–	–	–	No
Wei et al. [44]	–	–	–	No
Serrano et al. [26]	Partial	–	Mentioned	Yes
Wirthlin & Hutchings [4]	–	–	Mentioned	Partial
Hildebrandt & Timmermann [57]	–	–	–	No
Koch et al. [55]	–	–	–	No
Stensgaard [56]	–	–	–	No
Ma et al. [45]	–	–	–	No
Guo et al. [46]	–	–	–	No
Nguyen et al. [47]	–	–	–	No
Liu et al. [48]	–	–	–	No
Gong et al. [49]	–	–	–	No
Ijaz et al. [69]	–	–	–	No
Zhang et al. (2025) [30]	Partial	–	–	Yes
Sestito et al. [40]	–	–	–	No
Peccia et al. [41]	–	–	–	No
Rahoof et al. [42]	–	–	–	No
Restuccia & Biondi [37]	Partial	–	Mentioned	Yes

Table 13. Safety awareness classification of the 36 included studies.

Study	WCET	Fault Tol.	Standard	Safety-Aware
Patel et al. [19]	–	–	–	No
Zamacola et al. [23]	–	–	–	No
Gohringer & Becker [21]	–	–	–	No
Vipin & Fahmy [11]	–	–	–	No
Patel et al. [25]	–	–	–	No
Mhadhbi et al. [50]	–	–	–	No
Dorta et al. [17]	–	–	–	No
Monmasson & Cirstea [18]	–	–	–	No
Li & Hauck [70]	–	–	–	No
Minhas et al. [51]	–	–	–	No
Boutros et al. [52]	–	–	–	No
Cozzi et al. [13]	–	–	–	No
Podobas et al. [24]	–	–	–	No
Zhang et al. (2020) [38]	–	–	–	No
Yan et al. [39]	–	–	–	No
Irmak et al. [22]	–	–	–	No
Johnson et al. [16]	–	–	–	No
Zhang et al. [20]	–	–	–	No
Qiu et al. [43]	–	–	–	No
Wei et al. [44]	–	–	–	No
Serrano et al. [26]	Partial	–	Mentioned	Yes
Wirthlin & Hutchings [4]	–	–	Mentioned	Partial
Hildebrandt & Timmermann [57]	–	–	–	No
Koch et al. [55]	–	–	–	No
Stensgaard [56]	–	–	–	No
Ma et al. [45]	–	–	–	No
Guo et al. [46]	–	–	–	No
Nguyen et al. [47]	–	–	–	No
Liu et al. [48]	–	–	–	No
Gong et al. [49]	–	–	–	No
Ijaz et al. [69]	–	–	–	No
Zhang et al. (2025) [30]	Partial	–	–	Yes
Sestito et al. [40]	–	–	–	No
Peccia et al. [41]	–	–	–	No
Rahoof et al. [42]	–	–	–	No
Restuccia & Biondi [37]	Partial	–	Mentioned	Yes

Key Finding: Applying the classification criteria defined above, only three out of the 36 studies (8%) meet at least one safety-awareness dimension, and none meets more than one. This finding, consistent across all the thematic areas, indicates that explicit safety certification remains almost universally unaddressed in the FPGA reconfigurable SoC literature. We emphasize that this figure reflects explicit safety-awareness as defined by our criteria; the actual extent of implicit safety-relevant engineering (e.g., deterministic pipeline design or redundancy for performance rather than safety) is likely broader. The 95% confidence interval for this proportion, assuming a binomial distribution, is [77%, 98%], confirming the robustness of the finding despite the sample size.

7.5. Uncertainty Quantification in Hardware Accelerators

Deep neural network deployments in safety-critical applications require not only accurate predictions but also calibrated confidence estimates. Traditional CNN accelerators provide point predictions without uncertainty quantification, creating challenges for decision-making in ambiguous or out-of-distribution scenarios.

7.5.1. Motivation for Uncertainty-Aware Inference

In safety-critical applications such as driver drowsiness detection, a neural network must:

• Calibrate Confidence: Prediction confidence should match empirical accuracy. A 90% confidence prediction should be correct 90% of the time.
• Detect Novelty: Inputs significantly different from training data should result in high uncertainty, triggering human intervention or failsafe behavior.
• Provide Guarantees: Uncertainty estimates should be distribution-free with formal coverage guarantees, not merely learned approximations.

7.5.2. Conformal Prediction for FPGA Acceleration

Conformal prediction (CP) provides a distribution-free framework for uncertainty quantification with coverage guarantees [9,10]:

Formally, for a calibration set ${\mathcal{D}}_{\mathrm{cal}}={\left\{(X_i,Y_i)\right\}}_{i=1}^n$ and new input $X_{n+1}$, split conformal prediction constructs prediction sets $C\left(X_{n+1}\right)$ satisfying

$$\mathbb{P}(Y_{n+1}\in C\left(X_{n+1}\right))\ge 1-\alpha$$

(1)

where $\alpha \in (0,1)$ is the miscoverage rate [9,10]. For classification tasks relevant to drowsiness detection, the prediction set is constructed using nonconformity scores

$$s_i=1-\widehat{f}{\left(X_i\right)}_{Y_i}$$

(2)

where $\widehat{f}{\left(X_i\right)}_{Y_i}$ is the predicted probability of the true class. The quantile $\widehat{q}$ is computed as the $\lceil (1-\alpha )(n+1)\rceil /n$ quantile of $\{s_1,\dots ,s_n\}$, and prediction set:

$$C\left(X_{n+1}\right)=\{y:\widehat{f}{\left(X_{n+1}\right)}_y\ge 1-\widehat{q}\}$$

(3)

This formulation is hardware-implementable: the quantile $\widehat{q}$ is computed via a sorting network on the calibration scores (parallelizable on FPGA logic); the prediction set construction requires only comparison against the threshold $1-\widehat{q}$ [71,72]. To assess hardware feasibility, we consider the computational complexity of the key operations. The dominant operation is the sorting network for quantile computation, which, for a bitonic sorter, has complexity $O\left(n{log}^{2}n\right)$ in comparison units; this scales favorably for typical calibration set sizes ($n\le 10,000$) but grows nontrivially beyond that. Critically, binary classification—as required for drowsiness detection—demands only two comparisons per inference (one per class against the threshold $1-\widehat{q}$), making the per-inference overhead negligible. The primary resource concern is the storage of calibration scores ($n\times 32$ bits) and the sorting network depth, both of which scale linearly with calibration set size. On contemporary FPGA SoC platforms (e.g., AMD Xilinx Zynq UltraScale+), the CP module represents a modest fraction of the available logic resources for calibration sets up to several thousand samples, with the sorting network dominating the area cost and the inference-time comparison logic contributing minimal overhead.

Limitations of the CP hardware proposal. These resource estimates are analytical projections, not empirical measurements from a deployed implementation. The bitonic sorting network has $O\left(n{log}^{2}n\right)$ comparison complexity, which scales favorably but remains nontrivial for large calibration sets ($n>10,000$). The estimated latency of <1 μs applies only to the CP module overhead; end-to-end latency, including CNN inference, calibration score lookup, and AXI data transfer, will be substantially higher. We have not validated these estimates on silicon, and actual resource consumption and timing may differ due to routing congestion, clock domain crossings, and memory bandwidth contention. Empirical validation of the conformal prediction module on a physical FPGA platform—including latency measurements under varying calibration set sizes, resource utilization with accurate post-place-and-route numbers, and comparison against a GPU baseline with equivalent optimization—is an essential next step that we identify as a priority item in our research agenda (Section 11, Direction 1).

7.6. Research Gap Analysis

Figure 6 provides a visual summary of the safety-critical gap across eight ISO 26262 requirement dimensions, contrasting the current research coverage against the ASIL-D certification requirements. The substantial visual gap between the two polygons encapsulates the central finding of this review: research coverage barely registers on most safety dimensions.

Table 14. Safety-critical research gap analysis.

Gap Area	Current State	Required for Safety	Priority
Timing Analysis	Average case reported	WCET bounds (methods emerging [29,30,37])	Critical
Uncertainty Quantification	Not addressed	Calibrated confidence	Critical
DPR Verification	Simulation-based	Formal methods	High
Fault Tolerance	Not addressed	Detection/recovery	High
Certification Tools	Not available	Automated compliance	Medium
SOTIF Compliance	Not addressed	Triggering event analysis	Critical
AI Safety (ISO/PAS 8800)	Not addressed	Confidence monitoring	Critical

quantifies the identified gaps between the current research and safety-critical deployment requirements.

This analysis reveals that safety-critical FPGA SoC research is in its infancy, with significant opportunities for researchers to address the identified gaps.

7.7. Connection to Driver Drowsiness Detection

The driver drowsiness detection application motivating this research exemplifies the safety-critical constraints discussed above:

• Real-Time Requirement: Detection must complete within 100 ms to enable timely intervention.
• Uncertainty Awareness: Low-confidence predictions should trigger warnings or transition to alternative sensors.
• Calibration: Confidence estimates must be reliable across diverse lighting conditions, driver positions, and partial occlusions.
• FPGA Deployment: Hardware acceleration enables edge deployment without cloud dependency.

Conformal prediction provides the theoretical foundation for calibrated uncertainty in this context:

• Coverage Guarantee: 90% prediction sets cover the true label with user-specified probability.
• Adaptive Sets: Set size increases for difficult inputs, providing natural uncertainty indication.
• Efficient Computation: Quantile regression is implementable on resource-constrained FPGA platforms.

This survey positions uncertainty-aware FPGA accelerators as a critical research frontier, directly connecting to the broader theme of trustworthy AI for safety-critical transportation systems.

8. Discussion

8.1. Principal Findings and Interpretation

The synthesis reveals that FPGA-based reconfigurable parallel SoCs achieve robust scalability through DPR and modular architectures, with performance gains like 3× speedups and competitive energy efficiency stemming from optimized task partitioning that aligns hardware granularity with application demands [19,38].

8.1.1. Convergence on NoC Interconnects

A key pattern emerging from the literature is the convergence on networks-on-chip (NoCs) as a mechanistic linchpin for reconfigurable SoCs. NoC interconnects enable efficient data flow in heterogeneous setups where accelerators handle compute-intensive kernels while microprocessors manage control, thus exploiting instruction-level parallelism without the inefficiencies of superscalar general-purpose processors [13].

8.1.2. Evolution of Reconfiguration Methods

The trajectory from early configuration prefetching methods [70] to modern runtime-adaptive systems [21] reveals a clear evolution toward unified design flows. This progression only surfaces when synthesizing temporal trends across the 25-year span of included studies.

8.1.3. Performance Mechanisms

DPR minimizes downtime by targeting specific regions—such as LUTs for fine adjustments or overlays for medium-scale changes—allowing systems to reallocate resources dynamically, as seen in multi-grained tools that balance flexibility against overhead [23]. The consistent throughput improvements suggest underlying optimizations in DSP reuse and memory bandwidth that mitigate bottlenecks in parallel execution.

8.2. Comparison with Existing Literature

The findings align with the prior work on FPGA acceleration, where reconfigurable SoCs extend beyond static ASICs by offering 2–5× speedups in adaptive scenarios, mechanistically tied to partial reconfiguration’s ability to preserve static regions for uninterrupted parallelism [11].

8.2.1. Consistency with Prior Work

The consistency of the findings underscores the robustness of modular designs as NoC-based communication reduces latency in multi-FPGA setups, mirroring established benefits in scalable computing [70].

8.2.2. Resolution of Apparent Contradictions

Apparent contradictions in performance reporting were identified and resolved:

• Some studies claim linear scaling with resources, while others note suboptimal utilization in fixed-slot partitioning [51].
• This heterogeneity likely reflects methodological differences—earlier conceptual overviews versus recent empirical benchmarks on larger devices.
• Static evaluations suit prototyping [17], but dynamic workloads expose bottlenecks absent in controlled tests.

No publication bias was evident given the inclusion of reviews critiquing tool limitations [11]. Instead, the progression from early FPGA design flows [18] to HLS/OpenCL [51] in later studies suggests improved estimates, with earlier works potentially underestimating due to limited device densities.

8.3. Practical Implications

8.3.1. Edge AI Deployments

Reconfigurable SoCs with competitive throughput and energy efficiency enable real-time CNN inference in resource-limited devices, benefiting IoT sensors in surveillance where power < 5 W is critical. Partial reconfiguration allows task-specific tuning without hardware swaps [38].

8.3.2. Datacenter Settings

RAD architectures with NoC integration suit hyperscale providers handling variable workloads, warranting adoption for 2.6× performance gains in deep learning inference under fluctuating demands [52].

8.3.3. Medical Imaging

Multiplexed CNN processors with 97.3% accuracy at 340.7 μs inference support portable diagnostics in underserved areas, advising practitioners to prioritize Xilinx-based designs for low-latency pattern recognition [39].

8.3.4. Regulatory Considerations

Regulatory bodies should consider mandating DPR support in standards for high-performance computing as evidence of no safe “threshold” for reconfiguration overhead—persisting even in sub-millisecond updates—which implies system-wide efficiency mandates to avoid underutilization in safety-critical systems [11].

8.4. Strengths and Limitations of the Review

8.4.1. Strengths

• Comprehensive search across vast databases yielding diverse temporal coverage (1999–2024).
• Systematic thematic synthesis integrating design, performance, and application insights.
• Transparent extraction of structured data for cross-study comparisons.
• Evidence confidence assessment based on consistency and study quality.

8.4.2. Limitations of Included Studies

• Predominant focus on AMD Xilinx devices, potentially biasing generalizability to other FPGA families.
• Inconsistent quantitative reporting of metrics like exact LUT utilization.
• Conceptual emphases in early works lacking empirical depth.

8.4.3. Review Limitations

• Reliance on abstracts and extracted data without full-text access for all studies.
• Abstract-based screening may miss nuances in methodology.
• Absence of formal risk-of-bias assessment, although thematic analysis mitigates this by prioritizing consistent patterns.
• Cross-platform performance comparisons (FPGA vs. GPU vs. CPU) may reflect unequal optimization effort rather than inherent platform advantages; system-level costs (development time, tool licensing, and memory bottlenecks) are underreported in the surveyed literature and in our synthesis.

8.5. Evidence Summary

Table 15. Summary of evidence by theme.

Theme	Key Finding	Direction	Confidence
Design Approaches	Multi-grained tools, design flows	Positive	Moderate
Reconfiguration	DPR latency < 10 ms, 90% reduction	Positive	Strong
Parallel Arch.	3× speedup with NoC	Positive	Strong
Implementation	65% LUTs, 40% BRAM at 100 MHz	Positive	Moderate
Performance	Competitive throughput & efficiency	Positive	Moderate
Applications	Resource-multiplexing, DPR for CNNs	Positive	Strong

summarizes the evidence strength for each thematic finding.

9. Convergence–Divergence Analysis Framework

This section presents the convergence–divergence analysis (CDA), a structured exploratory framework for identifying research trajectory trends across the surveyed literature. The CDA provides a quantitative lens for understanding how different research threads within FPGA-based reconfigurable SoCs are evolving, offering qualitative trend identification and hypothesis generation rather than statistically validated predictions.

9.1. Framework Definition

The CDA framework analyzes research evolution along two dimensions:

• Convergence: When multiple research threads merge into unified approaches.
• Divergence: When research branches into specialized sub-fields.

We operationalize these concepts through three metrics:

• Citation Co-Occurrence: How frequently are two techniques cited together in later studies?
• Architecture Unification: Are separate components being integrated into single architectures?
• Tool Integration: Are design tools incorporating multiple techniques?

9.2. Convergence Score Calculation

Each convergence score is a composite metric computed from three equally weighted sub-indicators measured across the 36 primary studies:

• Citation Co-Occurrence (CC): The fraction of studies in a given period that cite both techniques together, indicating topical overlap in the community’s attention.
• Architecture Unification (AU): The fraction of studies that integrate both techniques within a single FPGA design, indicating practical convergence in implementations.
• Tool Integration (TI): The fraction of studies reporting use of shared design tools or toolchains that support both techniques, indicating infrastructure convergence.

The composite convergence score for each thread pair $(A,B)$ is defined as

$$\mathrm{CS}(A,B)={\displaystyle \frac{1}{3}}\left({\mathrm{CC}}_{\Delta }+{\mathrm{AU}}_{\Delta }+{\mathrm{TI}}_{\Delta }\right)$$

(4)

where each sub-indicator delta is the normalized increase between the early phase (pre-2015) and the recent phase (2019–2024)

$${\mathrm{CC}}_{\Delta }={\displaystyle \frac{{\mathrm{CC}}_{\mathrm{recent}}-{\mathrm{CC}}_{\mathrm{early}}}{1-{\mathrm{CC}}_{\mathrm{early}}}}$$

(5)

and analogously for ${\mathrm{AU}}_{\Delta }$ and ${\mathrm{TI}}_{\Delta }$. This normalization ensures that the score captures the relative gain in co-occurrence rather than the absolute difference, preventing bias toward thread pairs with low early-phase baselines. The “Early Phase” and “Recent Phase” columns in Table 16 report the CC component; the composite score incorporates all three sub-indicators. A score above 0.6 indicates strong convergence, 0.3–0.6 moderate convergence, and below 0.3 weak convergence or divergence.

Justification for equal weighting. The equal weighting of CC, AU, and TI ($w_{\mathrm{CC}}=w_{\mathrm{AU}}=w_{\mathrm{TI}}=1/3$) was chosen as the most neutral aggregation in the absence of an established theoretical framework for weighting bibliometric convergence indicators. This follows the principle of insufficient reason (Laplace): when no principled basis exists for preferential weighting, uniform weights minimize subjective bias. To assess the impact of this choice, our sensitivity analysis (below) tested inverse-variance weighting and single-indicator variants, finding that the convergence classifications (strong/moderate/weak) remain stable across reasonable weighting schemes. We acknowledge that future work could derive data-driven weights using expert survey or bibliometric calibration against external convergence criteria.

Table 16. Convergence metrics by research thread.

Thread Pair	Early Phase	Recent Phase	Conv. Score	Confidence
DPR + NoC	0.15	0.70	0.72	High
HLS + CNN	0.10	0.85	0.91	High
Edge + DPR	0.20	0.60	0.68	Moderate
CNN + Quantization	0.05	0.82	0.89	Moderate
NoC + Memory	0.30	0.55	0.45	Low

Table 16. Convergence metrics by research thread.

Thread Pair	Early Phase	Recent Phase	Conv. Score	Confidence
DPR + NoC	0.15	0.70	0.72	High
HLS + CNN	0.10	0.85	0.91	High
Edge + DPR	0.20	0.60	0.68	Moderate
CNN + Quantization	0.05	0.82	0.89	Moderate
NoC + Memory	0.30	0.55	0.45	Low

Sensitivity Analysis

To assess robustness of the convergence scores, we tested three variations of the CDA parameters. First, shifting the temporal split from pre/post-2015 to pre/post-2017 changed the mean absolute score by 0.04 (SD = 0.03), with no changes in convergence classification (strong/moderate/weak) for any thread pair. Second, replacing the equal-weighted average with inverse-variance weights derived from study counts per thread pair produced a maximum score change of 0.07 (CNN + Quantization: 0.89 → 0.82), again with no classification changes. Third, computing scores using only the CC sub-indicator (dropping AU and TI) yielded a Pearson correlation of $r=0.94$ with the composite scores, indicating that citation co-occurrence drives the majority of variance. These results suggest that the convergence classifications are robust to reasonable parameter variations, although the exact score magnitudes should be interpreted as indicative rather than precise.

Limitation. The CDA framework is a heuristic exploratory tool intended to synthesize qualitative trends in the research literature. With 36 primary studies, the sample size is insufficient for statistically validated inference, and the convergence scores should be interpreted as indicative trend magnitudes rather than precise measurements. Specifically: (1) the composite score normalization (Equation (5)) amplifies small absolute changes when early-phase baselines are near zero, potentially overstating convergence for thread pairs with low initial co-occurrence; (2) the equal weighting of the CC, AU, and TI sub-indicators has not been validated against an external ground truth; and (3) the scenario projections in Section 9 are qualitative extrapolations based on observed trends, not formal forecasting models. We present the CDA as a structured perspective that complements—but does not replace—expert judgment and bibliometric analysis.

9.3. Convergence Analysis

9.3.1. DPR + NoC Convergence

Analysis of citation patterns reveals strong convergence between dynamic partial reconfiguration and networks-on-chip:

• 2006–2012: Only 15% of DPR studies also addressed NoC integration;
• 2019–2024: 70% of DPR studies incorporate NoC communication;
• Convergence Score: 0.72 (high convergence).

This convergence reflects the practical need: DPR enables spatial reallocation while NoC provides the communication infrastructure to connect reconfigured modules.

9.3.2. HLS + CNN Acceleration Convergence

High-level synthesis tools and CNN acceleration show nearly complete convergence:

• Pre-2015: CNN accelerators primarily implemented in manual RTL;
• Post-2018: 85% of CNN accelerator papers use HLS;
• Convergence Score: 0.91 (very high convergence).

This convergence is driven by productivity requirements: CNN architecture evolution outpaces manual RTL development cycles.

9.3.3. Edge + DPR Convergence

Edge computing deployments increasingly leverage DPR for runtime adaptability:

• Edge Applications with DPR: 60% in recent phase vs. 20% in early phase;
• Edge+DPR+DNN: 45% of edge AI papers address all three;
• Convergence Score: 0.68 (moderate–high convergence).

9.4. Qualitative Scenario Projections

Based on the convergence–divergence patterns, we project the field evolution through 2030 as qualitative scenarios:

• Convergence to Unified Frameworks (2025–2027): DPR + NoC + HLS will converge into integrated design flows with automated exploration.
• Divergence into Safety-Critical vs. Best-Effort (2026–2028): Clear separation between safety-certified and performance-optimized research tracks.
• Convergence of Uncertainty + Acceleration (2027–2030): Integration of uncertainty quantification with CNN acceleration will become standard.
• Divergence of Edge vs. Cloud (Ongoing): Distinct optimization targets and methodologies for edge and cloud deployments.

Figure 7 visualizes the convergence scores from Table 16, revealing a clear stratification: four of five thread pairs exceed the strong convergence threshold (0.6), with HLS+CNN and CNN+Quantization showing near-complete integration (0.91 and 0.89). Only the NoC+Memory pair remains below the strong threshold, suggesting that memory architecture optimization has not yet converged with interconnect design—a potential area for targeted research investment.

9.5. Implications for Researchers

The CDA framework provides actionable insights:

• For new researchers: Enter at convergence points where unified frameworks are emerging; avoid investing in diverging sub-fields unless specific expertise exists.
• For funding agencies: Convergence areas (DPR+NoC+HLS integration and uncertainty quantification) represent high-impact opportunities; divergence areas may require specialized investment.
• For industry: Safety-critical specialization represents underexplored convergence opportunity combining DPR + uncertainty + certification.
• For tool developers: Unified design flows integrating current disparate tools represent significant market opportunity.

This analytical framework transforms the survey from a descriptive summary to a structured exploratory contribution, providing qualitative trend identification beyond what standard literature reviews offer.

10. Design Space Taxonomy and Decision Framework

This section presents a novel multi-dimensional taxonomy for classifying FPGA-based reconfigurable parallel processing SoC designs. The taxonomy provides researchers and practitioners with a structured framework for understanding the design space and selecting appropriate approaches based on application constraints.

10.1. Multi-Dimensional Taxonomy

We propose a four-dimensional classification system:

• Reconfigurability Granularity.
• Parallelism Exploitation.
• Design Automation Level.
• Safety Criticality.

10.1.1. Dimension 1: Reconfigurability Granularity

Reconfigurability granularity determines how finely hardware can be modified at runtime, ranging from no runtime adaptation to hierarchical multi-grained approaches.

Table 17. Reconfigurability granularity taxonomy.

Level	Description	Example
Static	No runtime reconfiguration	Fixed CNN accelerator
Partial (Coarse)	Module-level swapping	Accelerator substitution
Partial (Medium)	Overlay reconfiguration	DSP functional updates
Partial (Fine)	LUT-level tuning	Parameter adjustment
Full Adaptive	Hierarchical multi-grained	Combined approaches

presents the five-level taxonomy for this dimension. Static designs offer simplicity, while full adaptive approaches maximize flexibility at the cost of verification complexity.

10.1.2. Dimension 2: Parallelism Exploitation

Parallelism exploitation classifies how an architecture distributes computation across spatial and temporal dimensions.

Table 18. Parallelism exploitation taxonomy.

Type	Description	Implementation
Spatial Only	Fixed parallel resources	Unrolled loops, PEs
Temporal Only	Time-multiplexed resources	DPR-based sharing
Pipeline	Staged computation	Layer-by-layer streaming
Heterogeneous	Mixed PE types	CPU + GPU + FPGA SoC
Hybrid	Combined spatial/temporal	Adaptive resource allocation

summarizes the five types observed in the surveyed literature, from purely spatial designs to hybrid approaches that combine spatial and temporal parallelism.

10.1.3. Dimension 3: Design Automation Level

The design automation level captures the degree to which tooling abstracts the hardware implementation process.

Table 19. Design automation taxonomy.

Level	Tools	Trade-Off
Manual RTL	Verilog/VHDL	Maximum control, high effort
HLS-Guided	Vitis HLS, Intel HLS	Balanced productivity/control
Auto-ML	Vitis AI, NAS	High automation, limited control
Template-Based	DNNweaver, FINN	Domain optimization
End-to-End	Full stack	Minimum effort, opaque

presents the five-level taxonomy from manual RTL to end-to-end automated flows, each offering different trade-offs between designer control and development productivity.

10.1.4. Dimension 4: Safety Criticality

Safety criticality classifies designs by the rigor of their verification and certification requirements.

Table 20. Safety criticality taxonomy.

Level	Requirements	Standards
Best-Effort	None	None
Quality-Assured	Testing coverage	Internal QA
Deterministic	WCET bounds	IEC 61508 SIL-2
Safety-Certified	Formal verification	ISO 26262 ASIL-B/C
Mission-Critical	Fault tolerance	DO-254 DAL-A

presents the five-level taxonomy from best-effort to mission-critical, with corresponding standards and requirements at each level.

10.2. Decision Framework

The taxonomy enables systematic design decisions based on application constraints. Based on the surveyed literature, we provide recommendations in

Table 21. Recommended approach matrix.

Application	Latency	Power	Recommended Architecture	Confidence
CNN Inference (Edge)	<50 ms	<5 W	DPR + Quantization + Streaming	High
CNN Inference (Cloud)	Batch	>50 W	Spatial + HLS + Full Precision	High
Signal Processing	Real-Time	<10 W	NoC + Pipelined + DPR	Medium
Scientific HPC	Variable	>100 W	Multi-FPGA + NoC + Manual RTL	Medium
Safety-Critical	Deterministic	<10 W	DPR + Uncertainty + Formal	Low

, mapping application requirements to recommended architectural approaches.

Technology Selection Guidelines

• For latency-critical applications:
  • Choose spatial parallelism over temporal (DPR has overhead);
  • Use streaming architectures to minimize memory access;
  • Target II = 1 in HLS for critical loops.
• For power-constrained applications:
  • Aggressive quantization (INT8 minimum, consider binary);
  • DPR for time-sharing expensive resources;
  • Clock gating and power-aware HLS directives.
• For safety-critical applications:
  • Uncertainty quantification for confidence estimation;
  • WCET analysis for all timing paths;
  • Consider manual RTL for critical sections.
• For productivity-focused projects:
  • HLS with domain-specific libraries (Vitis AI);
  • Template-based design for standard workloads;
  • Accept 10–30% efficiency trade-off.

10.3. Design Space Coverage Analysis

We analyzed the surveyed studies against our taxonomy.

Table 22. Design space coverage.

	Edge AI	Cloud HPC	Signal Proc.	Safety-Critical
Studies	8	5	7	3
Coverage	High	High	Medium	Low
Tools Available	Mature	Mature	Maturing	Emerging
Confidence	High	High	Medium	Low

summarizes the design space coverage across four application domains.

Key Finding: Only 3 of 36 surveyed studies (8%) address safety certification requirements, representing the most significant gap in the FPGA reconfigurable SoC design space.

This taxonomy provides immediate practical value to practitioners while also revealing underexplored research directions, adding novel contribution beyond standard survey content.

11. Research Agenda

This section presents a quantified research agenda derived from the gap analysis in Section 5, Section 6, Section 7, Section 8, Section 9 and Section 10. Unlike generic “future work” sections, we provide specific research problems, proposed approaches, and estimated complexity to guide future efforts. Figure 8 summarizes the proposed three-phase roadmap spanning 2025–2030, progressing from foundational benchmarks and uncertainty-aware CNN implementations (Phase 1), through integration of unified design flows with WCET analysis (Phase 2), to safety-certified prototypes validated on real-world deployments (Phase 3). Each phase is detailed in the subsections below.

11.1. Evidence Gaps

The systematic review reveals four evidence gaps that limit the generalizability of the current findings:

• Non-Xilinx Implementations: Sparse reporting on Intel (Altera) Stratix, Lattice, and Microsemi platforms limits applicability to diverse FPGA ecosystems. The 66% concentration on AMD Xilinx devices creates potential bias in design conclusions and tool compatibility assumptions.
• Inconsistent Metrics: Heterogeneous performance reporting (peak vs. sustained throughput; batch vs. single-sample latency) prevents quantitative cross-study synthesis of safety-relevant parameters.
• Missing Mechanistic Details: Physical-level analysis of routing delays, power pathways during DPR, and configuration memory fault propagation is absent, leaving causal links between architecture and performance unproven.
• Scalability Contradictions: Contradictions in scaling behavior (linear growth vs. fixed-slot limits) remain unresolved due to varying benchmarks, with no replication in safety-critical domains.

11.2. Prioritized Research Gaps

Table 23. Quantified research gaps.

Gap	Current Limitation	Proposed Approach	Complexity	Timeline
Uncertainty in HW	No confidence estimates	Conformal prediction	Medium	1–2 years
DPR Safety	No ASIL-compliant DPR	Formal verification	High	2–3 years
WCET Bounds	Average case only; methods emerging [29,30]	Extend multi-DPU WCET to DPR	High	1–2 years
SOTIF Compliance	Not addressed	Triggering event + prediction sets	High	1–2 years
ISO/PAS 8800	Not addressed	Confidence monitoring	Medium	1–2 years
Benchmark Std.	Incomparable metrics	Open suite proposal	Low	6 months
Cross-Domain	Not validated	Transfer learning	Medium	1–2 years
Tool Integration	Fragmented flows	Unified framework	High	2–3 years

summarizes the prioritized research gaps derived from our analysis.

11.3. Research Directions

Direction 1: Uncertainty-Aware Hardware Acceleration. The current CNN accelerators provide point predictions without calibrated confidence. We propose implementing conformal prediction on FPGA (Section 7) with quantile regression in HLS, targeting 90% coverage guarantees with <15% hardware overhead and <20% latency increase. Expected outcome: FPGA accelerator producing prediction sets with guaranteed coverage.

Direction 2: Safety-Certified Dynamic Partial Reconfiguration. No existing DPR methodology addresses the ISO 26262 requirements, and SOTIF compliance (ISO 21448) for dynamically reconfigured AI inference remains unexplored. We propose developing formal models of DPR state transitions, WCET analysis for reconfiguration operations, and an ASIL-B-compliant reconfiguration controller. Expected outcome: a formal verification framework with WCET bounds (building on Zhang et al. [30]), ISO 26262 compliance guidelines, and ISO 21448 triggering event analysis for reconfigurable AI inference.

Direction 3: Standardized Benchmark Suite. The surveyed studies report incomparable metrics, making quantitative synthesis difficult. We propose defining standardized workloads (CNN inference and signal processing), specifying required reporting metrics (throughput, efficiency, latency, and WCET), and creating reference implementations for common FPGAs. Expected outcome: community-accepted benchmark suite enabling normalized performance comparisons.

Direction 4: Unified Design Flow Integration. The current tools require manual integration of HLS, DPR, and NoC design. We propose a specification language for DPR+NoC systems, automated floorplanning for reconfiguration regions, and closed-loop optimization across design dimensions. Expected outcome: 50% reduction in design time for DPR systems with automated trade-off exploration.

Direction 5: Cross-Domain Transfer Validation. Techniques validated in one domain may not transfer to other safety-critical domains. We propose systematic evaluation of transferability, identification of domain-specific constraints, and validation using the driver drowsiness detection case study. Expected outcome: taxonomy of transferable vs. domain-specific techniques with adaptation guidelines.

11.4. Research Roadmap

We propose a phased research roadmap:

• Phase 1 (Year 1): Foundation—Benchmark standardization proposal; uncertainty-aware CNN implementation; survey of formal DPR methods; SOTIF triggering event analysis for FPGA-based AI.
• Phase 2 (Year 2): Integration—Unified design flow prototype; WCET analysis for DPR extending Zhang et al. [30]; cross-domain transfer study; ISO/PAS 8800 confidence monitoring integration.
• Phase 3 (Year 3): Validation—Safety-certified prototype; benchmark suite validation; real-world deployment case study.

11.5. Opportunities for Researchers

• For practitioners: Benchmark standardization offers immediate contribution with moderate effort.
• For systems researchers: A unified design flow addresses critical productivity barriers.
• For safety researchers: DPR safety certification is a high-impact, high-effort opportunity.
• For ML/HW researchers: Uncertainty-aware acceleration connects expertise to safety-critical applications.
• For PhD students: The drowsiness detection application provides a concrete case study for validating techniques.

This research agenda transforms our survey from a passive summary into an active guide for future research, providing specific directions with estimated timelines and expected outcomes.

12. Conclusions

12.1. Key Findings

This systematic review of 36 studies spanning 25 years of FPGA reconfigurable SoC research yields six principal findings:

• Safety certification is universally neglected: 33 out of the 36 (92%) surveyed studies ignore safety certification requirements entirely (ISO 26262 and IEC 61508), focusing solely on average-case performance metrics without worst-case execution time analysis.
• FPGA CNN accelerators achieve competitive efficiency: Performance has progressed from 61.6 GOPS [20] to 294 GOPS [44], with competitive energy efficiency [38], yet none provide WCET bounds or uncertainty quantification.
• DPR enables adaptation but lacks verification: Dynamic partial reconfiguration achieves sub-10 ms latency [21] and 2–5× throughput improvement [22,24], but no study addresses timing verification across configuration combinations.
• Research threads are converging: The convergence–divergence analysis (Section 9) reveals convergence scores of 0.72–0.91 for the DPR, NoC, and HLS threads, indicating increasing research coherence.
• No ASIL-compliant implementations exist: Despite ISO 26262 mandating deterministic timing for ASIL-B and above, no surveyed FPGA implementation provides the formal verification or timing guarantees required for certification.
• Conformal prediction bridges the gap: CP offers a distribution-free framework for uncertainty quantification with finite-sample coverage guarantees that is computationally compatible with FPGA implementation, representing a promising research direction for certifiable AI inference.

12.2. Confidence Assessment

• Strong confidence: DPR effectiveness for latency reduction (<10 ms) and parallel speedup (3×) is supported by eight or more convergent implementations.
• Moderate confidence: CNN acceleration performance metrics show consistent directions but heterogeneous measurement methodologies.
• Tentative: Scalability claims and universal resource metrics require further validation due to limited replication across device generations.

12.3. Critical Uncertainty

The most significant open problem is the safety-critical gap: the chasm between impressive average-case performance and the absence of worst-case guarantees, fault tolerance, and certification artifacts. Until FPGA implementations can demonstrate ASIL compliance through formal timing analysis, fault injection testing, and configuration integrity verification, deployment in safety-critical automotive systems remains infeasible regardless of throughput achievements.

12.4. Threats to Validity

We acknowledge the following threats to the validity of this review:

• Internal validity: The safety-awareness classification (Table 13) relies on reported content in published papers; studies may have addressed safety considerations without explicitly reporting them. The binary safety-aware classification may undercount studies with partial or informal safety considerations.
• Selection bias: The inclusion criterion requiring FPGA hardware implementation excludes simulation-based safety research and formal verification studies that address safety certification without physical deployment. This scope decision focuses the review on implementation practices but may underestimate the broader community’s engagement with safety, particularly in the formal methods literature. Readers should interpret the 92% safety gap as specific to hardware-implemented FPGA accelerator studies, not the full spectrum of safety-related FPGA research.
• Sample size: With 36 included studies, quantitative generalizations are limited. The CDA convergence scores should be interpreted as indicative rather than statistically significant. Confidence intervals for the 92% safety gap estimate, assuming a binomial distribution, yield a 95% confidence interval of [77%, 98%], indicating that the finding is robust despite the small sample.
• Construct validity: The CDA framework uses heuristic metrics (CC, AU, and TI) with equal weighting. Alternative weighting schemes or different temporal splits may yield different convergence classifications, although our sensitivity analysis (Section 9) suggests stability under reasonable parameter variations.
• Evaluation criteria alignment: Assessing exploratory academic prototypes against ASIL-D certification requirements may appear misaligned as most studies were not designed with certification as a goal. We adopt this lens intentionally as a forward-looking gap analysis, not as a criticism of individual studies.
• Database coverage: The formal search was limited to Scopus, IEEE Xplore, Web of Science, and ACM Digital Library. Relevant studies published in venue-specific proceedings, institutional repositories, or non-English languages may be underrepresented.
• Publication bias: Studies with positive results are more likely to be published, potentially inflating the reported performance metrics (GOPS and GOPS/W) relative to typical implementations. Studies that failed to achieve safety certification may be underrepresented due to the “file drawer” effect.
• Temporal validity: The search was conducted in early 2025. Rapid developments in FPGA-based AI acceleration, particularly from major vendors (AMD/Xilinx and Intel/Altera), may shift the landscape significantly by the time of publication.

12.5. Key Takeaway

The FPGA reconfigurable computing community must transition from performance-only optimization to safety-certified design. The convergence of DPR, NoC, and HLS research threads creates a foundation for integrated systems, but safety certification remains the critical missing element. Conformal prediction, with its distribution-free coverage guarantees and hardware-compatible computation, represents a compelling research frontier for enabling trustworthy AI on resource-constrained FPGA platforms. The proposed research agenda (Section 11) provides a phased roadmap toward this goal, with the drowsiness detection application serving as a concrete validation case study.