Search Results (11)

In this work, a unified design methodology for front-end RF/mmWave receivers is presented, aiming to significantly accelerate the design procedure of the front-end RF blocks in complex RX/TX chain implementations. The proposed design methodology is based on optimization loops with well-defined cost functions so as to minimize the design iterations that may be encountered during specification tuning. As proof of concept, two essential RF blocks widely used in RF receivers, a low-noise amplifier (LNA) and a voltage-controlled oscillator (VCO), were designed using the proposed unified methodology with a 65 nm RF-CMOS processing node. Finally, the derived designs were compared to similar designs in the literature, proving that the proposed unified methodology is capable of synthesizing RF/mmWave LNAs and VCOs with industry-standard specifications within a significantly faster time frame. Full article

A new dual-band low-noise amplifier (LNA) operating at L1/E1 1.575 GHz and L5/E5 1.192 GHz center frequencies for global navigation satellite system receivers is proposed. A doubled common-source amplifier architecture is used with a single input, shared gate inductor, and two outputs to split the RF signal into separate RX channels. The main advantage of the proposed circuit is compatibility with widespread multi-band antennas with single RF connectors dedicated to high-precision applications, as well as the possibility to use cheap SAW filters with small footprints to build low-cost, highly accurate GNSS receiver modules. The input and both outputs are well matched to 50 Ω impedance. The LNA is designed with a 110 nm CMOS process, consuming 6.13 mA current from a 1.5 V supply. The measured noise figures and voltage gains of the dual-band LNA are, respectively, NF1/NF5 = 3.23/3.5 dB and G1/G5 = 21.22/18.2 dB in the band of interest for each channel. The measured impedance matching at the input (S11) and output (S22) of the dual-band low-frequency amplifier is as follows: S11_L1 = −23.89, S11_L5 = −8.42, S22_L1 = −12.65, S22_L5 = −15.08. The one-decibel compression points are L1 band PdB1 = −37.71 dBm and L5 band PdB5 = −34.72 dBm, respectively. Full article

A fully integrated 24-GHz radar transceiver with one transmitter (TX) and two receivers (RXs) for compact frequency modulated continuous wave (FMCW) radar applications is here presented. The FMCW synthesizer was realized using a fractional-N phase-locked loop (PLL) and programmable chirp generator, which are completely integrated in the proposed transceiver. The measured output phase noise of the synthesizer is −80 dBc/Hz at 100 kHz offset. The TX consists of a three-bit bridged t-type attenuator for gain control, a two-stage drive amplifier (DA) and a one-stage power amplifier (PA). The TX chain provides an output power of 13 dBm while achieving <0.5 dB output power variation within the range of 24 to 24.25 GHz. The RX with a direct conversion I-Q structure is composed of a two-stage low noise amplifier (LNA), I-Q generator, mixer, transimpedance amplifier (TIA), a two-stage biquad band pass filter (BPF), and a differential-to-single (DTS) amplifier. The TIA and the BPF employ a DC offset cancellation (DCOC) circuit to suppress the strong reflection signal and TX-RX leakage. The RX chain exhibits an overall gain of 100 dB. The proposed radar transceiver is fabricated using a 65 nm CMOS technology. The transceiver consumes 220 mW from a 1 V supply voltage and has 4.84 mm² die size including all pads. The prototype FMCW radar is realized with the proposed transceiver and Yagi antenna to verify the radar functionality, such as the distance and angle of targets. Full article

The integration of wireless communication, e.g., in real- or quasi-real-time applications, is related to many challenges such as energy consumption, communication range, quality of service, and reliability. The improvement of wireless sensor networks (WSN) performance starts by enhancing the capabilities of each sensor node. To minimize latencies without increasing energy consumption, wake-up receiver (WuRx) nodes have been introduced in recent works since they can be always-on or power-gated with short latencies by a power consumption in the range of some microwatts. Compared to standard receiver technologies, they are usually characterized by drawbacks in terms of sensitivity. To overcome the limitation of the sensitivity of WuRxs, a design of a low noise amplifier (LNA) with several design specifications is required. The challenging task of the LNA design is to provide equitable trade-off performances such as gain, power consumption, the noise figure, stability, linearity, and impedance matching. The design of fast settling LNA for a duty-cycled WuRx front-end operating at a 868 MHz frequency band is investigated in this work. The paper details the trade-offs between design challenges and illustrates practical considerations for the simulation and implementation of a radio frequency (RF) circuit. The implemented LNA competes with many commercialized designs where it reaches single-stage 12 dB gain at a 1.8 V voltage supply and consumes only a 1.6 mA current. The obtained results could be made tunable by working with off-the-shelf components for different wake-up based application exigencies. Full article

This work presents a high efficiency RF-to-DC conversion circuit composed of an LC-CL balun-based Gm-boosting envelope detector, a low noise baseband amplifier, and an offset canceled latch comparator. It was designed to have high sensitivity with low power consumption for wake-up receiver (WuRx) applications. The proposed envelope detector is based on a fully integrated inductively degenerated common-source amplifier with a series gate inductor. The LC-CL balun circuit is merged with the core of the envelope detector by sharing the on-chip gate and source inductors. The proposed technique doubles the transconductance of the input transistor of the envelope detector without any extra power consumption because the gate and source voltage on the input transistor operates in a differential mode. This results in a higher RF-to-DC conversion gain. In order to improve the sensitivity of the wake-up radio, the DC offset of the latch comparator circuit is canceled by controlling the body bias voltage of a pair of differential input transistors through a binary-weighted current source cell. In addition, the hysteresis characteristic is implemented in order to avoid unstable operation by the large noise at the compared signal. The hysteresis window is programmable by changing the channel width of the latch transistor. The low noise baseband amplifier amplifies the output signal of the envelope detector and transfers it into the comparator circuit with low noise. For the 2.4 GHz WuRx, the proposed envelope detector with no external matching components shows the simulated conversion gain of about 16.79 V/V when the input power is around the sensitivity of −60 dBm, and this is 1.7 times higher than that of the conventional envelope detector with the same current and load. The proposed RF-to-DC conversion circuit (WuRx) achieves a sensitivity of about −65.4 dBm based on 45% to 55% duty, dissipating a power of 22 μW from a 1.2 V supply voltage. Full article

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications. Full article

This study presents a low-power Zigbee receiver with a current-reusing structure and function-reused mixing techniques. To reduce the overall power consumption, a low noise amplifier (LNA) and a power amplifier (PA) share the biasing current with a voltage-controlled oscillator (VCO) in the receiving (RX) mode and transmitting (TX) mode, respectively. The function-reused mixer reuses the radio frequency trans-conductance (RF gm) stage to amplify the down-converted intermediate frequency (IF) signal, obtaining a free IF gain without extra power consumption. A peak detector circuit detects the receiving signal strength and auto-adjusts the biasing current to save power when a strong signal strength is detected. Meanwhile, the peak detector helps to provide a coarse gain control as part of the auto-gain-control function. As part of the IF gain range is shared by the multiple-feedback (MFB) low-pass filter, the number of programmable-gain IF amplifier stages can be reduced, which also means a decrease in power consumption. A prototype of this wireless sensor network (WSN) receiver was designed and fabricated using the TSMC 130 nm CMOS process under a supply voltage of 1 V. The entire receiver realizes a noise figure (NF) of 3.5 dB and a receiving sensitivity of −90 dBm for the 0.25 Mbps offset quadrature phase shift keying (O-QPSK) signal with a power consumption of 2.9 mW. Full article

In this paper, an inductive-power-transmission (IPT) system for a wearable textile heater is proposed to comfortably provide heating to a user’s body. The conductive thread, which has high electrical resistance, was sewn into a receiver (Rx) coil on clothing to generate high temperature with a low current. The proposed wearable heaters are completely washable thanks to their nonmetallic materials, other than conductive threads in the clothing. We introduced series-none (SN) topology to eliminate a resonant capacitor in the wearable textile heater. A single resonant capacitor in a transmitter (Tx) in SN mode was implemented to resonate both Tx and Rx, resulting in increased power delivered to the load (PDL) while maintaining high-power transfer efficiency (PTE), comparable with conventional series-series (SS) topology. When the supply voltage of the power amplifier was 7 V, while the PTE of the SS and SN modes was 85.2% and 75.8%, respectively, the PDL of the SS and SN modes was 2.74 and 4.6 W, respectively. Full article

This paper presents an analog front-end transceiver for an ultrasound imaging system based on a high-voltage (HV) transmitter, a low-noise front-end amplifier (RX), and a complementary-metal-oxide-semiconductor, aluminum nitride, piezoelectric micromachined ultrasonic transducer (CMOS-AlN-PMUT). The system was designed using the 0.13-μm Silterra CMOS process and the MEMS-on-CMOS platform, which allowed for the implementation of an AlN PMUT on top of the CMOS-integrated circuit. The HV transmitter drives a column of six 80-μm-square PMUTs excited with 32 V in order to generate enough acoustic pressure at a 2.1-mm axial distance. On the reception side, another six 80-μm-square PMUT columns convert the received echo into an electric charge that is amplified by the receiver front-end amplifier. A comparative analysis between a voltage front-end amplifier (VA) based on capacitive integration and a charge-sensitive front-end amplifier (CSA) is presented. Electrical and acoustic experiments successfully demonstrated the functionality of the designed low-power analog front-end circuitry, which outperformed a state-of-the art front-end application-specific integrated circuit (ASIC) in terms of power consumption, noise performance, and area. Full article

This paper presents a low power Gaussian Frequency-Shift Keying (GFSK) transceiver (TRX) with high efficiency power management unit and integrated Single-Pole Double-Throw switch for Bluetooth low energy application. Receiver (RX) is implemented with the RF front-end with an inductor-less low-noise transconductance amplifier and 25% duty-cycle current-driven passive mixers, and low-IF baseband analog with a complex Band Pass Filter(BPF). A transmitter (TX) employs an analog phase-locked loop (PLL) with one-point GFSK modulation and class-D digital Power Amplifier (PA) to reduce current consumption. In the analog PLL, low power Voltage Controlled Oscillator (VCO) is designed and the automatic bandwidth calibration is proposed to optimize bandwidth, settling time, and phase noise by adjusting the charge pump current, VCO gain, and resistor and capacitor values of the loop filter. The Analog Digital Converter (ADC) adopts straightforward architecture to reduce current consumption. The DC-DC buck converter operates by automatically selecting an optimum mode among triple modes, Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), and retention, depending on load current. The TRX is implemented using 1P6M 55-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology and the die area is 1.79 mm². TRX consumes 5 mW on RX and 6 mW on the TX when PA is 0-dBm. Measured sensitivity of RX is −95 dBm at 2.44 GHz. Efficiency of the DC-DC buck converter is over 89% when the load current is higher than 2.5 mA in the PWM mode. Quiescent current consumption is 400 nA from a supply voltage of 3 V in the retention mode. Full article

In this work, a low cost Bluetooth Low Energy (BLE) transceiver for wireless sensor network (WSN) applications, with a receiver (RX) matching network reusing power amplifier (PA) load inductor, is presented. In order to decrease the die area, only two inductors were used in this work. Besides the one used in the voltage control oscillator (VCO), the PA load inductor was reused as the RX impedance matching component in the front-end. Proper controls have been applied to achieve high transmitter (TX) input impedance when the transceiver is in the receiving mode, and vice versa. This allows the TRX-switch/matching network integration without significant performance degradation. The RX adopted a low-IF structure and integrated a single-ended low noise amplifier (LNA), a current bleeding mixer, a 4th complex filter and a delta-sigma continuous time (CT) analog-to-digital converter (ADC). The TX employed a two-point PLL-based architecture with a non-linear PA. The RX achieved a sensitivity of −93 dBm and consumes 9.7 mW, while the TX achieved a 2.97% error vector magnitude (EVM) with 9.4 mW at 0 dBm output power. This design was fabricated in a 0.11 μm complementary metal oxide semiconductor (CMOS) technology and the front-end circuit only occupies 0.24 mm². The measurement results verify the effectiveness and applicability of the proposed BLE transceiver for WSN applications. Full article