A Linearity Improvement Front End with Subharmonic Current Commutating Passive Mixer for 2.4 GHz Direct Conversion Receiver in 0.13 µ m CMOS Technology

: Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, ﬂicker noise and direct current (DC) o ﬀ set are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no ﬂicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming e ﬀ ectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisﬁes modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise ampliﬁer (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the ﬁrst time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 µ m complementary metal oxide semiconductor (CMOS) process with a chip area of 750 µ m × 1270 µ m. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise ﬁgure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC o ﬀ set with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC o ﬀ set, good gain and NF, moderate IIP3 and the highest ﬁgure of merit compared to the state-of-the-art publications.


Introduction
Today, portable electronic devices with less power consumption are urgently required. Therefore, integrated circuit (IC) designers have drawn much attention to direct-conversion transceiver architectures because of their low cost, low power and ease of integration. To implement a direct-conversion receiver successfully, frequency-conversion circuits should be carefully designed because the DC offset and flicker noise generated by a down mixer could significantly corrupt the output signal-to-noise ratio (SNR) in the receiver path and the large leakage of the local oscillator (LO) to radio RF port could severely degrade the linearity of the system [1,2]. The subharmonic RF front end, in which the LO frequency is half the RF frequency, overcomes the DC offset effectively because the RF signal mixes with the LO signal, which feeds through into the RF port that is out of band [3][4][5][6][7][8]. The absence of a DC current in the current commutating passive mixer has no 1/f noise [9,10]. Hence, the subharmonic passive current-driven mixer topology is suitable for the direct conversion receiver. The crowded RF band and monolithic integration of the transceiver have required designers to increasingly focus on linearity [11,12]; however, the linearity of subharmonic mixer topology has not been discussed much. In Reference [13], a 25% duty cycle LO switching is implemented to improve the second-order intermodulation intercept point (IIP2) of the subharmonic mixer (SHM). References [14,15] used the second-order intermodulation (IM2) current injection method to improve the active SHM linearity, but the flicker noise was higher than the passive SHM. The authors of [5] used a common gate (CG)-common source (CS) LNA with a positive-or negativefeedback technique to improve LNA linearity, but they did not include a mixer core. A resistively degenerated method is introduced for the passive current driving mixer architecture to improve NF and linearity [16].
To implement a high linearity RF front end with current driving passive SHM, some linearity improvement methods have been introduced. For LNA, the complementary derivative superposition (DS) method is used to improve IIP3. With more mixer core cascades than a conventional current driving passive mixer, the on-resistance of SHM is more sensitive to the front end. The feedforward body bias (FBB) is applied to reduce the on-resistance and can improve linearity. The quadrature square-like LO is needed for one channel of SHM. The polyphase filter and LO buffer are carefully designed and deeply discussed in this paper. The 2.4-GHz subharmonic RF front end is implemented in a 0.13-μm CMOS process.

Proposed LNA Design
The circuit's block diagram is shown in Figure 1, where TIA is a transimpedance amplifier and PPF is a polyphase filter. The differential RF and LO inputs are obtained by an off-chip balun. The first stage of the circuit is a cascoded inductively degenerated common source (IDCS) LNA with an improvement in linearity. The cascode structure provides better reverse isolation than a common-source structure, avoiding the large LO leakage back into the RF input.   For the cascoded IDSC LNA, the degeneration inductor is transformed at the input to create a resistive portion to the input impedance. With proper selection of g m , C gs and L d , the input of the amplifier can be matched to R s for maximum power transfer. With degeneration, the second-order tones generated from the second-order nonlinearities are fed back to mix with the fundamental tones at the input, creating third-order tones. Hence, the third-order intermodulation (IM3) with feedback consists of two contributions: one from the third-order nonlinearity of the transistor and the other from the second-order nonlinearity. The authors of [17] used an IM3 sinker to improve the linearity of LNA, but they did not consider the feedback of second-order tones. The authors of [18] introduced a modified superposition method for linearizing LNA. In the LNA proposed this paper, as illustrated in Figure 2a, positive metal oxide semiconductor (PMOS) (M 5 and M 6 ) and negative metal oxide semiconductor (NMOS aux ) (M 3 and M 4 ) were introduced to eliminate the second-and third-order distortions. M 1 and M 2 were biased to the strong inversion state for high conversion gain. The inputs of PMOS M 5 and M 6 were cross-connected with the inputs of M 1 and M 2 and were also biased to the strong inversion state, while M 3 and M 4 were biased to the weak inversion state. For the cascoded IDSC LNA, the degeneration inductor is transformed at the input to create a resistive portion to the input impedance. With proper selection of gm, Cgs and Ld, the input of the amplifier can be matched to Rs for maximum power transfer. With degeneration, the second-order tones generated from the second-order nonlinearities are fed back to mix with the fundamental tones at the input, creating third-order tones. Hence, the third-order intermodulation (IM3) with feedback consists of two contributions: one from the third-order nonlinearity of the transistor and the other from the second-order nonlinearity. The authors of [17] used an IM3 sinker to improve the linearity of LNA, but they did not consider the feedback of second-order tones. The authors of [18] introduced a modified superposition method for linearizing LNA. In the LNA proposed this paper, as illustrated in Figure 2a, positive metal oxide semiconductor (PMOS) (M5 and M6) and negative metal oxide semiconductor (NMOSaux ) (M3 and M4) were introduced to eliminate the second-and third-order distortions. M1 and M2 were biased to the strong inversion state for high conversion gain. The inputs of PMOS M5 and M6 were cross-connected with the inputs of M1 and M2 and were also biased to the strong inversion state, while M3 and M4 were biased to the weak inversion state. According to Kirchhoff's current law, as depicted in Figure 2b: In general, the drain current ids of an MOS transistor can be expressed as: By carefully designing the sizes of M1, M3 and M5, as well as the bias voltage, we get: The second-and third-order nonlinearities of the main NMOS are eliminated simultaneously, as shown in Figure 3; thus, the linearity is notably improved. According to Kirchhoff's current law, as depicted in Figure 2b: In general, the drain current i ds of an MOS transistor can be expressed as: By substituting Equation (1) into Equation (2), we can get: By carefully designing the sizes of M 1 , M 3 and M 5 , as well as the bias voltage, we get: The second-and third-order nonlinearities of the main NMOS are eliminated simultaneously, as shown in Figure 3; thus, the linearity is notably improved.  Referring to the notation in [18], the third-order intermodulation distortion (IMD3) of the drain current of a traditional IDCS LNA is proportional to: In this paper, 3    Referring to the notation in [18], the third-order intermodulation distortion (IMD3) of the drain current of a traditional IDCS LNA is proportional to: In this paper, g 3 = g 1m3 + g 5m3 + g 3m3 and g 2 = g 1m2 − g 5m2 + g 3m2 . Figure 4a,b shows the improvement in linearity of the LNA with PMOS and NMOS aux .  Referring to the notation in [18], the third-order intermodulation distortion (IMD3) of the drain current of a traditional IDCS LNA is proportional to: In this paper, 3

Current Commutating Subharmonic Passive Mixer Design
The second stage of the circuit is a current commutating subharmonic passive mixer (Figure 6a), in which the bias circuit is not given. Transistors M1-M4 form the first stage, which is a regular doublebalanced passive mixer, while transistors M5-M8 form the second stage to achieve subharmonic mixing. In every quarter-cycle, two of the first-and second-stage transistors are turned on, modulating the current to the intermediate frequency (IF) port. It can be observed that, in one complete cycle of the LO, the current from LNA is commutated four times, and, hence, at twice the LO frequency. Thus, this circuit can be regarded as a passive mixer with square-wave switching at twice the LO frequency, as illustrated in Figure 6b [19]. Because the passive mixers exhibit intrinsic bidirectionality, the TIA amplifier and LNA coinfluence the performance of the mixer core, thus the analysis of the mixer core cannot be done separately. Because of the influence of the current, the output impedance of the LNA and the mixer core should be as high as possible, while the input impedance of the mixer core and the TIA should be as low as possible. Therefore, a high Q LC parallel circuit is not good for LNA gain but is necessary

Current Commutating Subharmonic Passive Mixer Design
The second stage of the circuit is a current commutating subharmonic passive mixer (Figure 6a), in which the bias circuit is not given. Transistors M 1 -M 4 form the first stage, which is a regular double-balanced passive mixer, while transistors M 5 -M 8 form the second stage to achieve subharmonic mixing. In every quarter-cycle, two of the first-and second-stage transistors are turned on, modulating the current to the intermediate frequency (IF) port. It can be observed that, in one complete cycle of the LO, the current from LNA is commutated four times, and, hence, at twice the LO frequency. Thus, this circuit can be regarded as a passive mixer with square-wave switching at twice the LO frequency, as illustrated in Figure 6b [19].

Current Commutating Subharmonic Passive Mixer Design
The second stage of the circuit is a current commutating subharmonic passive mixer (Figure 6a), in which the bias circuit is not given. Transistors M1-M4 form the first stage, which is a regular doublebalanced passive mixer, while transistors M5-M8 form the second stage to achieve subharmonic mixing. In every quarter-cycle, two of the first-and second-stage transistors are turned on, modulating the current to the intermediate frequency (IF) port. It can be observed that, in one complete cycle of the LO, the current from LNA is commutated four times, and, hence, at twice the LO frequency. Thus, this circuit can be regarded as a passive mixer with square-wave switching at twice the LO frequency, as illustrated in Figure 6b [19]. Because the passive mixers exhibit intrinsic bidirectionality, the TIA amplifier and LNA coinfluence the performance of the mixer core, thus the analysis of the mixer core cannot be done separately. Because of the influence of the current, the output impedance of the LNA and the mixer core should be as high as possible, while the input impedance of the mixer core and the TIA should be as low as possible. Therefore, a high Q LC parallel circuit is not good for LNA gain but is necessary Because the passive mixers exhibit intrinsic bidirectionality, the TIA amplifier and LNA co-influence the performance of the mixer core, thus the analysis of the mixer core cannot be done separately. Because of the influence of the current, the output impedance of the LNA and the mixer core should be as high as possible, while the input impedance of the mixer core and the TIA should be as low as possible. Therefore, a high Q LC parallel circuit is not good for LNA gain but is necessary for enhancing the performance of the mixer core. Figure 7a is the equivalent circuit of the front end. For simplicity, we only consider half of Figure 7a, and this circuit is simplified as Figure 7b, where R sw is the on-resistance of MOS switch. For the ideal switch consideration, we express it on the Fourier series, where a n is the nth Fourier coefficient. The derivation formula of the input impedance is given in [9]; in this paper, the input impedance was changed to (9), twice the on-resistance of the double-balanced mixer (DBM).
The value of the output impedance of the mixer core decreases because of a more cascaded MOS switch than the conventional DBM, as shown in (10), where Cpar is the parasitic capacitance of the mixer core. A small R mix_out has negative effects on the noise of the TIA. Of course, the big size of the mixer core introduces large capacitance, which leads to a finite rise and fall time of the LO. Furthermore, NF and linearity also worsen [10,20,21]. Hence, the size of the mixer core should be set carefully under both noise and gain considerations. The bias voltage V G of the mixer core is another important parameter for the performance of the mixer core. V G should be set a bit higher to ensure that the mixer core works in the on-overlap state [10].
Electronics 2020, 9, x FOR PEER REVIEW 6 of 18 for enhancing the performance of the mixer core. Figure 7a is the equivalent circuit of the front end.
For simplicity, we only consider half of Figure 7a, and this circuit is simplified as Figure 7b, where Rsw is the on-resistance of MOS switch. For the ideal switch consideration, we express it on the Fourier series, where n a is the nth Fourier coefficient. The derivation formula of the input impedance is given in [9]; in this paper, the input impedance was changed to (9), twice the on-resistance of the doublebalanced mixer (DBM).
The value of the output impedance of the mixer core decreases because of a more cascaded MOS

FBB for Enhancing the Performance of the Mixer Core
As mentioned above, the on-resistance of the mixer core should be as small as possible, which means that a large-sized MOS is needed, leading to an increase in the parasitic capacitance. In SHM, its on-resistance is double that of the DBM, thus the size of the mixer core should be more sensitive than that of the DBM in terms of front end performance. The on-resistance of NMOS is equal to: V TH decreases and then R SW decreases. In this paper, the FBB voltage is used in the mixer core to reduce the on-resistance. As shown in Figure 8a, the on-resistance of MOS reduces when using the FBB voltage. For example, the blue line shows a 58% decrease in Rsw from 31 Ω to 20 Ω, with W = 50 µm and V DS = 0.15 V at V B = 0.6 V and 0 V. Figure 8b shows the output impedance of the SHM core; the small size of the MOS means that large output impedance is expected in the front end. Therefore, a small-sized mixer core with FBB is chosen in this paper, and a deep N-well process is needed. The authors of [22] stated that the deep N-well implantation MOS does not impact the DC, AC, RF and noise performance of the multi-fingered transistor, hence allowing model consistency with the standard-well multi-fingered transistor.
In this paper, the FBB voltage is used in the mixer core to reduce the on-resistance. As shown in Figure 8a, the on-resistance of MOS reduces when using the FBB voltage. For example, the blue line shows a 58% decrease in Rsw from 31 Ω to 20 Ω, with W = 50 μm and VDS = 0.15 V at VB = 0.6 V and 0 V. Figure 8b shows the output impedance of the SHM core; the small size of the MOS means that large output impedance is expected in the front end. Therefore, a small-sized mixer core with FBB is chosen in this paper, and a deep N-well process is needed. The authors of [22] stated that the deep N-well implantation MOS does not impact the DC, AC, RF and noise performance of the multifingered transistor, hence allowing model consistency with the standard-well multi-fingered transistor.
(a) (b) The process of simplification of the circuits is shown in [20], assuming that the load is a pure resistance RL. The circuit is illustrated in Figure 9a,b for the calculation of a Volterra core, where gsw is the conductance of the mixer core and iNL2 and iNL3 are the second and third nonlinear sources, respectively.  The process of simplification of the circuits is shown in [20], assuming that the load is a pure resistance R L . The circuit is illustrated in Figure 9a,b for the calculation of a Volterra core, where g sw is the conductance of the mixer core and i NL2 and i NL3 are the second and third nonlinear sources, respectively.
In this paper, the FBB voltage is used in the mixer core to reduce the on-resistance. As shown in Figure 8a, the on-resistance of MOS reduces when using the FBB voltage. For example, the blue line shows a 58% decrease in Rsw from 31 Ω to 20 Ω, with W = 50 μm and VDS = 0.15 V at VB = 0.6 V and 0 V. Figure 8b shows the output impedance of the SHM core; the small size of the MOS means that large output impedance is expected in the front end. Therefore, a small-sized mixer core with FBB is chosen in this paper, and a deep N-well process is needed. The authors of [22] stated that the deep N-well implantation MOS does not impact the DC, AC, RF and noise performance of the multifingered transistor, hence allowing model consistency with the standard-well multi-fingered transistor.
(a) (b) The process of simplification of the circuits is shown in [20], assuming that the load is a pure resistance RL. The circuit is illustrated in Figure 9a,b for the calculation of a Volterra core, where gsw is the conductance of the mixer core and iNL2 and iNL3 are the second and third nonlinear sources, respectively.  For nonlinearity analysis, the source and drain voltages can be expressed as a converging Volterra series of input current, as shown in Figure 9a,b. Thus, H 1 S = g sw + g L g sw g S + g sw g L + g S g L (15) H 1 D = 2 π g sw g sw g S + g sw g L + g S g L (16) where H n S and H n D are the nth-order Volterra kernels for the source and drain ports, respectively [20]. The nonlinear current source is a function of the first-order Volterra kernels [23], which is given by (17), ignoring the cross derivative.
The second-order Volterra kernels are [20]: (g sw g S +g sw g L +g S g L ) 4 g L (g L + g sw ) K 2g ms (g sw + g L ) 2 + K 2g md g 2 sw + K 2g md (g sw g S +g sw g L +g S g L ) 4 g S g sw K 2g ms (g sw + g L ) 2 + K 2g md g 2 sw (20) (g sw g S +g sw g L +g S g L ) 4 K 3g ms (g sw + g L ) 3 + K 3g md g 3 sw + K 2gms (g sw g S +g sw g L +g S g L ) 5 g L (g L + g sw ) K 2g ms (g sw + g L ) 2 + K 2g md g 2 sw + K 2g md (g sw g S +g sw g L +g S g L ) 5 g S g sw K 2g ms (g sw + g L ) 2 + K 2g md g 2 (g sw g S +g sw g L +g S g L ) 4 K 3g ms (g sw + g L ) 3 + K 3g md g 3 sw + K 2gms (g sw g S +g sw g L +g S g L ) 5 g L (g L + g sw ) K 2g ms (g sw + g L ) 2 + K 2g md g 2 sw + K 2g md (g sw g S +g sw g L +g S g L ) 5 g S g sw K 2g ms (g sw + g L ) 2 + K 2g md g 2 Typically, g S is much smaller than both g SW and g L ; hence, H S 3 is the main nonlinearity contribution and H 3 D may be ignored. Additionally, we can assume that: g sw g S + g sw g L + g S g L ≈ g sw g L The simplified expression for Equation (22) is given by: For the triode region, the drain current is equal to: Electronics 2020, 9, 1369 9 of 17 Taking into account the variation of the depletion layer along the channel, (25) can be rewritten in terms of the voltages v GB , v DB and v SB (Equation (26)) [23]: Figure 10 displays the simulation results of K 3g md /g sw and K 2g md /g sw . Increasing the V B leads to a decrease in both K 2g md /g sw and K 3g md /g sw , as well as an increase in g SW . Finally, from (30), a decrease in H 3 S as the V B increases can be obtained.
Electronics 2020, 9, x FOR PEER REVIEW 10 of 18     Figure 10. Simulation results of K 3g md /g sw and K 2g md /g sw . Figure 11 provides the simulation results of K 3g ms /g sw and K 2g ms /g sw , according to which we can observe that a small value of V S is beneficial for linearity.
R sw decreases when V B increases, which means that V RF also decreases, while it is equal to V S . Hence, FBB can improve the linearity of the proposed mixer core. According to the simulation, the MOS of the mixer core with a width of 30 µm has an optimized IIP3 value, as well as good voltage gain and NF performance, as shown in Figure 12a Figure 11 provides the simulation results of 3 / ms g s w K g and 2 / ms g s w K g , according to which we can observe that a small value of VS is beneficial for linearity.
sw R decreases when VB increases, which means that VRF also decreases, while it is equal to VS. Hence, FBB can improve the linearity of the proposed mixer core. According to the simulation, the MOS of the mixer core with a width of 30 μm has an optimized IIP3 value, as well as good voltage gain and Figure 11. Simulation results of K 3g ms /g sw and K 2g ms /g sw .

TIA and Quadrature LO Generation Design
The careful design of the TIA is very important to the noise performance and the linearity of the whole circuit. As mentioned in [24], the input impedance of the TIA is "low enough" (Zin_TIA < Rsw), which provides a very high IIP3. The TIA is always composed of an operational amplifier (op-amp) with a parallel resistor and capacitance for feedback. The TIA gain is, assuming The simulation results of the input impedance of the TIA are shown in Figure 13b. The TIA achieved a DC trans-impedance gain of 1 kΩ (Rf = 1 kΩ) and a bandwidth of 20 MHz. The TIA op-amp had a low-frequency gain, an Avo of 1000 v/v, and a gain-bandwidth product (GBW) of 1 GHz. When increasing the GBW, the input impedance of TIA remained quite low at a high frequency, which is good for linearity but results in more power consumption. From (32) and Figure 13b, we can observe that gain and linearity are conflicting targets.

TIA and Quadrature LO Generation Design
The careful design of the TIA is very important to the noise performance and the linearity of the whole circuit. As mentioned in [24], the input impedance of the TIA is "low enough" (Z in_TIA < R sw ), which provides a very high IIP3. The TIA is always composed of an operational amplifier (op-amp) with a parallel resistor and capacitance for feedback. The TIA gain is, assuming A v ( jω) >> 1: The simulation results of the input impedance of the TIA are shown in Figure 13b. The TIA achieved a DC trans-impedance gain of 1 kΩ (R f = 1 kΩ) and a bandwidth of 20 MHz. The TIA op-amp had a low-frequency gain, an A vo of 1000 v/v, and a gain-bandwidth product (GBW) of 1 GHz. When increasing the GBW, the input impedance of TIA remained quite low at a high frequency, which is good for linearity but results in more power consumption. From (32) and Figure 13b, we can observe that gain and linearity are conflicting targets. achieved a DC trans-impedance gain of 1 kΩ (Rf = 1 kΩ) and a bandwidth of 20 MHz. The TIA op-amp had a low-frequency gain, an Avo of 1000 v/v, and a gain-bandwidth product (GBW) of 1 GHz. When increasing the GBW, the input impedance of TIA remained quite low at a high frequency, which is good for linearity but results in more power consumption. From (32) and Figure 13b, we can observe that gain and linearity are conflicting targets.  Because of the finite output impedance of the mixer, the total output noise would be given by: By substituting Equation (10) into Equation (32), we can get: The feedback resistors in the TIA and mixer core should be as small as possible for noise considerations. In this paper, the core of the TIA is a fully differential operational transconductance amplifier (OTA), as shown in Figure 14. The OTA comprises a PMOS input stage and an NMOS load. A common-mode feedback (CMFB) circuit is also adopted to maintain a common-mode voltage of 0.3 V. A PMOS input stage is chosen for a lower noise contribution than that of an NMOS one. The common-mode feedback circuit comprises a common-mode sensing stage, along with an operational amplifier to generate the common-mode bias. The value of the common-mode sensing resistor is chosen to be 1 MΩ. The CMFB op-amp is a single-stage op-amp, consisting of a PMOS input stage and an NMOS current mirror active load. All devices work in saturation mode.
Electronics 2020, 9, x FOR PEER REVIEW 12 of 18 Because of the finite output impedance of the mixer, the total output noise would be given by: By substituting Equation (10) into Equation (32), we can get: The feedback resistors in the TIA and mixer core should be as small as possible for noise considerations. In this paper, the core of the TIA is a fully differential operational transconductance amplifier (OTA), as shown in Figure 14. The OTA comprises a PMOS input stage and an NMOS load. A common-mode feedback (CMFB) circuit is also adopted to maintain a common-mode voltage of 0.3 V. A PMOS input stage is chosen for a lower noise contribution than that of an NMOS one. The common-mode feedback circuit comprises a common-mode sensing stage, along with an operational amplifier to generate the common-mode bias. The value of the common-mode sensing resistor is chosen to be 1 MΩ. The CMFB op-amp is a single-stage op-amp, consisting of a PMOS input stage and an NMOS current mirror active load. All devices work in saturation mode. The quadrature LO is generated by a poly-phase filter, as illustrated in Figure 15a. The quadrature LO is generated by a poly-phase filter, as illustrated in Figure 15a. The quadrature LO is generated by a poly-phase filter, as illustrated in Figure 15a.  One branch of the output signal can be derived with the superposition principle: The output signals of the other three branches are obtained using the same method, thus they can be depicted in a matrix notation: There are two kinds of input connections in PPF. For the first one (Figure 15b), according to (35), the output voltage ratio of I and Q is: Then, the output signals have the same magnitude at ω = 1/RC, and the phase difference between I and Q outputs is 90 • at all frequencies and with all R and C values in (37). For the second one (Figure 15c), the output voltage ratio of I and Q is: The output signals have the same magnitude at all frequencies and with all R and C values in (38). The ratio of the load-to-signal impedances of PPF should be large, which is an effective way to decrease the voltage loss [25]. Meanwhile, the same values of C in the first and second stages and the value of R in the second stage triple that in the first stage are chosen to decrease voltage loss. A square LO signal is good to ensure the performance of the mixing core, thus an LO buffer and driver, comprising an inverter with feedback (linear amplifier) and a series of inverters, is designed. In consideration of power consumption, the driver is biased on subthreshold voltage. The inverter design is based on the standard F04 inverter sizing, meaning that the sizing of each inverter stage progressively increases by a ratio of 3. Figure 16b shows the simulated results of the quadrature LO signal.
comprising an inverter with feedback (linear amplifier) and a series of inverters, is designed. In consideration of power consumption, the driver is biased on subthreshold voltage. The inverter design is based on the standard F04 inverter sizing, meaning that the sizing of each inverter stage progressively increases by a ratio of 3. Figure 16b shows the simulated results of the quadrature LO signal.

Measured Results and Discussion
The chip was designed and fabricated in a 0.13-µm CMOS process. The chip's microphotograph is shown in Figure 17, with an area of 650 µm × 1070 µm. Two off-chip baluns, of the 1720BL15A0100 (Johanson Technology Inc., Camarillo, CA, USA) types and with a 1.5-dB insertion loss from 625 MHz to 2800 MHz, were used to obtain differential LO and RF inputs. The power supply V DD and the LO input frequency were set to 1.2 V and 1.2 GHz, respectively, while the down-converted IF frequency was fixed at 1 MHz for the measurements. Figure 17 shows that the measured S11 parameter was −15 dB, which means that the RF port was well matched to 50 Ω.

Measured Results and Discussion
The chip was designed and fabricated in a 0.13-μm CMOS process. The chip's microphotograph is shown in Figure 17, with an area of 650 μm × 1070 μm. Two off-chip baluns, of the 1720BL15A0100 (Johanson Technology Inc.) types and with a 1.5-dB insertion loss from 625 MHz to 2800 MHz, were used to obtain differential LO and RF inputs. The power supply VDD and the LO input frequency were set to 1.2 V and 1.2 GHz, respectively, while the down-converted IF frequency was fixed at 1 MHz for the measurements. Figure 17 shows that the measured S11 parameter was −15 dB, which means that the RF port was well matched to 50 Ω.  Figure 18 shows the measured conversion gain and the NF of the chip, sweeping LO from −8 dBm to 8 dBm at an IF frequency of 1 MHz. The voltage gain remained almost the same, but the NF obviously changed with the LO sweep. At 0 dBm LO, the NF was 6.8 dB, i.e., 3 dB higher than the simulation result. This is because of the process variation of the R and C values of a poly-phase filter, which introduced more phase noise than in the simulation.  Figure 18 shows the measured conversion gain and the NF of the chip, sweeping LO from −8 dBm to 8 dBm at an IF frequency of 1 MHz. The voltage gain remained almost the same, but the NF obviously changed with the LO sweep. At 0 dBm LO, the NF was 6.8 dB, i.e., 3 dB higher than the simulation result. This is because of the process variation of the R and C values of a poly-phase filter, which introduced more phase noise than in the simulation. Figure 18 shows the measured conversion gain and the NF of the chip, sweeping LO from −8 dBm to 8 dBm at an IF frequency of 1 MHz. The voltage gain remained almost the same, but the NF obviously changed with the LO sweep. At 0 dBm LO, the NF was 6.8 dB, i.e., 3 dB higher than the simulation result. This is because of the process variation of the R and C values of a poly-phase filter, which introduced more phase noise than in the simulation.  Figure 19 shows the measured IIP3 of −2 dBm; the two-tone signal was swept from −50 dBm to −20 dBm with a ±100 kHz spacing at a center frequency of 2.4 GHz and an unchanged LO. The measured results were slightly higher than those of the simulation. The FBB voltage achieved an optimum value that improved the linearity of the circuit. One reason might be that the FBB voltage was closer to the optimum value of the chip than the circuits simulation, and the large capacitance of the printed circuit board (PCB) test board-filtered high-frequency signal might be another reason.  Figure 19 shows the measured IIP3 of −2 dBm; the two-tone signal was swept from −50 dBm to −20 dBm with a ±100 kHz spacing at a center frequency of 2.4 GHz and an unchanged LO. The measured results were slightly higher than those of the simulation. The FBB voltage achieved an optimum value that improved the linearity of the circuit. One reason might be that the FBB voltage was closer to the optimum value of the chip than the circuits simulation, and the large capacitance of the printed circuit board (PCB) test board-filtered high-frequency signal might be another reason. The port isolation is illustrated in Figure 20. The proposed circuit exhibited notable LO-RF port isolation, and the LO-IF port isolation was even better. The 2LO-RF and IF port isolations were also good. Figure 20. The measured port-to-port isolation.
The time-varying DC offset measurement followed the same process as that mentioned in [26], quantified using the formula: The port isolation is illustrated in Figure 20. The proposed circuit exhibited notable LO-RF port isolation, and the LO-IF port isolation was even better. The 2LO-RF and IF port isolations were also good. The port isolation is illustrated in Figure 20. The proposed circuit exhibited notable LO-RF port isolation, and the LO-IF port isolation was even better. The 2LO-RF and IF port isolations were also good. The time-varying DC offset measurement followed the same process as that mentioned in [26], quantified using the formula: Figure 20. The measured port-to-port isolation.
The time-varying DC offset measurement followed the same process as that mentioned in [26], quantified using the formula: where R amp is a reflection factor at the LNA output port, and both G RF-BB and G LO-BB are the conversion gains of the mixer from the RF and LO signal frequency to the baseband, respectively. The measured DC offset was 0.8 mV with a 1.2 GHz LO at 0 dBm. Table 1 provides a summary of the performance of the chipset in comparison to other subharmonic mixers in the CMOS technology. In this table, we can observe that the proposed front end exhibits notable voltage gain, good IIP3 and acceptable NF performance. To evaluate the dynamic performance of the proposed mixer, a figure of merit (FOM) was adopted. The performance of the mixer was compared in terms of conversion gain, linearity, noise figure and power dissipation. However, in the prospect of low-cost subharmonic mixing implementation, the consumption of the chip area was taken into account in the FOM calculation. The LO-RF isolation was also incorporated for a fair comparison of the FOM with other reported works. The modified FOM of the subharmonic mixer can be expressed as [13]: where CG is the conversion gain in decibels, IIP3 is the input-referred third-order intercept point in decibel milliwatts, P iso is the LO-RF isolation in decibels, NF is the noise figure in decibels, P dc is the power consumption of the subharmonic mixer core in megawatts and Area is the consumption of the chip area for the subharmonic mixer core circuitry in square millimeters. Table 1 shows that the proposed subharmonic front end exhibited an FOM value of 78.1, which is the highest value compared to other reported works. However, the proposed work had a higher power consumption and a bigger chip area compared to the other works listed in Table 1, because the LNA became the most power-hungry component when the complementary DS method was introduced and occupied most of the chip area. The authors of [8] used a single-to-differential transformer connected to the transconductance stage of the following mixer core, which saved the chip area and power consumption. However, the complimentary DS method could not be used in a single-input LNA. When comparing the proposed circuits to those in [27], the voltage gain, NF and FOM were better than those of the latter, and the two works achieved nearly the same power dissipation when removing TIAs. When the bias body voltage was set to zero, the figure of merit of the proposed circuit decreased to 67.3, meaning that the FBB technology is suitable for enhancing the performance of the entire circuit.

Conclusions
In this paper, a 2.4 GHz front end with subharmonic mixer topology is proposed. The transconductance stage comprises an LNA with a novel complementary DS method for improving linearity. The mixer core is a passive SHM architecture, chosen because the offset of DC and the immunity of flicker noise are suitable for zero-IF. FBB technology is introduced to enhance the performance of the mixer core. To the best of the authors' knowledge, this is the first time that FBB technology has been adopted in SHPM for performance enhancement and the first time that a Volterra series has been introduced to provide an analytical formula for the FBB of a SHPM core. The measured results show that this process achieves good voltage gain and IIP3, with moderate NF and the highest figure of merit compared to state-of-the-art publications.