Search Results (20)

Amorphous indium gallium zinc oxide (a-IGZO) is widely used as an oxide semiconductor in the electronics industry due to its low leakage current and high field-effect mobility. However, a-IGZO suffers from notable limitations, including crystallization at temperatures above 600 °C and the high cost of indium. To address these issues, nitrogen-doped zinc oxynitride (ZnON), which can be processed at room temperature, has been proposed. Nitrogen in ZnON effectively reduces oxygen vacancies (V_O), resulting in enhanced field-effect mobility and improved stability under positive bias stress (PBS) compared to IGZO. In this study, selective deep ultraviolet femtosecond (DUV fs) laser annealing was applied to the channel region of ZnON thin-film transistors (TFTs), enabling rapid threshold voltage (Vth) modulation within microseconds, without the need for vacuum processing. Based on the electrical characteristics of both Vth-modulated and pristine ZnON TFTs, an NMOS inverter was fabricated, demonstrating reliable performance. These results suggest that laser annealing is a promising technique, applicable to various logic circuits and electronic devices. Full article

Dual-gate metal-oxide-semiconductor transistors have attracted considerable interest due to their high threshold voltage control capability, higher drain current, and the ability to alleviate the impact of carrier surface scattering at the channel/dielectric interface. However, their applications in the monolithic integration of scaled devices encounter challenges stemming from the interaction between the pre-treated channel layer and its covering dielectric. Here, we demonstrate the successful realization of a scaled back-end-of-line (BEOL) compatible dual-gate indium–gallium–zinc oxide (IGZO) transistor with a channel length (L_ch) scaled down to 150 nm and a channel thickness (T_ch) of 4.2 nm. After precisely adjusting the metal ratio to In_0.24Ga_0.58Zn_0.18O and employing O₃ as an oxygen precursor for the deposition of Al₂O₃ as the top-gate dielectric layer, a high maximum current of 1.384 mA was attained under top-gate control, while a high current of 1.956 mA was achieved under bottom-gate control. Additionally, a high current on/off ratio (I_on/off > 10⁹) was achieved for the dual gate. Careful calculations reveal that the field-effective mobility (μ_eff) reaches 11.68 cm²V⁻¹s⁻¹ under top-gate control and 22.46 cm²V⁻¹s⁻¹ under bottom-gate control. We demonstrate excellent dual-gate low-voltage modulation performance, with a high current switch ratio of 3 × 10⁵ at L_ch = 300 nm and 2 × 10⁴ at L_ch = 150 nm achieved by only 1 V modulation voltage, accompanied by a normalized current variation higher than 10⁶. Overall, our devices show the remarkable electrical performance characteristics, highlighting their potential applications in high-performance electronic circuits. Full article

Molecular beam epitaxy (MBE) is demonstrated as an excellent growth technique for growing a low-defect GaN channel layer, which is crucial for controlling vertical leakage current and improving breakdown voltage (BV) in GaN-based high-electron mobility transistors (HEMTs). The 3D islands to 2D growth mode transition approach was induced by modulating substrate growth temperature (Tsub), displaying an overall improvement in film quality. A comprehensive investigation was conducted into the effects of Tsub on surface morphologies, crystal quality, and the optical and electrical properties of GaN films. Optimal results were achieved with a strain-relaxed GaN film grown at 690 °C, exhibiting significantly improved surface characteristics (root-mean-square roughness, Rq = 0.3 nm) and impressively reduced edge dislocations. However, the film with the smoothest surface roughness, attributed to the effect of the Ga-rich condition, possessed a high surface pit density, negatively affecting optical and electrical properties. A reduction in defect-related yellow emission further confirmed the enhanced crystalline quality of MBE GaN films. The optimized GaN film demonstrated outstanding electrical properties with a BV of ~1450 V, surpassing that of MOCVD GaN (~1180 V). This research significantly contributes to the advancement of MBE GaN-based high electron mobility transistor (HEMT) applications by ensuring outstanding reliability. Full article

In this study, the electrical characteristics of depletion-mode AlGaN/GaN high-electron-mobility transistors (HEMTs) with a SiN_x gate dielectric were tested under hydrogen exposure conditions. The experimental results are as follows: (1) After hydrogen treatment at room temperature, the threshold voltage V_TH of the original device was positively shifted from −16.98 V to −11.53 V, and the positive bias of threshold was 5.45 V. When the V_DS was swept from 0 to 1 V with V_GS of 0 V, the I_DS was reduced by 25% from 9.45 A to 7.08 A. (2) Another group of original devices with identical electrical performance, after the same duration of hydrogen treatment at 100 °C, exhibited a reverse shift in threshold voltage with a negative threshold shift of −0.91 V. The output characteristics were enhanced, and the saturation leakage current was increased. (3) The C-V method and the low-frequency noise method were used to investigate the effect of hydrogen effect on the device interface trap and border trap, respectively. It was found that high-temperature hydrogen conditions can passivate the interface/border traps of SiN_x/AlGaN, reducing the density of interface/border traps and mitigating the trap capture effect. However, in the room-temperature hydrogen experiment, the concentration of interface/border traps increased. The research findings in this paper provide valuable references for the design and application of depletion-mode AlGaN/GaN HEMT devices. Full article

Gallium nitride high-electron-mobility transistor (GaN HEMT) power devices are favored in various scenarios due to their high-power density and efficiency. However, with the significant increase in the heat flux density, the junction temperature of GaN HEMT has become a crucial factor in device reliability. Since the junction temperature monitoring technology for GaN HEMT based on temperature-sensitive electrical parameters (TSEPs) is still in the exploratory stage, the TSEPs’ characteristics of GaN HEMT have not been definitively established. In this paper, for the common steady-state TSEPs of GaN HEMT, the variation rules of the saturation voltage with low current injection, threshold voltage, and body-like diode voltage drop with temperature are investigated. The influences on the three TSEPs’ characteristics are considered, and their stability is discussed. Through experimental comparison, it is found that the saturation voltage with low current injection retains favorable temperature-sensitive characteristics, which has potential application value in junction temperature measurement. However, the threshold voltage as a TSEP for certain GaN HEMT is not ideal in terms of linearity and stability. Full article

Wide-bandgap gallium nitride (GaN)-based semiconductors offer significant advantages over traditional Si-based semiconductors in terms of high-power and high-frequency operations. As it has superior properties, such as high operating temperatures, high-frequency operation, high breakdown electric field, and enhanced radiation resistance, GaN is applied in various fields, such as power electronic devices, renewable energy systems, light-emitting diodes, and radio frequency (RF) electronic devices. For example, GaN-based high-electron-mobility transistors (HEMTs) are used widely in various applications, such as 5G cellular networks, satellite communication, and radar systems. When a current flows through the transistor channels during operation, the self-heating effect (SHE) deriving from joule heat generation causes a significant increase in the temperature. Increases in the channel temperature reduce the carrier mobility and cause a shift in the threshold voltage, resulting in significant performance degradation. Moreover, temperature increases cause substantial lifetime reductions. Accordingly, GaN-based HEMTs are operated at a low power, although they have demonstrated high RF output power potential. The SHE is expected to be even more important in future advanced technology designs, such as gate-all-around field-effect transistor (GAAFET) and three-dimensional (3D) IC architectures. Materials with high thermal conductivities, such as silicon carbide (SiC) and diamond, are good candidates as substrates for heat dissipation in GaN-based semiconductors. However, the thermal boundary resistance (TBR) of the GaN/substrate interface is a bottleneck for heat dissipation. This bottleneck should be reduced optimally to enable full employment of the high thermal conductivity of the substrates. Here, we comprehensively review the experimental and simulation studies that report TBRs in GaN-on-SiC and GaN-on-diamond devices. The effects of the growth methods, growth conditions, integration methods, and interlayer structures on the TBR are summarized. This study provides guidelines for decreasing the TBR for thermal management in the design and implementation of GaN-based semiconductor devices. Full article

Low-voltage Zn-doped CuI thin film transistors (TFTs) gated by chitosan dielectric were fabricated at a low temperature. The Zn-doped CuI TFT exhibited a more superior on/off current ratio than CuI TFT due to the substitution or supplementation of copper vacancies by Zn ions. The Zn-doped CuI films were characterized by scanning electron microscope, X-ray diffraction, and X-ray photoelectron spectroscopy. The Zn-doped CuI TFTs exhibited an on/off current ratio of 1.58 × 10⁴, a subthreshold swing of 70 mV/decade, and a field effect mobility of 0.40 cm²V⁻¹s⁻¹, demonstrating good operational stability. Due to the electric-double-layer (EDL) effect and high specific capacitance (17.3 μF/cm²) of chitosan gate dielectric, Zn-doped CuI TFT operates at a voltage below −2 V. The threshold voltage is −0.2 V. In particular, we have prepared Zn-doped CuI TFTs with two in-plane gates and NOR logic operation is implemented on such TFTs. In addition, using the ion relaxation effect and EDL effect of chitosan film, a simple pain neuron simulation is realized on such a p-type TFTs for the first time through the bottom gate to regulate the carrier transport of the channel. This p-type device has promising applications in low-cost electronic devices, complementary electronic circuit, and biosensors. Full article

A comprehensive model for micro-powered piezoelectric generator (PG), analysis of operation, and control of voltage doubler joule thief (VDJT) circuit to find the piezoelectric devices (PD’s) optimum functioning points are discussed in the present article. The proposed model demonstrates the power dependence of the PG on mechanical excitation, frequency, and acceleration, as well as outlines the load behaviour for optimal operation. The proposed VDJT circuit integrates the combination of voltage doubler (VD) and joule thief circuit, whereas the VD circuit works in Stage 1 for AC (alternating current)–DC (direct current) conversion, while a joule thief circuit works in Stage 2 for DC–DC conversion. The proposed circuit functions as an efficient power converter, which converts power from AC–DC and boosts the voltage from low to high without employing any additional electronic components and generating duty cycles. The electrical nature of the input (i.e., PD) of a VDJT circuit is in perfect arrangement with the investigated optimisation needs when using the proposed control circuit. The effectiveness of the proposed VDJT circuit is examined in terms of both simulation and experiment, and the results are presented. The proposed circuit’s performance was validated with available results of power electronics interfaces in the literature. The proposed circuit’s flexibility and controllability can be used for various applications, including mobile battery charging and power harvesting. Full article

The electrical and physical properties of the SiC/SiO₂ interfaces are critical for the reliability and performance of SiC-based MOSFETs. Optimizing the oxidation and post-oxidation processes is the most promising method of improving oxide quality, channel mobility, and thus the series resistance of the MOSFET. In this work, we analyze the effects of the POCl₃ annealing and NO annealing processes on the electrical properties of metal–oxide–semiconductor (MOS) devices formed on 4H-SiC (0001). It is shown that combined annealing processes can result in both low interface trap density (D_it), which is crucial for oxide application in SiC power electronics, and high dielectric breakdown voltage comparable with those obtained via thermal oxidation in pure O₂. Comparative results of non-annealed, NO-annealed, and POCl₃-annealed oxide–semiconductor structures are shown. POCl₃ annealing reduces the interface state density more effectively than the well-established NO annealing processes. The result of 2 × 10¹¹ cm⁻² for the interface trap density was attained for a sequence of the two-step annealing process in POCl₃ and next in NO atmospheres. The obtained values D_it are comparable to the best results for the SiO₂/4H-SiC structures recognized in the literature, while the dielectric critical field was measured at a level ≥9 MVcm⁻¹ with low leakage currents at high fields. Dielectrics, which were developed in this study, have been used to fabricate the 4H-SiC MOSFET transistors successfully. Full article

Along with the technology boom regarding electric vehicles such as lithium-ion batteries, electric motors, and plug-in charging systems, inductive power transfer (IPT) systems have gained more attention from academia and industry in recent years. This article presents a review of the state-of-the-art development of IPT systems, with a focus on low-voltage and high-current electric mobility applications. The fundamental theory, compensation topologies, magnetic coupling structures, power electronic architectures, and control methods are discussed and further considered in terms of several aspects, including efficiency, coil misalignments, and output regulation capability. A 3D finite element software (Ansys Maxwell) is used to validate the magnetic coupler performance. In addition, a 2.5 kW 400/48 V IPT system is proposed to address the challenges of low-voltage and high-current wireless charging systems. In this design, an asymmetrical double-sided LCC compensation topology and a passive current balancing method are proposed to provide excellent current sharing capability in the dual-receiver structures under both resonant component mismatch and misalignment conditions. Finally, the performance of the proposed method is verified by MATLAB/PSIM simulation results. Full article

Electric vehicles (EVs) are expected to take over the transportation and mobility market over traditional internal combustion engine (ICE) vehicles soon. The internal power demands of EVs are expected to increase. The reason for this is to achieve a longer driving range for the EV and to provide the required power for the low-voltage (LV) network auxiliary loads. To illustrate, there are extra added sensors, cameras, and small actuating motors, especially for future autonomous vehicles. Therefore, a new electrical/electronic (E/E) architecture is required to convert the high-voltage (HV) traction battery voltage (e.g., 320–800 V DC) to the standard LV levels with high current ratings of 5 kW and more. This HV-LV DC-DC converter is known in the literature as an auxiliary power module (APM). The standard LV rails in an EV are the 12 V/24 V rail to supply for an instant the EV’s lighting and electronic control units (ECUs), while the 48 V rail is required for propulsive loads, such as air compressors and electric power steering systems. Furthermore, in a few applications, this converter is responsible for voltage upwards to support the start of a hybrid vehicle or emergency backup power handling, which requires bidirectional capability. Therefore, in this paper, possible APM topologies for EV applications are presented. In line with this, the main standards and safety requirements of the APMs are presented. Detailed quantitative and qualitative comparisons between topologies and their associated control schemes are discussed. In addition, the placement of the APM in the EV cooling cycle has been investigated and demonstrated. Finally, the industrial trends and future research targets for the APM in automotive applications are outlined. Full article

Amorphous InGaZnO (a-InGaZnO) is currently the most prominent oxide semiconductor complement to low-temperature polysilicon for thin-film transistor (TFT) applications in next-generation displays. However, balancing the transmission performance and low-temperature deposition is the primary obstacle in the application of a-InGaZnO TFTs in the field of ultra-high resolution optoelectronic display. Here, we report that a-InGaZnO:O TFT prepared at room temperature has high transport performance, manipulating oxygen vacancy (V_O) defects through an oxygen-doped a-InGaZnO framework. The main electrical properties of a-InGaZnO:O TFTs included high field-effect mobility (µ_FE) of 28 cm²/V s, a threshold voltage (V_th) of 0.9 V, a subthreshold swing (SS) of 0.9 V/dec, and a current switching ratio (I_on/I_off) of 10⁷; significant improvements over a-InGaZnO TFTs without oxygen plasma. A possible reason for this is that appropriate oxygen plasma treatment and room temperature preparation technology jointly play a role in improving the electrical performance of a-InGaZnO TFTs, which could not only increase carrier concentration, but also reduce the channel-layer surface defects and interface trap density of a-InGaZnO TFTs. These provides a powerful way to synergistically boost the transport performance of oxide TFTs fabricated at room temperature. Full article

Compared with conventional silicon-based semiconductors, amorphous oxide semiconductors present several advantages, including the possibility of room-temperature fabrication, excellent uniformity, high transmittance, and high electron mobility. Notably, the application of oxide semiconductors to flexible electronic devices requires a low-temperature fabrication process. However, for the realization of semiconductor characteristics and stable products, the fabrication process requires annealing at temperatures of 300 °C or higher. To address this, a low-temperature microwave annealing method, which improves the electrical characteristics of a transistor and reduces the production time compared with the conventional annealing method, is presented herein. Microwave annealing is a well-known method of annealing that minimizes the heat energy transferred to a substrate via instantaneous heat transfer through the vibrations of the lattice in the material during microwave irradiation and is suitable as a low-temperature annealing method. In this study, we evaluate the electrical characteristics of devices subjected to conventional annealing at 200 °C and 300 °C for 1 h and microwave annealing at 200 °C for 10 min. For the device subjected to microwave annealing at 200 °C for 10 min, the threshold voltage, current on/off ratio, subthreshold swing, and saturation mobility are 13.9 V, 1.14 × 10⁵, 3.05 V/dec, and 4.23 cm²/V$·$s, respectively. These characteristic results are far superior to the characteristic results of the device subjected to conventional annealing at 200 °C for 1 h and are equivalent to those of the device treated at 300 °C for 1 h. Thus, this study develops a more effective annealing method, which facilitates low-temperature fabrication in a reduced period. Full article

Several studies on amorphous oxide semiconductor thin-film transistors (TFTs) applicable to next-generation display devices have been conducted. To improve the poor switching characteristics and gate bias stability of co-sputtered aluminum–indium–zinc oxide (AIZO) TFTs, we fabricate Al₂O₃/indium–zinc oxide (IZO) dual-active-layer TFTs. By varying the Al₂O₃ target power and oxygen partial pressure in the chamber during Al₂O₃ back-channel deposition, we optimize the electrical characteristics and gate bias stability of the Al₂O₃/IZO TFTs. The Al₂O₃/IZO TFTs, which are fabricated under 50 W Al₂O₃ target power and 13% oxygen partial pressure conditions, exhibit a high electron mobility of 23.34 cm²/V·s, a low threshold voltage of 0.96 V, an improved on–off current ratio of 6.8 × 10⁷, and a subthreshold swing of 0.61 V/dec. Moreover, by increasing the oxygen partial pressure in the chamber, the positive and negative bias stress values improve to +0.32 V and −2.08 V, respectively. X-ray photoelectron spectroscopy is performed to reveal the cause of these improvements. Full article

The wider bandgap AlGaN (Eg > 3.4 eV) channel-based high electron mobility transistors (HEMTs) are more effective for high voltage operation. High critical electric field and high saturation velocity are the major advantages of AlGaN channel HEMTs, which push the power electronics to a greater operating regime. In this article, we present the DC characteristics of 0.8 µm gate length (L_G) and 1 µm gate-drain distance (L_GD) AlGaN channel-based high electron mobility transistors (HEMTs) on ultra-wide bandgap β-Ga₂O₃ Substrate. The β-Ga₂O₃ substrate is cost-effective, available in large wafer size and has low lattice mismatch (0 to 2.4%) with AlGaN alloys compared to conventional SiC and Si substrates. A physics-based numerical simulation was performed to investigate the DC characteristics of the HEMTs. The proposed HEMT exhibits sheet charge density (n_s) of 1.05 × 10¹³ cm⁻², a peak on-state drain current (I_DS) of 1.35 A/mm, DC transconductance (g_m) of 277 mS/mm. The ultra-wide bandgap AlGaN channel HEMT on β-Ga₂O₃ substrate with conventional rectangular gate structure showed 244 V off-state breakdown voltage (V_BR) and field plate gate device showed 350 V. The AlGaN channel HEMTs on β-Ga₂O₃ substrate showed an excellent performance in I_ON/I_OFF and V_BR. The high performance of the proposed HEMTs on β-Ga₂O₃ substrate is suitable for future portable power converters, automotive, and avionics applications. Full article