Search Results (58)

Stochastic geometry provides a powerful analytical framework for evaluating interference-limited cellular networks with randomly deployed base stations (BSs). While prior studies have examined limited channel state information at the transmitter (CSIT) and low-resolution analog-to-digital converters (ADCs) separately, their joint impact in multi-user multiple-input multiple-output (MIMO) systems remains largely unexplored. This paper investigates a downlink cellular network in which BSs are distributed according to a homogeneous Poisson point process (PPP), employing zero-forcing beamforming (ZFBF) with limited feedback, and receivers are equipped with one-bit ADCs. We derive a tractable approximation for the achievable spectral efficiency that explicitly accounts for both the quantization error from limited feedback and the receiver distortion caused by coarse ADCs. Based on this approximation, we determine the optimal feedback rate that maximizes the net spectral efficiency. Our analysis reveals that the optimal number of feedback bits scales logarithmically with the channel coherence time but its absolute value decreases due to coarse quantization. Simulation results validate the accuracy of the proposed approximation and confirm the predicted scaling behavior, demonstrating its effectiveness for interference-limited multi-user MIMO networks. Full article

In view of the great need for quality assurance in radiotherapy, this paper proposes a stitching-based detector (SBD) technique and a set of intelligent algorithms that can reconstruct the information of projected particle beams. The reconstructed information includes the intensity, sigma value, and location of the maximum intensity of the beam under test. To verify the effectiveness of the proposed technique and algorithms, this research study adopts the pencil beam scanning (PBS) form of proton beam therapy (PBT) as an example. Through the SBD technique, it is possible to utilize 128 × 128 ionization chambers, which constitute an ionization plate of 25.6 cm², with an acceptable number of 4096 analog-to-digital converters (ADCs) and a resolution of 0.25 mm. Through simulation, the proposed SBD technique and intelligent algorithms are proven to exhibit satisfactory and practical performance. By using two kinds of maximum intensity definitions, sigma values ranging from 10 to 120, and two definitions in an erroneous case, the maximum error rate is found to be 3.95%, which is satisfactorily low. Through analysis, this research study discovers that most errors occur near the symmetrical and peripheral boundaries. Furthermore, lower sigma values tend to aggravate the error rate because the beam becomes more like an ideal particle, which leads to greater imprecision caused by symmetrical sensor structures as its sigma is reduced. However, because proton beams are normally not projected onto the border region of the sensed area, the error rate in practice can be expected to be even lower. Although this research study adopts PBS PBT as an example, the proposed SBD technique and intelligent algorithms are applicable to any type of particle beam reconstruction in the field of radiotherapy, as long as the particles under analysis follow a Gaussian distribution. Full article

This paper presents a microcontroller-based technique for accurately measuring resistive sensors over a wide dynamic range using an adaptive constant current source. Unlike conventional voltage dividers or fixed-current methods—often limited by reduced resolution and saturation when sensor resistance varies across several decades—the proposed system dynamically adjusts the excitation current to maintain optimal Analog-to-Digital Converter (ADC) input conditions. The measurement circuit employs a fixed reference resistor and an inverting amplifier configuration, where the excitation current is generated by one or more pulse-width modulated (PWM) signals filtered through low-pass RC networks. A microcontroller selects the appropriate PWM channel to ensure that the output voltage remains within the ADC’s linear range. To support multiple sensors, an analog switch enables sequential measurements using the same dual-PWM current source. The full experimental implementation uses four op-amps to support modularity, buffering, and dual-range operation. Experimental results show accurate measurement of resistances from 1 kΩ to 100 kΩ, with maximum relative errors of 0.15% in the 1–10 kΩ range and 0.33% in the 10–100 kΩ range. The method provides a low-cost, scalable, and digitally controlled solution suitable for embedded resistive sensing applications without the need for high-resolution ADCs or programmable gain amplifiers. Full article

The use of low-resolution analog-to-digital converters (ADCs) in receivers has emerged as an effective solution for reducing power consumption in millimeter-wave (mmWave) massive multiple-input–multiple-output (MIMO) systems. However, low-resolution ADCs also pose significant challenges for channel estimation. To address this issue, we propose a joint uplink/downlink (UL/DL) channel estimation algorithm that utilizes the spatial reciprocity of frequency division duplex (FDD) to improve the estimation of quantized UL channels. Quantified UL/DL channels are concentrated at the BS for joint estimation. This estimation problem is regarded as a compressed sensing problem with finite bits, which has led to the development of expectation-maximization-based quantitative generalized approximate messaging (EM-QGAMP) algorithms. In the expected step, QGAMP is used for posterior estimation of sparse channel coefficients, and the block maximization minimization (MM) algorithm is introduced in the maximization step to improve the estimation accuracy. Finally, simulation results verified the robustness of the proposed EM-QGAMP algorithm, and the proposed algorithm’s NMSE (normalized mean squared error) outperforms traditional methods by over 90% and recent state-of-the-art techniques by 30%. Full article

This manuscript introduces NeuroDetect, a model-free deep learning-based signal detection framework tailored for phase-modulated wireless systems with low-resolution analog-to-digital converters (ADCs). The proposed framework eliminates the need for explicit channel state information, which is typically difficult to acquire under coarse quantization. NeuroDetect utilizes a neural network architecture to learn the nonlinear relationship between quantized received signals and transmitted symbols directly from data. It achieves near-optimum performance, within a worst-case $12\%$ margin of the maximum likelihood detector that assumes perfect channel knowledge. We rigorously investigate the interplay between ADC resolution and detection accuracy, introducing novel penalty metrics that quantify the effects of both quantization and learning errors. Our results shed light on the design trade-offs between ADC resolution and detection accuracy, providing future directions for developing energy-efficient high-speed and wideband wireless systems. Full article

This paper presents a successive approximation register (SAR) and incremental sigma-delta modulator (ISDM) hybrid analog-to-digital converter (ADC) that operated at a minimum voltage supply of 0.575 V. A thorough analysis of the non-linearities caused by PVT variations and common-mode voltage (VCM) shifts in the ISDM stage is presented. The ADC employs an improved high-precision double-bootstrapped switch, and the synchronous clock is also double-bootstrapped to work under the low supply voltage. A modified merged capacitor switching (MCS) approach is presented to maintain a stable VCM at the differential input. The chip was fabricated using a 0.18 µm CMOS process, with a core area of 0.21 mm². It consumed only 0.42 µW at a 0.6 V supply and a sampling rate of 10 kS/s, which achieved an effective number of bits (ENOB) of 11.03. The resulting figure of merit (FOM_W) was 20.05 fJ/conversion-step, which is the lowest reported for ADCs of this architecture in a 0.18 µm process. Full article

This paper presents a successive approximation register analog-to-digital converter (SAR ADC) specifically optimized for brain–computer interface (BCI) applications. Designed and post-layout-simulated using 180 nm CMOS technology, the proposed SAR ADC achieves a 13.44-bit effective number of bits (ENOB) and 27.9 μW of power consumption at a supply voltage of 1.8 V, enabled by a piecewise monotonic switching scheme and dynamic logic architecture. The ADC supports a high input range of ±500 mV, making it suitable for neural signal acquisition. Through an optimized capacitive digital-to-analog converter (CDAC) array and a high-speed dynamic comparator, the ADC demonstrates a signal-to-noise-and-distortion ratio (SINAD) of 81.94 dB and a spurious-free dynamic range (SFDR) of 91.69 dBc at a sampling rate of 320 kS/s. Experimental results validate the design’s superior performance in terms of low-power operation, high resolution, and moderate sampling rate, positioning it as a competitive solution for high-density integration and precision neural signal processing in next-generation BCI systems. Full article

Based on Digital Beamforming (DBF) technology, spaceborne SAR systems can achieve high-resolution and wide-swath (HRWS) imaging. When combined with reflector antennas, the DBF-SCORE (Digital Beamforming-SCan On REceive) system also features light weight and low cost, making it an important choice for spaceborne HRWS SAR. This paper firstly proposes an advanced Full-chain Real-time Internal Calibration (FRIC) scheme, where the calibration path covers the entire receive chain from the antenna feed port to the input port of the Analog-to-Digital Converter (ADC) and achieves high-precision internal calibration concurrently with data acquisition. Secondly, based on the L-band reflector antenna DBF-SCORE system architecture, the design of radio frequency (RF) front end, namely the Transmit-Receive-Calibration Module (TRCM), is carried out. We propose the implementation of azimuth encoding modulation of the calibration signal through periodic switch control within the TRCM. Subsequently, the calibration signal is extracted using waveform diversity technology and its Signal-to-Noise Ratio (SNR) is improved through azimuth coherent integration technology. In addition, a ground verification system is established using the TRCM to evaluate the comprehensive performance of transmitting, receiving, and real-time internal calibration. Experimental results verify the effectiveness of the FRIC scheme and provide valuable insights for future spaceborne DBF SAR systems. Full article

Energy measurement in dynamic penetration tests is key to correctly interpreting test results and ensuring comparable geotechnical data. Although commercial devices are widely used, their high cost limits adoption in developing regions such as Peru, affecting the accuracy of soil evaluation in many geotechnical studies. In this context, this research presents an energy measurement system called Kallpa, which uses low-cost electronic components to digitize sensor signals during Standard Penetration Tests (SPTs). Kallpa employs high-resolution analog-to-digital converters (ADCs) with an advanced sampling frequency, processing and storing data via a Raspberry Pi 4 microcomputer. The sensors, including accelerometers and strain gauges, were calibrated and compared with the Pile Driving Analyzer (PDA) to validate their accuracy in the Kallpa system. This study involved sixteen Standard Penetration Tests (SPTs) conducted in various regions of Peru using donut hammers and two tests involving automatic hammers. The results demonstrate that the Kallpa system is comparable to other energy measurement devices on the market, such as the Dynamic Penetration Test (DPT), which provides accurate SPT energy measurements. The Kallpa Processor (Version 1.0) software was developed to perform data acquisition and calibration, analyzing approximately 500 hammer blows and comparing peak values with those of the Pile Driving Analyzer. The data collected by Kallpa’s sensors strongly agreed with the PDA data, validating the reliability of the device. The Energy Transfer Ratio (ETR) for manual hammers ranged from 43.5% to 68.4%, with an average of 58.9%, whereas automatic hammers presented ETR values between 82% and 87%. The correction of the N60 blow count allowed for the estimation of the relative density of soils evaluated at different depths and locations across Peru. Full article

In this study, we describe a low-noise complementary metal-oxide semiconductor (CMOS) image sensor (CIS) with a 10/11-bit hybrid single-slope analog-to-digital converter (SS-ADC). The proposed hybrid SS-ADC provides a resolution of 11 bits in low-light and 10 bits in high-light. To this end, in the low-light section, the digital-correlated double sampling method using a double data rate structure was used to obtain a noise performance similar to that of the 11-bit SS-ADC under low-light conditions, while maintaining linear in-out characteristics. The CIS with the proposed 10/11-bit hybrid SS-ADC was fabricated using a 110 nm 1-poly 4-metal CIS process. The measurement results showed that dark random noise was reduced by 8% in low light when using the proposed hybrid SS-ADC, compared with the existing 10-bit ADC. Additionally, in the case of high brightness, when using a 10-bit resolution, the dynamic power consumption decreased by approximately 31%, compared to the 11-bit ADC. The total power consumption is 3.9 mW at 15 fps when the analog, pixel, and digital supply voltages are 3.3 V, 3.3 V, and 1.5 V, respectively. Full article

Stochastic geometry has emerged as a powerful tool for modeling cellular networks, especially in dense deployment scenarios where inter-cell interference is significant. Previous studies have extensively analyzed multi-antenna systems with partial channel state information at the transmitter (CSIT) using stochastic geometry models. However, most of these works assume the use of infinite-resolution analog-to-digital converters (ADCs) at the receivers. Recent advances in low-resolution ADCs, such as one-bit ADCs, offer an energy-efficient alternative for millimeter-wave systems, but the interplay between limited feedback and one-bit ADCs remains underexplored in such networks. This paper addresses this gap by analyzing the optimal feedback rate that maximizes net spectral efficiency in dense cellular networks, modeled using stochastic geometry, with both limited feedback and one-bit ADC receivers. We introduce an approximation of the achievable spectral efficiency to derive a differentiable expression of the optimal feedback rate. The results show that while the scaling behavior of the optimal feedback rate with respect to the channel coherence time remains unaffected by the ADC’s resolution, the absolute values are significantly lower for one-bit ADCs compared to infinite-resolution ADCs. Simulation results confirm the accuracy of our theoretical approximations and demonstrate the impact of ADC resolution on feedback rate optimization. Full article

Battery-powered Internet-of-Things applications require high-resolution, energy-efficient analog-to-digital converters (ADCs). There are still limited works on sub-MHz-bandwidth ADC designs. This paper presents a sturdy multi-stage shaping (SMASH) discrete-time (DT) delta-sigma modulator (DSM) structure using a self-cascoded floating-inverter-based dynamic amplifier (FIA). The proposed structure removes the explicit quantization error extraction of the first loop and all the feedback DACs in the cascaded loop, decreasing the design complexity of the circuit. This enables the proposed DT DSM to operate at a higher speed, which is suitable for achieving high-order noise at a low oversampling ratio (OSR). The proposed self-cascoded FIA is more power-efficient and can acquire more than 45 dB DC gain under a 1.2 V supply. The DT DSM implemented in a piece of 55 nm CMOS technology measures an 88.0 dB peak signal-to-noise-and-distortion ratio (SNDR) in a 100 kHz bandwidth (BW) and an 85.3 dB dynamic range (DR), consuming 249.1 μW from a 1.2 V supply at 10 MS/s. The obtained 174.0 dB SNDR-based Schreier figure-of-merit (FoMs) is competitive within state-of-art high-resolution (SNDR > 85 dB) and general-purpose (sub-MHz-bandwidth) ΔΣ ADCs. Full article

Neural recording systems play a crucial role in comprehending the intricacies of the brain and advancing treatments for neurological disorders. Within these systems, the analog-to-digital converter (ADC) serves as a fundamental component, converting the electrical signals from the brain into digital data that can be further processed and analyzed by computing units. This research introduces a novel nonlinear ADC designed specifically for spike sorting in biomedical applications. Employing MOSFET varactors and voltage-controlled oscillators (VCOs), this ADC exploits the nonlinear capacitance properties of MOSFET varactors, achieving a parabolic quantization function that digitizes the noise with low resolution and the spikes with high resolution, effectively suppressing the background noise present in biomedical signals. This research aims to develop a reconfigurable, nonlinear voltage-controlled oscillator (VCO)-based ADC, specifically designed for implantable neural recording systems used in neuroprosthetics and brain–machine interfaces. The proposed design enhances the signal-to-noise ratio and reduces power consumption, making it more efficient for real-time neural data processing. By improving the performance and energy efficiency of these devices, the research contributes to the development of more reliable medical technologies for monitoring and treating neurological disorders. The quantization step of the ADC spans from 44.8 mV in the low-amplitude range to 1.4 mV in the high-amplitude range. The circuit was designed and simulated utilizing a 180 nm CMOS process; however, no physical prototype has been fabricated at this stage. Post-layout simulations confirm the expected performance. Occupying a silicon area is 0.09 mm². Operating at a sampling frequency of 16 kS/s and a supply voltage of 1 volt, this ADC consumes 62.4 µW. Full article

To establish ubiquitous and energy-efficient wireless sensor networks (WSNs), short-range Internet of Things (IoT) devices require Bluetooth low energy (BLE) technology, which functions at 2.4 GHz. This study presents a novel approach as follows: a fully integrated all-digital phase-locked loop (ADPLL)-based Gaussian frequency shift keying (GFSK) modulator incorporating two-point modulation (TPM). The modulator aims to enhance the efficiency of BLE communication in these networks. The design includes a time-to-digital converter (TDC) with the following three key features to improve linearity and time resolution: fast settling time, low dropout regulators (LDOs) that adapt to process, voltage, and temperature (PVT) variations, and interpolation assisted by an analog-to-digital converter (ADC). It features a digital controlled oscillator (DCO) with two key enhancements as follows: ΔΣ modulator dithering and hierarchical capacitive banks, which expand the frequency tuning range and improve linearity, and an integrated, fast-converging least-mean-square (LMS) algorithm for DCO gain calibration, which ensures compliance with BLE 5.0 stable modulation index (SMI) requirements. Implemented in a 28 nm CMOS process, occupying an active area of 0.33 mm², the modulator demonstrates a wide frequency tuning range of from 2.21 to 2.58 GHz, in-band phase noise of −102.1 dBc/Hz, and FSK error of 1.42% while consuming 1.6 mW. Full article

This paper proposes a heuristic association algorithm between access points (APs) and user equipment (UE) in user-centric cell-free massive multiple-input-multiple-output (MIMO) systems, specifically targeting scenarios where UEs share the same frequency and time resources. The proposed algorithm prevents overserving APs and ensures the connectivity of all UEs, even when the number of UEs is significantly greater than the number of APs. Additionally, we assume the use of low-resolution analog-to-digital converters (ADCs) to reduce fronthaul capacity. While realistic massive access scenarios, such as those in Internet-of-Things (IoT) environments, often involve hundreds or thousands of UEs per AP using multiple access techniques to allocate different frequency and time resources, our study focuses on scenarios where UEs within each AP cluster share the same frequency and time resources to highlight the impact of pilot contamination in dense network environments. The proposed algorithm is validated through simulations, confirming that it guarantees the connection of all UEs and prevents overserving APs. Furthermore, we analyze the required fronthaul capacity based on quantization bits and confirm that the proposed algorithm outperforms existing algorithms in terms of SE and average SE performance for UEs. Full article