Search Results (14)

This study systematically investigates the mechanism by which total ionizing dose (TID) affects the lifetime degradation of NMOS devices induced by hot-carrier injection (HCI). Experiments involved Cobalt-60 (Co-60) gamma-ray irradiation to a cumulative dose of 500 krad (Si), followed by 168 h annealing at 100 °C to simulate long-term stability. However, under HCI stress conditions (V_D = 2.7 V, V_G = 1.8 V), irradiated devices show a 6.93% increase in threshold voltage shift (ΔV_th) compared to non-irradiated counterparts. According to the IEC 62416 standard, the lifetime degradation of irradiated devices induced by HCI stress is only 65% of that of non-irradiated devices. Conversely, when the saturation drain current (I_Dsat) degrades by 10%, the lifetime doubles compared to non-irradiated counterparts. Mechanistic analysis demonstrates that partial neutralization of E’ center positive charges at the gate oxide interface by hot electrons weakens the electric field shielding effect, accelerating ΔV_th drift, while interface trap charges contribute minimally to degradation due to annealing-induced self-healing. The saturation drain current shift degradation primarily correlates with electron mobility variations. This work elucidates the multi-physics mechanisms through which TID impacts device reliability and provides critical insights for radiation-hardened design optimization. Full article

Despite the advantages of fin field-effect transistors (FinFETs), there are hidden issues such as electric field enhancement and exacerbated self-heating effects, which will intensify device aging effects. Due to the escalating costs associated with aging protection at the device process level, there is an urgent need to reduce the impact of aging on circuit performance from the circuit design perspective. This study focuses on the specific structure of the strong-arm latch comparator and conducts a detailed aging analysis. Based on the quasi-static approximation (QSA) model, the threshold voltage shift under operational stress is simulated. It is concluded that both the hot carrier injection (HCI) effect and negative bias temperature instability (NBTI) effect play equally non-negligible roles. Furthermore, aging tests were conducted based on 14 nm FinFET devices, validating the substantial HCI effects induced by short-duration pulses. Simultaneously, the test results suggest that the aging effect becomes more remarkable with increasing current. An improved circuit is proposed to reduce the HCI effect by reducing the current pulse by the way of pre-charging, which effectively reduces the threshold voltage shift of the latch comparator input transistors. Full article

The working environment of electronic devices in the aerospace field is harsh. In order to ensure the reliable application of the SOI FinFET, the total ionizing dose (TID) and hot carrier injecting (HCI) reliability of an SOI FinFET were investigated in this study. First, the influence of TID on the device was simulated. The results show that TID causes the threshold voltage to decrease and the off-state current and subthreshold swing to increase. TID causes more damage to the device at high temperature and also reduces the saturation drain current of the device. HCI causes the device threshold voltage to increase and the saturation drain current to decrease. The HCI is more severe at high temperatures. Finally, the coupling effects of the two were simulated, and the results show that the two effects cancel each other out, and the degradation of various electrical characteristic parameters is different under different coupling modes. Full article

In this work, we propose a SiC-NSFET structure that uses a PTS scheme only under the gate, with SiC layers under the source and drain, to improve the leakage current and thermal reliability. Punch-through stopper (PTS) doping is widely used to suppress the leakage current, but aggressively high PTS doping will cause additional band-to-band (BTBT) current. Therefore, the bottom oxide isolation nanosheet field-effect transistor (BOX-NSFET) can further reduce the leakage current and become an alternative to conventional structures with PTS. However, thermal reliability issues, like bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB), induced by the self-heating effect (SHE) of BOX-NSFET, become more profound due to the lower thermal conductivity of ${\mathrm{SiO}}_2$ than silicon. Moreover, the bottom oxide will reduce the stress along the channel due to the challenges associated with growing high-quality SiGe material on ${\mathrm{SiO}}_2$. Therefore, this method faces difficulties in enhancing the mobility of p-type devices. The comprehensive TCAD simulation results show that SiC-NSFET significantly suppresses the substrate leakage current compared to the conventional structure with PTS. In addition, compared to the BOX-NSFET, the stress reduction caused by the bottom oxide is avoided, and the SHE is mitigated. This work provides significant design guidelines for leakage and thermal reliability optimization of next-generation advanced nodes. Full article

The gate-all-around (GAA) nanosheet (NS) field-effect-transistor (FET) is poised to replace FinFET in the 3 nm CMOS technology node and beyond, marking the second seminal shift in device architecture across the extensive 60-plus-year history of MOSFET. The introduction of a new device structure, coupled with aggressive pitch scaling, can give rise to reliability challenges. In this article, we present a review of the key reliability mechanisms in GAA NS FET, including bias temperature instability (BTI), hot carrier injection (HCI), gate oxide (Gox) time-dependent dielectric breakdown (TDDB), and middle-of-line (MOL) TDDB. We aim to not only underscore the unique reliability attributes inherent to NS architecture but also provide a holistic view of the status and prospects of NS reliability, taking into account the challenges posed by future scaling. Full article

Many silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) are used in deep space detection systems because they have higher radiation resistance than bulk silicon devices. However, SOI devices have to face the double challenge of radiation and conventional reliability problems, such as hot carrier stress, at the same time. Thus, we wondered whether there is any interaction between reliability degradation and irradiation damage. In this paper, the effect of hot-carrier injection (HCI) on γ-ray-irradiated partially depleted (PD) SOI n-MOSFETs with a T-shaped gate structure is investigated. A strange phenomenon that accelerated the annealing effect on irradiation devices caused by HCI in 5 s was observed. That is, HCI has fast recovery ability on the irradiated narrow-channel n-MOSFETs. We explain the physical mechanism of this recovery effect qualitatively. Moreover, we designed a comparable experiment to evaluate the effect on the wide-channel devices. These results show that the narrow-channel devices are more sensitive to irradiation and HCI effects than wide-channel devices. Full article

In this work, the degradation of the random telegraph noise (RTN) and the threshold voltage ($V_t$) shift of an 8.3Mpixel stacked CMOS image sensor (CIS) under hot carrier injection (HCI) stress are investigated. We report for the first time the significant statistical differences between these two device aging phenomena. The $V_t$ shift is relatively uniform among all the devices and gradually evolves over time. By contrast, the RTN degradation is evidently abrupt and random in nature and only happens to a small percentage of devices. The generation of new RTN traps by HCI during times of stress is demonstrated both statistically and on the individual device level. An improved method is developed to identify RTN devices with degenerate amplitude histograms. Full article

The rapid progress of artificial neural networks (ANN) is largely attributed to the development of the rectified linear unit (ReLU) activation function. However, the implementation of software-based ANNs, such as convolutional neural networks (CNN), within the von Neumann architecture faces limitations due to its sequential processing mechanism. To overcome this challenge, research on hardware neuromorphic systems based on spiking neural networks (SNN) has gained significant interest. Artificial synapse, a crucial building block in these systems, has predominantly utilized resistive memory-based memristors. However, the two-terminal structure of memristors presents difficulties in processing feedback signals from the post-synaptic neuron, and without an additional rectifying device it is challenging to prevent sneak current paths. In this paper, we propose a four-terminal synaptic transistor with an asymmetric dual-gate structure as a solution to the limitations of two-terminal memristors. Similar to biological synapses, the proposed device multiplies the presynaptic input signal with stored synaptic weight information and transmits the result to the postsynaptic neuron. Weight modulation is explored through both hot carrier injection (HCI) and Fowler–Nordheim (FN) tunneling. Moreover, we investigate the incorporation of short-term memory properties by adopting polysilicon grain boundaries as temporary storage. It is anticipated that the devised synaptic devices, possessing both short-term and long-term memory characteristics, will enable the implementation of various novel ANN algorithms. Full article

Hot carrier injection (HCI) can generate interface traps or oxide traps mainly by dissociating the Si-H or Si-O bond, thus affecting device performances such as threshold voltage and saturation current. It is one of the most significant reliability issues for devices and circuits. Particularly, the increase in heat generation per unit volume due to high integration density of advanced integrated circuits leads to a severe self-heating effect (SHE) of nanoscale field effect transistors (FETs), and low thermal conductivity of materials in nanoscale FETs further aggravates the SHE. High temperature improves the HCI reliability in the conventional MOSFET with long channels in which the energy of carriers can be relaxed. However, high temperature due to severe SHE deteriorates HCI reliability in nanoscale FETs, which is a big concern in device and circuit design. In this paper, the modeling and simulation methods of HCI in FETs are reviewed. Particularly, some recently proposed HCI models with consideration of the SHE are reviewed and discussed in detail. Full article

As the device feature size shrinks, the dissipation of power increases and further raises the carrier and lattice temperature, which finally affects device performance. In this paper, we analyze the comprehensive influence of the self-heating effect and hot carrier injection (HCI) using TCAD simulations. Based on the hydrodynamic and thermodynamic models, it is demonstrated that the thermal surface resistance had a positive impact on the carrier and lattice temperature and that the drain saturation current is reduced dramatically due to the self-heating effect. Moreover, the impact of HCI on device performance is discussed. Finally, it is concluded that the self-heating effect exacerbates the influence of HCI on device characteristics. Full article

Device guidelines for reducing power with punch-through current annealing in gate-all-around (GAA) FETs were investigated based on three-dimensional (3D) simulations. We studied and compared how different geometric dimensions and materials of GAA FETs impact heat management when down-scaling. In order to maximize power efficiency during electro-thermal annealing (ETA), applying gate module engineering was more suitable than engineering the isolation or source drain modules. Full article

A gate all around with back-gate (GAAB) structure was proposed for 3D NAND Flash memory technology. We demonstrated the excellent characteristics of the GAAB NAND structure, especially in the self-boosting operation. Channel potential of GAAB shows a gradual slope compared with a conventional GAA NAND structure, which leads to excellent reliability characteristics in program disturbance, pass disturbance and oxide break down issue. As a result, the GAAB structure is expected to be appropriate for a high stacking structure of future memory structure. Full article

As semiconductor processes enter the nanoscale, system-on-chip (SoC) interconnects suffer from link aging owing to negative bias temperature instability (NBTI), hot carrier injection (HCI), and electromigration. In network-on-chip (NoC) for heterogeneous manycore systems, there is a difference in the aging speed of links depending on the location and utilization of resources. In this paper, we propose a heterogeneous manycore NoC topology synthesis that predicts the aging effect of each link and deploys routers and error correction code (ECC) logic. Aging-aware ECC logic is added to each link to achieve the same link lifetime with less area and latency than the Bose-Chaudhuri-Hocquenghem (BCH) logic. Moreover, based on the modified genetic algorithm, we search for a solution that minimizes the average latency while ensuring the link lifetime by changing the number of routers, location, and network connectivity. Simulation results demonstrate that the aging-aware topology synthesis reduces the average latency of the network by up to 26.68% compared with the aging analysis and the addition of ECC logic on the link after the topology synthesis. Furthermore, topology synthesis with aging-aware ECC logic reduces the maximum average latency by up to 39.49% compared with added BCH logic. Full article

With CMOS technology aggressively scaling towards the 22-nm node, modern FPGA devices face tremendous aging-induced reliability challenges due to bias temperature instability (BTI) and hot carrier injection (HCI). This paper presents a novel anti-aging technique at the logic level that is both scalable and applicable for VLSI digital circuits implemented with FPGA devices. The key idea is to prolong the lifetime of FPGA-mapped designs by strategically elevating the V_DD values of some LUTs based on their modular criticality values. Although the idea of scaling V_DD in order to improve either energy efficiency or circuit reliability has been explored extensively, our study distinguishes itself by approaching this challenge through an analytical procedure, therefore being able to maximize the overall reliability of the target FPGA design by rigorously modeling the BTI-induced device reliability and optimally solving the V_DD assignment problem. Specifically, we first develop a systematic framework to analytically model the reliability of an FPGA LUT (look-up table), which consists of both RAM memory bits and associated switching circuit. We also, for the first time, establish the relationship between signal transition density and a LUT’s reliability in an analytical way. This key observation further motivates us to define the modular criticality as the product of signal transition density and the logic observability of each LUT. Finally, we analytically prove, for the first time, that the optimal way to improve the overall reliability of a whole FPGA device is to fortify individual LUTs according to their modular criticality. To the best of our knowledge, this work is the first to draw such a conclusion. Full article