Hot Carrier Injection Reliability in Nanoscale Field Effect Transistors: Modeling and Simulation Methods

Abstract

Hot carrier injection (HCI) can generate interface traps or oxide traps mainly by dissociating the Si-H or Si-O bond, thus affecting device performances such as threshold voltage and saturation current. It is one of the most significant reliability issues for devices and circuits. Particularly, the increase in heat generation per unit volume due to high integration density of advanced integrated circuits leads to a severe self-heating effect (SHE) of nanoscale field effect transistors (FETs), and low thermal conductivity of materials in nanoscale FETs further aggravates the SHE. High temperature improves the HCI reliability in the conventional MOSFET with long channels in which the energy of carriers can be relaxed. However, high temperature due to severe SHE deteriorates HCI reliability in nanoscale FETs, which is a big concern in device and circuit design. In this paper, the modeling and simulation methods of HCI in FETs are reviewed. Particularly, some recently proposed HCI models with consideration of the SHE are reviewed and discussed in detail.

1. Introduction

Hot carrier injection (HCI) is a significant reliability issue for transistors in analog/RF circuits and logic circuits [1,2,3,4,5,6]. Considerable evidence show that hot carriers can dissociate the Si-H and Si-O bond through a single-carrier process or multiple-carrier process [7,8,9,10,11,12]. As a result, interface traps and oxide traps are generated [13], which leads to the degradation of transistor performance, such as threshold voltage shift ($\Delta V_{TH}$), mobility shift ($\Delta \mu$), linear current shift ($\Delta I_{LIN}$), saturation current shift ($\Delta I_{SAT}$) and transconductance shift ($\Delta G_m$) [2,14,15,16,17]. Furthermore, the degradation of transistor performance degrades the performance of the circuit. For example, it can increase the risetime in inverters [18]; increase the delay for large-scale digital circuits [19,20], which reduces the maximum frequency of the CPU; and it also causes the read disturbance of memory [21] and increases the probability of failure of the memory system [18,22].

Various models have been developed to reveal the physical mechanisms behind the phenomena, and models were also built to predict HCI induced device degradation. In 1985, Hu et al. developed the lucky electron model involving Si-H bond breakage and related HCI with the maximum electric field in the channel, based on which the $t^n$ time dependence of interface traps can be derived and the barrier energy for creating interface traps can also be extracted [7]. In 1995, the behavior of hot-carrier-induced degradation of deep-submicron n-Channel LDD MOSFETs was modeled analytically by introducing an empirical model of mobility degradation and series resistance [23]. In 2002, Mcmahon et al. proposed a model for interface trap generation through multiple vibrations of electrons: the model relates the device lifetime with the magnitude of source-drain current, and large source-drain current increases the probability of multiple vibrations of electrons and degrades the device faster [8]. In 2005, Rauch et al. proposed an energy-driven paradigm to describe hot carrier behavior in scaled NMOSFETs of that time, in which the available electron energy, instead of the peak lateral electric field in the lucky electron model, is the fundamental “driving force” for HCI [24]. In 2009, a theoretical framework for interface state creation by dissociation of Si-H bonds at the Si/SiO₂ interface was developed by Guerin et al. [9], which includes three main ways of bond breaking: the first one is due to the rising of energy levels because of strong quantum confinement caused by a large electrical field, the second one is due to very energetic incident carriers, the third one is due to numerous but less energetic carriers. In 2014, Bina et al. presented and verified a physics-based model of hot carrier degradation (HCD) based on a thorough solution of the Boltzmann transport equation [25], which is capable of representing HCD in transistors stressed under different conditions using a unique set of model parameters. In 2016, Chen et al. developed a numerical simulation method to capture HCI induced threshold voltage shift with consideration of time-dependent temperature in SOI MOSFETs [26] and FinFET [27], which is applicable to analyze HCI for transistors under stress voltage with different duty cycles, frequency and waveform. In 2017, Jiang et al. proposed an analytical model to capture the temperature of transistors in a digital circuit that is biased under pulse trains characterized by frequency and power duty cycle, then HCI performance is predicted [28]. Yu et al. proposed a trap-based compact model [29,30,31], which can accurately predict hot carrier degradation and variation in full V_gs/V_ds bias. In 2019, a SPICE compatible compact hot carrier degradation time kinetics model was proposed for conventional, lightly doped drain, and drain extended MOSFETs and FinFETs [32]. In 2022, Wang et al. introduced the artificial neural network (ANN) method into HCI reliability prediction and significantly reduced the HCI simulation cost [33].

In the conventional long-channel MOSFET, the worst case HCI condition is V_G = V_D/2 in which $I_{sub}$ reaches maximum [2]. The traps generated by HCI are located at drains corresponding to maximum lateral electric field [34]. The time evolution of degradation follows the power law. In short-channel MOSFET, the worst HCI condition is V_G = V_D [35]. The traps generated by HCI are closed to source and drain [36,37]. The time evolution of degradation follows the power law in the early time and becomes saturated at long time stress. In FinFET, two types of oxide traps and interface traps are generated [29]. The oxide traps generated in planar devices only have one type [29]. The difference can be explained in that FinFET has one more lattice orientation than the planar device [30]. The interface traps and oxide traps (type 1) are mainly located at the channel center closer to the source on the Fin sidewall, while the oxide traps (type 2) are mainly distributed at the channel center closer to the drain on the Fin top [30]. In gate-all-around (GAA) nanowire, HCI is dependent on its width [38,39]; the degradation mechanism is similar to that of the planar device but the self-heating effect becomes more severe and needs to be taken into account [40].

Moreover, HCI in nanoscale FET deteriorates as temperature increases [3,41,42,43], which is totally different from the conventional long-channel MOSFET [44,45,46,47,48]. One explanation is that the bond dissociation in nanoscale FET is more triggered by multi-vibration excitation (MVE) than single-vibration excitation (SVE) [49] and high temperature favors bond dissociation rate [42,50,51]. Another explanation is that the total HCI consists of two parts: classical channel hot carrier (CHC) at the drain side and bias temperature instability (BTI) along the channel [37,52]. As the temperature increases, the increase in BTI degradation is greater than the decrease in CHC degradation; consequently, the total degradation increases with temperature [52].

On the other hand, a more severe self-heating effect (SHE) in nanoscale transistors happens because of the increase in heat generation per unit volume caused by high integration density [53]. Furthermore, low thermal conductivity of the more confined thin films in silicon-on-insulator (SOI) MOSFET and FinFET leads to more severe SHEs [54,55,56,57]. As a result, the temperature in nanoscale transistors increases significantly [58,59,60,61]. Severe SHE further deteriorates HCI reliability for nanoscale transistors, which is a big concern in modern nanoscale transistors [3,41,42,50,62].

The review paper is organized as follows: In Section 2, we present and discuss some recently proposed modeling and simulation methods for HCI, including numerical methods [26,27,33], an analytical HCI model in digital circuit [3,28,63], trap-based HCI models [29,30,31] and an ANN model for HCI reliability [33]. In Section 3, a conclusion and outlook are given.

2. Modeling and Simulation Methods

2.1. HCI Simulation via Numerical Methods

In order to calculate the HCI-induced threshold voltage shift under stress voltages with different waveforms and frequencies, numerical simulation methods were developed for SOI MOSFETs and FinFETs [26,27,33]. The simulation process can be divided into three parts: (1) the current density can be obtained by numerically solving carrier transport equations, then the time dependent heat generation rate for the device under different stresses voltage can be obtained; (2) by using a numerical method to solve the time-dependent thermal conduction equation, the transient temperature responses can be obtained [26,27,33]; (3) HCI induced threshold voltage shift (TVS) as a function of time is then captured numerically based on the temperature response [26,27,33]. The numerical methods can simulate HCI under various stress voltages and operation conditions. However, the simulation cost is high, which makes it very time-consuming to calculate TVS for a long-time stress, and thus extrapolation is typically applied.

2.1.1. Electro-Thermal Numerical Simulation

The time-dependent temperature distribution is obtained by solving the heat conduction equation,

$$\rho (\overrightarrow{r})c(\overrightarrow{r})\partial T(\overrightarrow{r},t)/\partial t=\kappa (\overrightarrow{r},T){\nabla }^{2}T(\overrightarrow{r},t)+Q(\overrightarrow{r},t)$$

(1)

where $\rho (\overrightarrow{r})$ is the density of materials, $c(\overrightarrow{r})$ is the specific heat capacity of materials, $T$ is the temperature, $\kappa (T)$ is thermal conductivity, which depends on materials and temperature, and $Q$ is the heat generation rate. Following the standard procedure of the time domain finite element method [64,65,66], the matrix form of Equation (1) can be obtained,

$$\left([M]+\Delta t[K]\right){\left\{T\right\}}^{t+\Delta t}=\Delta t[S]{\left\{Q\right\}}^{t+\Delta t}+[M]{\left\{T\right\}}^t+\{B\}$$

(2)

where $[M]$ is the time-dependent matrix, $[K]$ is the thermal conduction matrix, $[S]$ is the overlap matrix, $\left\{B\right\}$ is the boundary condition matrix, $\left\{Q\right\}$ is the heat generation vector and $\Delta t$ is the time step for time evolution.

The current density in 100 nm SOI MOSFET with device structure, as in [26], can be obtained by solving the Poisson Equation (3), drift-diffusion Equations (4) and (5) and current continuity Equations (6) and (7):

$$-\nabla \cdot \left({ϵ}_r\nabla V\right)=(p-n-N_A+N_D)q/{ϵ}_0$$

(3)

$$J_n=-qn{\mu }_n\nabla V+q{D}_n\nabla n$$

(4)

$$J_p=-qp{\mu }_p\nabla V-q{D}_p\nabla p$$

(5)

$$1/q\times \nabla \cdot J_n+G_n-R=0$$

(6)

$$-1/q\times \nabla \cdot J_p+G_p-R=0$$

(7)

where $V$ is the voltage; n and p are the electron and hole density, respectively; $N_D$ and $N_A$ are the donor and acceptor density, respectively; ${ϵ}_r$ and ${ϵ}_0$ are the relative dielectric and constant vacuum dielectric constant, respectively; and $J_n$, ${\mu }_n$, $D_n$ and $G_n$ are the electron (hole) current density, mobility, diffusion coefficient and generation rate, respectively, where $J_P$, ${\mu }_p$, $D_p$ and $G_p$ are holes. The heat generation in the SOI MOSFET then can be written as,

$$Q=\overrightarrow{J}\cdot \overrightarrow{E}$$

(8)

where $\overrightarrow{J}$ and $\overrightarrow{E}$ are the current density and the electric field intensity, respectively.

On the other hand, for the advanced short-channel field effect transistor in which the quantum transport rather than drift-diffusion transport should be considered, it is quite difficult to obtain the heat generation rate by simulating the quantum transport process with carrier scattering; therefore, Gaussian distribution is usually applied to model the heat generation rate in short channel devices [27,67,68]. Take FinFET as an example. Figure 1a shows the 3D schematics of a 3-Fin 14 nm n-type FinFET, including the source extension, source, channel, drain and drain extension [67,69,70]. The cross sections of the FinFET perpendicular to and parallel to the channel are shown in Figure 1b,c, respectively [33]. The heat generation rate along the channel direction in this FinFET is shown in Figure 2 [33].

2.1.2. Temperature-Dependent Threshold Voltage Shift (TVS) Model

To simulate TVS under time-dependent temperature, TVS can be numerically calculated by [26,27,33],

$$\Delta V_{TH}(n)=\Delta V_{TH}(n-1)+\frac{d\Delta V_{TH}}{dt}|{}_{t=t_n}\cdot \Delta t$$

(9)

where $\Delta V_{TH}$ is the device threshold voltage shift, $n$ is time step and $\Delta t$ is the time interval between two adjacent time steps. $\Delta V_{th}$ is the TVS model under DC voltage stress and usually varies for different device types. A temperature-dependent parameter is introduced for calculating the TVS for SOI MOSFET, and the TVS as a function of time with linear temperature-dependent parameters can be expressed as [26,71],

$$\Delta V_{th}=\Delta V_{th0}{(t/t_0)}^{\alpha }$$

(10)

$$\alpha ={\alpha }_0+\beta (T-T_0)$$

(11)

where $\alpha$ is the temperature-dependent parameter and $t$ is stress time. Equation (9) then can be rewritten as,

$$\begin{array}{l}\Delta V_{th}(n)={\displaystyle \sum _{m=1}^n\frac{\alpha }{t_0}\Delta V_{th0}{(t/t_0)}^{{\alpha }_m-1}dt}\\ \begin{array}{ccc}& & =\Delta V_{th}(n-1)+\frac{\alpha }{t_0}\Delta V_{th0}{(t/t_0)}^{{\alpha }_n-1}dt\end{array}\end{array}$$

(12)

Furthermore, a V_d and V_g dependent term is included into Equation (12) to simulate the TVS under real circuit stress [27],

$$\Delta V_{th}(n)=\Delta V_{th}(n-1)+V_{g,n}^u{V}_{d,n}^v\left[\frac{\alpha }{t_0}\Delta V_{th0}{(\frac{t}{t_0})}^{{\alpha }_n-1}dt\right]$$

(13)

where $V_{g,n}$ and $V_{d,n}$ are the gate voltage $V_g$ and drain voltage $V_d$ at time step $n$, respectively.

In order to capture the saturation behavior of TVS evolution, an empirical model to capture the saturation behavior of TVS evolution for 14 nm FinFET is applied [29,33],

$$\Delta V_{TH}=V_0\left[1-{\mathrm{e}}^{-{(t/\tau )}^m}\right]$$

(14)

where $V_0$ is maximum TVS, $\tau$ associates with bond dissociation rate, $m$ is the exponent of TVS at power law stage and $\tau$ and $m$ are time-dependent for a time-dependent stress voltage and can be expressed as [32],

$$\tau =A{e}^{(-E_a/k_{B}T)}{e}^{[{\Gamma }_1{V}_d-{\Gamma }_2{V}_g]}$$

(15)

$$m=m_0{e}^{[-{(t/{\tau }_m)}^k]}$$

(16)

where $V_g$ and $V_d$ are the gate and drain voltage, respectively; $T$ is the temperature of the device; $k_B$ is the Boltzmann constant; $E_a$ is the activation energy depending on device type and scale; ${\mathsf{\Gamma }}_1$, ${\mathsf{\Gamma }}_2$ and A are coefficients; ${\tau }_m$ and $k$ are fixed parameters for all devices; and $m_0$ is a device-specific parameter. The derivative with respect to time for Equation (14) can then be obtained [33],

$$\begin{array}{ll}\frac{d\Delta V_{TH}}{dt}& =V_0\cdot m\cdot t^{m-1}\cdot {\tau }^{-m}\cdot e^{-{(t/\tau )}^m}\cdot \\ & \left[1-k{\left(t/{\tau }_m\right)}^k{\tau }^{-m}\ln \left(t/{\tau }_m\right)\right]\end{array}$$

(17)

2.1.3. Simulation Results

The I-V curve of SOI MOSFET is obtained by solving the Poisson equation, drift-diffusion equations and current continuity equations [26]. The transient temperature responses for different voltage stress are then calculated as shown in Figure 3a,b [26]. The simulation results in [25] show: (1) the step pulse has much higher temperature response than the AC pulse and pseudo-random binary sequence (PRBS) pulse due to higher input power; (2) the temperature oscillations of the PRBS pulse and low frequency pulse are larger than those of the AC pulse and high-frequency stress, respectively. The PRBS pulse has consecutive On (1.2 V) and Off (0 V) states and the low-frequency AC pulse has a longer On state time, so they have a more time for the temperature to increase or fall.

Based on the temperature response, the TVS under different waveforms and frequencies is further captured as shown in Figure 4a,c [26], respectively. Some trends for a single transistor under different biases can be concluded: (1) as the frequency decreases, the TVS increases; (2) PRBS stress suffers more severe HCI than AC stress at the same frequency [26]. The above-mentioned conclusion is also validated by experiment data [3,15,42,43,60].

2.2. Analytical HCI Model

An analytical model for calculating self-heating peak temperature for digital circuits has been proposed and validated [28]. The HCI lifetime can then captured by inserting the peak temperature into the analytical HCI model [3,28]. The thermal resistance is an average value and the simulation accuracy is not as high as that of numerical simulation. In order to acquire high accuracy, an equivalent thermal circuit model can be established by carefully dividing the simulation region into several sub-domains.

2.2.1. Temperature Prediction via Thermal Equivalent Circuit

The self-heating peak temperature by using the thermal equivalent circuit can be expressed as follows [28]:

$$\begin{array}{ll}\Delta T_{L,Diff}& =\Delta T_L^{pk}-\Delta T_L^{avg}\\ & =H(f,\xi ,\tau )\times \left(P_{pk}-P_{avg}(d,f)\right)\end{array}$$

(18)

$$\Delta T_L^{avg}\equiv R_{th}\times P_{avg}$$

(19)

$$H(f,\xi ,\tau )\equiv R_{th}\left\{\left(1-e^{-\frac{\xi }{f\tau }}\right)\left(1-e^{-\frac{1-\xi }{f\tau }}\right)/\left(1-e^{-\frac{1}{f\tau }}\right)\right\}$$

(20)

$$\tau \equiv R_{th}\times C_{th}$$

(21)

where $\Delta T_{L,Diff}$ is the difference between the maximum temperature ($\Delta T_L^{pk}$) and average temperature ($\Delta T_L^{avg}$); $R_{th}$, $C_{th}$ and $\tau$ are thermal resistance, capacitance and time constant, respectively; $P_{pk}$ and $P_{avg}$ are the maximum and average value of the dissipated function $P(t)$ over time; $f$ and $\xi$ are the frequency and duty cycle of signal; and $H(f,\xi ,\tau )$ is used to calculate $\Delta T_{L,Diff}$ and can be viewed as a differential thermal resistance.

2.2.2. HCI Prediction

The HCI degradation can be captured by introducing the temperature calculated from Equation (19) into the TVS model [28]:

$$\Delta V_{th}=A\times V_{ds}^m\times e^{E_A/k{T}_L}\times t^n$$

(22)

where $\Delta V_{th}$ is the threshold voltage shift; $t$ is the stress time; $T_L$ is lattice temperature; $V_{ds}$ is the voltage between drain and source; and $m$, $n$ and $E_a$ are accelerator factor, time exponent and activation energy, respectively, which are technology- and device-specific parameters [60].

In order to predict the HCI lifetime of the circuit, the lattice temperature in the summarized HCI model Error! is replaced by peak temperature ($T_{pk}$), which can be expressed as

$$T_{pk}=T_0+\Delta T_{pk}$$

(23)

where $T_0$ is the environment temperature and $\Delta T_{pk}$ is calculated by Equation (18) [28].

2.2.3. Application and Simulation Results

A ring oscillator (RO) with variable order of inverter ($N_{inv}$), loaded by the same capacitor $C_{Load}$, was investigated [28], and the peak self-heating temperature is shown in Figure 5a [28]. The symbol is the HSPICE simulation results while the solid line was calculated via the analytical model mentioned in Section 2.1.1 [28]. $\Delta T_L^{pk}$ increases linearly with frequency mainly because $P_{avg}$ increases linearly with frequency and leads to $\Delta T_L^{avg}$ increasing linearly with frequency, as shown in Figure 5b [28]. In contrast, $H$ and $P_{pk}-P_{avg}$ both decrease with frequency [28]. As a consequence, $\Delta T_{L,Diff}\to 0$ at frequencies higher than the technology-specific transistor frequency, which indicates that excess degradation caused by $\Delta T_{L,Diff}$ is negligible [28].

Figure 6a plots the $\Delta V_{th}$ predicted by Equation (22) for low frequency FinFET and 5 order ring oscillator composed of 90 nm with $C_{Load}=10 \mathrm{fF}$ operated at $V_{DD}=1.8 \mathrm{V}$ [28]. Figure 4b illustrates the TVS of FinFET as a function of frequency after 10 years’ operation in RO circuits [28]. The degradation increases with frequency due to higher peak temperature, as shown in Figure 5 [28].

2.3. Trap-Based HCI Model

Typically, HCI are modeled by investigating the carrier transport process, such as the lucky electron model or the energy-driven paradigm [7,24]. However, as the device scales down, it is difficult to model the transport processes in advanced nanoscale devices, including the FinFET, nanowire FET and nanosheet FET, in which the carrier transport is too complex. Therefore, some scientists started to model the traps rather than the increasingly complex carrier transport process [29]. A trap-based compact model is proposed, which is unified across different V_gs/V_ds regions with different carrier-based mechanisms [29,30,31,72,73]. For devices with different geometrical structure and crystal lattice, the trap types as well as their influence on device parameters may be different, thus it is needed to model them separately for different devices.

2.3.1. Trap Type in FinFET

The trap types in FinFET are roughly identified by $\Delta SS(i)/\Delta V_{th}(i)$ and further identified via a stress-induced leakage current (SILC) spectrum technique [29,31], where $\Delta SS$ is the variation of subthreshold swing (SS) and $\Delta V_{th}$ is the variation of threshold voltage ($V_{th}$). Because both interface traps and oxide traps can degrade $\Delta V_{th}$ while only the interface traps can degrade SS, the drop of $\Delta SS(i)/\Delta V_{th}(i)$ with time in FinFET as shown in Figure 7 indicates that both interface traps and oxide traps are generated [29]. By applying SILC spectrum technique [74], two types of oxide traps are identified in the HCI process, as shown in [31].

2.3.2. Trap-Based HCD Model

Taking the interface traps and oxide traps into consideration, a multitrap-based model is proposed and can decompose the contribution of different traps to HCD [29,31]. The total degradation can be modeled by the following equations [29]:

$${\mathrm{HCD}}_{\mathrm{total}}={\mathrm{HCD}}_{\mathrm{interface}}+{\mathrm{HCD}}_{\mathrm{oxide}1}+{\mathrm{HCD}}_{\mathrm{oxide}2}$$

(24)

$${\mathrm{HCD}}_{\mathrm{interface}}=N_0\times \left[1-\exp (-{\mathrm{AR}}_i\times t^n)\right]$$

(25)

$${\mathrm{HCD}}_{\mathrm{oxide}1}={\mathrm{AR}}_1\times \log (1+C_1\times t)$$

(26)

$${\mathrm{HCD}}_{\mathrm{oxide}2}={\mathrm{AR}}_2\times \log (1+C_2\times t)$$

(27)

$$\mathrm{AR}=A{(V_{gs}-V_{th})}^m\exp \left(\frac{-b}{V_{ds}-V_{dsat}}\right)\exp \left(\frac{-E_a}{k_B\times T}\right)$$

(28)

where $N_0$ is the saturation value of the interface trap, AR is the aging rate and $E_a$ is active energy. The model was tested using the following strategy: (1) extract the trap parameter in the single carrier event (SCE) region; (2) calculate the HCD in the multi carrier event (MCE) region using the parameter obtained from the last step. Taking nFinFET as an example, the first step and second step are shown in Figure 8a,b [29], respectively. The prediction is well fitted with experiment data, and parameters between different carrier transport mechanisms are the same, which indicates the model is unified across different $V_{gs}/V_{ds}$ regions.

2.4. Artificial Neural Network Model for HCI

Artificial neural networks are a powerful mathematical tool that can be used to solve complex problems as well as reduce simulation cost [75,76,77,78,79,80,81,82,83]. In order to reduce the simulation cost of numerical methods, an ANN model for 14 nm FinFET HCI prediction with consideration of the self-heating effect is proposed [33]. It can predict HCI induced TVS for FinFET under various environment temperatures and voltage stresses. The model has good accuracy and the average relative error is 0.36% [33]. Once the ANN model is built, it can greatly reduce simulation cost and has great potential in the reliability design of circuits and systems [33]. To train an accuracy ANN model, a large amount of experiment or simulation data are required.

2.4.1. Training Data

Simulation results produced using numerical methods introduced in Section 2.1 are used as the training data and divided into a test set (75%), training set (20%) and validation set (5%) [33]. The inputs are set as environment temperature and the features of stress including frequency, duty cycle, voltage amplitude and transition ratio. Min-Max normalization is applied to eliminate the impact of inconsistent data units,

$$x^{\prime }=\frac{x-X_{min}}{X_{max}-X_{min}}$$

(29)

where $x$ and $x^{\prime }$ are the data before and after normalization, respectively, and $X_{min}$ and $X_{max}$ are the minimum and maximum value in all x, respectively. The scaling parameter $S$ and normalized average temperature ${T^{\prime }}_{avg}$ are set as the training targets. The diagram of the ANN model is shown in Figure 9 [33]. The optimizer is set to the Adam optimizer [84], and the loss function is the mean square error (MSE). The learning rate and the number of training epochs are set to 0.0005 and 100, respectively. The relative error of TVS under 10 years of stress voltage is applied to evaluate the accuracy of the model [33].

2.4.2. Results

Figure 10 is the convergence graph of ANN training [33]. The errors in the validation set and test set are 0.37% and 0.36%, respectively, which means that even for unseen stress voltage conditions the network can predict TVS results accurately. Figure 11 shows the comparison of TVS predicted by ANN and experiments [42] under different (a) environment temperature, (b) voltage amplitude and (c) waveforms [33], in which the ANN results show good agreement with experiment results [33]. Figure 12 compares the ANN results and numerical simulation results under 10 years of stress voltage with different duty cycles, and the gap between the solid lines and dot lines is very small.

3. Conclusions

In summary, various models were developed to reveal the physical mechanisms behind the phenomena, and models were also built to predict the HCI induced device degradation. In this paper, numerical methods, analytical HCI model, trap-based HCI model and ANN model for HCI are reviewed and discussed in detail.

In terms of future research trends, the self-heating effect becomes more severe in gate-all-around devices such as nanosheets and nanowires due to the low thermal conductivity, high power density and stacked topologies that make it difficult to dissipate heat. The HCI will continue to be a significant reliability issue in these devices. There are many potential possibilities. As the carrier transport process become more and more complex for shorter-channel devices, the trap-based compact model that considers the influence of traps is meaningful. Numerical methods are capable to solve TVS under diverse stress voltages with different waveforms and frequencies. However, the simulation cost is high. On the other hand, artificial neural networks are a powerful tool to solve complex problems and reduce simulation cost. Reliability design in circuits and systems with the aid of artificial intelligence is of great potential. It is also very helpful to explore powerful and accurate compact models to give a more complete description of the HCI in advanced nanoscale field effect transistors.