Search Results (41)

With the rapid proliferation of real-time digital communication, particularly in multimedia applications, securing transmitted image data has become a vital concern. While chaotic systems have shown strong potential for cryptographic use, most existing approaches rely on low-dimensional, integer-order architectures, limiting their complexity and resistance to attacks. Advances in fractional calculus and memristive technologies offer new avenues for enhancing security through more complex and tunable dynamics. However, the practical deployment of high-dimensional fractional-order memristive chaotic systems in hardware remains underexplored. This study addresses this gap by presenting a secure image transmission system implemented on a field-programmable gate array (FPGA) using a universal high-dimensional memristive chaotic topology with arbitrary-order dynamics. The design leverages four- and five-dimensional hyperchaotic oscillators, analyzed through bifurcation diagrams and Lyapunov exponents. To enable efficient hardware realization, the chaotic dynamics are approximated using the explicit fractional-order Runge–Kutta (EFORK) method with the Caputo fractional derivative, implemented in VHDL. Deployed on the Xilinx Artix-7 AC701 platform, synchronized master–slave chaotic generators drive a multi-stage stream cipher. This encryption process supports both RGB and grayscale images. Evaluation shows strong cryptographic properties: correlation of $-6.1081\times {10}^{-5}$, entropy of 7.9991, NPCR of 99.9776%, UACI of 33.4154%, and a key space of $2^{1344}$, confirming high security and robustness. Full article

Carbon nanotube field-effect transistors (CNTFETs) are becoming a strong competitor for the next generation of high-performance, energy-efficient integrated circuits due to their near-ballistic carrier transport characteristics and excellent suppression of short-channel effects. However, CNT FETs with large diameters and small band gaps exhibit obvious bipolarity, and gate-induced drain leakage (GIDL) contributes significantly to the off-state leakage current. Although the asymmetric gate strategy and feedback gate (FBG) structures proposed so far have shown the potential to suppress CNT FET leakage currents, the devices still lack scalability. Based on the analysis of the conduction mechanism of existing self-aligned gate structures, this study innovatively proposed a design strategy to extend the length of the source–drain epitaxial region (L_ext) under a vertically stacked architecture. While maintaining a high drive current, this structure effectively suppresses the quantum tunneling effect on the drain side, thereby reducing the off-state leakage current (I_off = 10⁻¹⁰ A), and has good scaling characteristics and leakage current suppression characteristics between gate lengths of 200 nm and 25 nm. For the sidewall gate architecture, this work also uses single-walled carbon nanotubes (SWCNTs) as the channel material and uses metal source and drain electrodes with good work function matching to achieve low-resistance ohmic contact. This solution has significant advantages in structural adjustability and contact quality and can significantly reduce the off-state current (I_off = 10⁻¹⁴ A). At the same time, it can solve the problem of off-state current suppression failure when the gate length of the vertical stacking structure is 10 nm (the total channel length is 30 nm) and has good scalability. Full article

Background/Objectives: Ovarian follicular cysts (OFCs) in dairy cows represent a significant cause of infertility and share striking similarities with polycystic ovary syndrome (PCOS) in women. This study aimed to elucidate the molecular mechanisms underlying OFCs and their relevance to PCOS by profiling differentially expressed (DE) microRNAs (miRNAs) and constructing integrative RNA interaction networks. Methods: Expression analysis of 84 bovine miRNAs was conducted in antral follicular fluid from normal and cystic follicles using miScript PCR arrays. Bioinformatic tools including miRBase, miRNet, and STRING were employed to predict miRNA targets, construct protein–protein interaction networks, and perform gene ontology and KEGG pathway enrichment. Network analyses integrated miRNAs with coding (mRNAs) and non-coding RNAs (circRNAs, lncRNAs, snRNAs). Results: Seventeen miRNAs were significantly dysregulated in OFCs, including bta-miR-18a, bta-miR-30e-5p, and bta-miR-15b-5p, which were associated with follicular arrest, insulin resistance, and impaired steroidogenesis. Upregulated miRNAs such as bta-miR-132 and bta-miR-145 correlated with inflammation, oxidative stress, and intrafollicular androgen excess. Key regulatory lncRNAs such as Nuclear Enriched Abundant Transcript 1 (NEAT1), Potassium Voltage-Gated Channel Subfamily Q Member 1 Opposite Strand/Antisense Transcript 1 (KCNQ1OT1), Taurine-Upregulated 1 (TUG1), and X Inactive Specific Transcript (XIST), as well as circRNA/pseudogene hubs, were identified, targeting pathways involved in metabolism, inflammation, steroidogenesis, cell cycle, and apoptosis. Conclusions: The observed transcriptomic changes mirror core features of human PCOS, supporting the use of bovine OFCs as a comparative model. These findings provide novel insights into the regulatory RNA networks driving ovarian dysfunction and suggest potential biomarkers and therapeutic targets for reproductive disorders. This network-based approach enhances our understanding of the complex transcriptomic landscape associated with follicular pathologies in both cattle and women. Full article

Converters play a critical role in wind power generation systems, with their reliability directly impacting system stability and operational efficiency. To address the challenges posed by increased thermal load fluctuations due to solder layer aging in insulated gate bipolar transistor (IGBT) modules in converters, this paper proposes an aging-aware multi-objective thermal management (AAMO-TM) strategy to enhance the performance of aging modules. An improved junction temperature estimation model is developed, incorporating coordinated control of switching frequency and gate drive resistance to account for the dynamic thermal behavior of IGBT modules during aging. Pareto and hierarchical optimization techniques are employed to resolve the multi-objective problem of excessive junction temperature suppression, junction temperature fluctuation smoothing, and power quality improvement. Experimental results demonstrate that our proposed AAMO-TM strategy outperforms a competing strategy at temperature fluctuation by a large margin (up to 59.4%). Our proposed strategy significantly enhances the thermal stability of aging IGBT modules while effectively suppressing grid-connected current harmonics. This study provides valuable theoretical insights and practical guidance for achieving the stable operation of wind turbines and delivering high-quality power output. Full article

Accurately estimating the battery State of Health (SOH) is crucial for the safe and reliable operation of electric vehicles. Based on the actual operating data of electric buses, this article proposes a battery SOH estimation method that can be applied to multiple operating conditions and indicators. Specifically, the complex operating conditions are simplified into charging and driving conditions through data preprocessing. Under charging conditions, combined with Coulomb counting and incremental capacity analysis methods, a battery SOH estimation model of capacity indicators based on the Bayesian optimization bidirectional gated recursive unit model (BO-BiGRU) is established. Under driving conditions, the adaptive forgetting factor recursive least squares method considering the influence of current is used to identify the battery internal resistance feature. In addition, two separate battery SOH estimation models are established: one for internal resistance indicators based on BO-BiGRU and another for power indicators derived from the actual operational data feature. Finally, a joint battery SOH estimation method considering temperature and different operating conditions is proposed based on the SOH estimation results of the three battery indicators. The verification results show that the average error of the battery SOH estimation method proposed in this article is less than 2%, which has better accuracy for actual vehicles. Full article

In recent years, high-voltage analog switches have been widely used in various fields. To handle complex use scenarios, high-voltage analog switches need to achieve the goals of low on-resistance, high isolation performance, high response speed, and high voltage withstand range. Traditional high-voltage analog switches have issues such as low integration, large area, and slow response speed. This paper uses a super junction MOSFET (SJ-MOS) with a 0.18 μm SOI process and a solid-state relay (SSR) structure to implement a high-voltage analog switch. A gate drive circuit suitable for low gate-source breakdown voltage is proposed to maintain the gate-source voltage, achieving a low on-resistance of 24 Ω and high isolation. Compared with traditional high-voltage analog switches, it achieves higher performance with a smaller area. Full article

This work investigates the performance of state-of-the-art non-commercial 6.5 kV Silicon Carbide (SiC) PiN and Junction Barrier Schottky (JBS) diodes in hybrid (Si IGBT with SiC diode) and full SiC (SiC MOSFET with SiC diode) switch topologies. The static and dynamic performance has been systematically evaluated at distinct temperatures, gate resistances and currents for each configuration. The SiC PiN diode presented higher current density capability and lower leakage current density than the JBS diode. Moreover, in most cases, the SiC PiN diode-based topologies demonstrated slightly higher total switching losses compared to the SiC JBS diode-based equivalent configurations. A loadability analysis in a three-level NPC converter is presented to evaluate the potential of each configuration in a converter application. The SiC PiN technology presented a 25% power extension compared to the SiC JBS technology with similar efficiency at typical industrial drives switching frequency operation when comparing same-active-area diode technologies. Finally, a long-term reliability test (H3TRB) is presented to demonstrate the SiC PiN diode technology’s potential for operation in harsh environments. Such characteristics show the advantage of the 6.5 kV SiC PiN diode when a high current density (>100 A/cm²), high efficiency and reliability are required. Full article

Silicon carbide (SiC) metal-oxide semiconductor field-effect transistors (MOSFETs), as a new material, have the advantages of low drain-source resistance, high thermal conductivity, low leakage current, and high switching frequency compared with silicon (Si)-based MOSFETs. Therefore, in many industrial applications, Si MOSFETs have been replaced by SiC MOSFETs. However, as the switching speed increases exponentially, some problems are amplified, the most serious of which is the overshoot of current and voltage. The increase in voltage and current slope caused by high switching speeds inevitably leads to overshoot, oscillations, and additional losses in the circuit. This paper focusses on the actual performance of the optimised switching strategy (OSS) in circuit testing and combines the existing simulation results to verify the practicability of OSS. In this paper, the optimised switching strategy is introduced first, and then, the LTspice model of SiC MOSFET is established in detail and verifies the feasibility of the OSS through half-bridge circuit simulation. Finally, the test platform is built using a programmable gate drive module (2ASC-12A1HP). Through a 400 V/30 A double-pulse test, the practicality of the OSS is verified. The experiments show that the OSS can greatly improve the switching performance of SiC MOSFETs. Full article

Wide bandgap (WBG) power semiconductor devices are increasingly replacing silicon IGBTs in high-power and high-voltage power electronics applications. However, there is a significant gap in the literature regarding efficient testing methodologies for high-power and high-voltage converters under constrained laboratory resources. This paper addresses this gap by presenting comprehensive, hardware-focused testing methodologies for high-power and high-voltage WBG power semiconductor-based converter bring-up before the control validation phase steps in. The proposed methods enable thorough evaluation and validation of converter hardware, including device switching characteristics, driving circuit functionality, thermal management performance, insulation integrity, and sustained operation at full power. We utilized the double pulse test (DPT) to characterize switching performance in a two-level phase leg configuration, extract circuit parasitics, and validate magnetic components. The DPT was further applied to optimize gate driving circuits, validate overcurrent protection mechanisms, and measure device on-resistance. Additionally, a multicycle test was introduced to rapidly assess steady-state converter performance and estimate efficiency. Recognizing the critical role of thermal management in high-power converters, our methodologies extend to the experimental extraction of key thermal parameters—such as junction-to-ambient thermal resistance and thermal capacitance—via a heat loss injection method. A correlation method between temperature sensor measurements and junction temperature is presented to enhance the accuracy of device temperature monitoring during tests. To ensure reliability and safety, dielectric withstand tests and partial discharge measurements were conducted at both component and converter levels under conventional 60 Hz sinusoidal and high-frequency PWM waveforms. Finally, we highlight the importance of testing converters under full voltage, current, and thermal conditions through power circulating tests with minimal power consumption, applicable to both non-isolated and isolated high-power converters. Practical examples are provided to demonstrate the effectiveness and applicability of these hardware testing methodologies. Full article

This paper presents a thorough robust Class-AB power amplifier design and its application in pressure-mode sensor-on-chip nonlinearity correction. Considering its use in piezoresistive sensing applications, a gain-boosting-aided folded cascode structure is utilized to increase the amplifier’s gain by a large amount as well as enhancing the power rejection ability, and a push–pull structure with miller compensation, a floating gate technique, and an adaptive output driving limiting structures are adopted to achieve high-efficiency current driving capability, high stability, and electronic environmental compatibility. This amplifier is applied in a real sensor nonlinearity correction on-chip system. With the help of a self-designed 7-bit + sign DAC and a self-designed two-stage operational amplifier, this system is compatible with nonlinear correction at different signal conditioning output values. It can also drive resistive sensors as small as 300 ohms and as high as tens of thousands of ohms. The designed two-stage operational amplifier utilizes the TSMC 0.18 um process, resulting in a final circuit power consumption of 0.183 mW. The amplifier exhibits a gain greater than 140 dB, a phase margin of 68°, and a unit gain bandwidth exceeding 199.76 kHz. The output voltage range spans from 0 to 4.6 V. The final simulation results indicate that the nonlinear correction system designed in this paper can correct piezoresistive sensors with a nonlinearity of up to ±2.5% under various PVT (Process–Voltage–Temperature) conditions. After calibration by this system, the maximum error in the output voltage is 4 mV, effectively reducing the nonlinearity to 4% of its original value in the worst-case scenario. Full article

In the inverter circuit, the speed at which the MOSFET is impacted by the presence of a parasitic inductor within the printed circuit board (PCB) leads to a delay in the switching process. Furthermore, the parasitic inductor within the circuit can easily form an LC oscillation with the parasitic capacitor of the MOSFET. These two issues result in an inconsistency between the actual output of the MOSFET and the driving signal waveform, leading to distortion in the sinusoidal pulse width modulation (SPWM) waveform and an increase in total harmonic distortion (THD). It is a common practice to mitigate gate oscillation by introducing a resistor at the gate of the MOSFET. However, elevating the resistance leads to deceleration in the charging process of the MOSFET’s parasitic capacitor, consequently causing an increase in the switching delay, and thereby increasing THD. Therefore, an effective strategy to reduce THD is proposed in this paper, while augmenting the gate resistance, computing the MOSFET switching delay, and applying corrective compensation. In this way, the inherent issues of the switch are addressed, resulting in inverter output waveforms that closely resemble sine waves and reduced THD. Through a combination of simulation and empirical experimentation, the efficacy of the proposed approach in significantly reducing THD in the inverter’s output waveform has been empirically substantiated. Full article

Silicon carbide (SiC) MOSFETs exhibit superior performance compared to traditional silicon (Si) MOSFETs, characterized by faster switching speeds, lower on-resistance, higher breakdown voltage, and greater operational temperature tolerance. These attributes make SiC MOSFETs highly suitable for applications in electric vehicles, charging stations, and mobile devices. However, their rapid switching speed can intensify current and voltage overshoot and oscillations during device switching, leading to increased device losses or potential damage. To address this issue, this paper proposes a current-type active gate drive (AGD) circuit. The circuit first detects the rate of change in the drain current and drain-source voltage. Subsequently, it employs an analog amplifier circuit and adjustable drive resistors to decelerate the rate of change in the drain-source voltage and drain current. As a result, overshoot and oscillation in the drain-source voltage and drain current are mitigated. Experimental results demonstrate that the proposed AGD circuit can reduce drain current overshoot by 60%, drain-source voltage overshoot by 15.38%, and waveform oscillations. Additionally, the AGD circuit decreases conduction and turn-off losses by 24% and effectively mitigates electromagnetic interference (EMI) issues within the frequency range of 0.1 to 3 MHz. Full article

Multipolar bonded magnets based on a thermoset matrix provide the opportunity to expand the applications of bonded magnets, especially within the drive technology industry, in terms of the high thermal and chemical resistance, along with a higher utilisation of the magnetic potential. To realize the application of polymer bonded magnets based on thermosets within the drive technology industry, general design parameters in terms of the material, the process parameters, and the tool concept are needed. These allow for a fundamental realization of multipolar bonded magnets with complex geometries in drive technologies, based on thermosets as the matrix material. This paper investigates the impact of the material (matrix material and filler grade), the process conditions (holding pressure (p_h) and heating time (t_h)), and the tool concept (gating position and system, sleeve material, pole division, and sample thickness) on the magnetic properties in terms of the remanence (B_R) and the deviation (Δs) of the pole division, as well as the orientation of the fillers in the middle of the pole and at the pole pitch. For each parameter, an optimised value is derived. In the majority of the cases, this value is equal in terms of the magnetic properties and the orientation. In terms of the sleeve material and the sample thickness, the ideal value differs between the two criteria. Therefore, an optimised value for each criterion, as well as an overall value, is defined. In terms of the material, PF, along with a high filler grade; in terms of the process conditions, a high holding pressure (p_h) and a low heating time (t_h); and in terms of the tool concept, a two-pinpoint gating system, located in the middle of the pole, a Ferro-Titanit-Cromoni sleeve material, a high pole division, as well as small sample thickness, should be selected to improve the properties of polymer bonded magnets based on thermosets. Full article

This paper presents an in-depth analysis of the oscillation phenomenon occurring in multi-chip parallel automotive-grade power modules under short-circuit conditions and investigates three suppression methods. We tested and analyzed two commercial automotive-grade power modules, one containing two chips and the other containing a single chip, and found that short-circuit gate oscillations were more likely to occur in multi-chip parallel packaged modules than in single-chip packaged modules. Through experimental and simulation analyses, we observed that gate oscillations were mainly caused by the interaction between internal parasitic parameters of the module and the external drive circuit, and we found that high drive resistance and low common emitter inductance between parallel chips could effectively suppress gate voltage oscillations. We also analyzed the two mainstream suppression schemes, increasing the drive gate resistance and placing the drive capacitors in parallel. Unfortunately, we found that these suppression schemes were not ideal solutions because both schemes changed the switching characteristics of the power module. As an alternative, we propose a simple and effective solution that involves adding parallel connections between the parallel chips. Simulation calculations showed that this optimized method reduced the emitter inductance between parallel chips in the upper bridge arm by about 30% and in the lower bridge arm by 35%. Through short-circuit experiments conducted at different DC bus voltages, it has been verified that the new optimized solution effectively resolves gate oscillation issues without affecting the switching characteristics of the power module. Full article

Epidemics of arboviruses in general, and dengue fever in particular, are an increasing threat in areas where Aedes (Ae.) aegypti is present. The effectiveness of chemical control of Ae. aegypti is jeopardized by the increasing frequency of insecticide resistance. The aim of this study was to determine the susceptibility status of Ae. aegypti to public health insecticides and assess the underlying mechanisms driving insecticide resistance. Ae. aegypti eggs were collected in two study sites in the vicinity of houses for two weeks using gravid Aedes traps (GATs). After rearing the mosquitoes to adulthood, female Ae. aegypti were exposed to diagnostic doses of permethrin, deltamethrin and bendiocarb, using Centers for Disease Control and Prevention (CDC) bottle bioassays. Unexposed, un-engorged female Ae. aegypti were tested individually for mixed-function oxidase (MFO), glutathione-S-transferase (GST) and α and β esterase activities. Finally, allele-specific PCR (AS-PCR) was used to detect possible kdr mutations (F1534C, S989P, and V1016G) in the voltage-gated sodium channel gene in insecticide-exposed Ae. aegypti. Most traps were oviposition positive; 93.2% and 97% of traps contained Ae. aegypti eggs in the 10^ème arrondissement of Cotonou and in Godomey-Togoudo, respectively. Insecticide bioassays detected resistance to permethrin and deltamethrin in both study sites and complete susceptibility to bendiocarb. By comparison to the insecticide-susceptible Rockefeller strain, field Ae. aegypti populations had significantly higher levels of GSTs and significantly lower levels of α and β esterases; there was no significant difference between levels of MFOs. AS-PCR genotyping revealed the possible presence of 3 kdr mutations (F1534C, S989P, and V1016G) at high frequencies; 80.9% (228/282) of the Ae. aegypti tested had at least 1 mutation, while the simultaneous presence of all 3 kdr mutations was identified in 13 resistant individuals. Study findings demonstrated phenotypic pyrethroid resistance, the over-expression of key detoxification enzymes, and the possible presence of several kdr mutations in Ae. aegypti populations, emphasizing the urgent need to implement vector control strategies targeting arbovirus vector species in Benin. Full article