Search Results (642)

State-of-charge (SOC) and state-of-health (SOH) of lithium-ion batteries are critical parameters in battery management systems, directly impacting the driving range, performance stability, and safety of electric vehicles. To improve the accuracy and stability of SOC and SOH estimation simultaneously, this paper proposes a joint estimation method with constant-current bias compensation. First, based on a second-order RC equivalent circuit model, a constant-current bias compensation term is introduced into the Kalman filter framework. The estimation accuracy and robustness of SOC are validated under multiple operating conditions and noise levels. Then, a model integrating Transformer and gated recurrent unit is constructed. The fata morgana algorithm (FATA) is adopted for hyperparameter optimization. Ablation studies and multi-model comparative experiments are conducted to verify the model’s accuracy. Finally, capacity correction is performed using SOH results. By combining current bias compensation and precise temporal features extracted from aging data, joint estimation of SOC and SOH is achieved. Results show that after introducing current bias compensation and aging-based capacity correction, the accumulated SOC estimation error is reduced by more than 10%, while SOH estimation achieves a MAPE below 0.90% and an RMSPE below 1.10%. The proposed joint method is thus verified to be accurate and practical. Full article

Silicon carbide (SiC) MOSFETs are critical for next-generation power electronics, yet their reliability is challenged by alternating-current Bias Temperature Instability (AC BTI). While charge trapping and Recombination-Enhanced Defect Reaction (REDR) are known degradation pathways, the specific role of gate oxide thickness in determining the dominant mechanism remains unclear. This study investigates the degradation behaviors of SiC MOSFETs with varying oxide thicknesses under 150 kHz Dynamic Gate Stress. By maintaining a constant electric field, we decouple the effects of oxide thickness using high-frequency C-V, quasi-static gate current (I_GS) characteristics, and transconductance analysis. Results reveal that thin-oxide devices exhibit parallel C-V shifts and stable transconductance, indicating degradation driven by deep-level charge trapping. Conversely, thick-oxide devices display significant C-V stretch-out, negligible I_GS peak shifts, and severe transconductance degradation, accompanied by irreversible threshold voltage drift. We conclude that despite identical electric fields, the higher driving voltages in thick-oxide devices trigger severe interface state generation consistent with the REDR model, whereas thin-oxide devices are dominated by bulk oxide trapping. These findings highlight the necessity of thickness-dependent optimization strategies for SiC power devices. Full article

Battery ageing is inevitable during operation, leading not only to performance degradation but to potential safety concerns. Consequently, accurate prediction of the state of health (SOH) of lithium-ion batteries is crucial for ensuring their safety and reliability. This study proposed a novel hybrid neural network architecture that integrates a transformer module, an empirical degradation (ED) model, and a gated recurrent unit (GRU). The transformer module enhances the global representation of the feature sequence, while the ED model comprehensively considers the impact of temperature on the rate of battery capacity degradation, compensating the un-interpretability of the transformer architecture in predicting SOH. In addition, pseudo-incremental capacity curves have been obtained using charging fragments from multi-stage constant current fast charging, which solves the issue of extracting mechanism features under fast charging conditions. Experimental results demonstrate that, across a wide temperature range, the model maintains a low average RMSE between 0.43% and 0.59% for prediction horizons of 4 to 128 cycles. Specifically, the average RMSE is 0.87% at −5 °C and 0.37% between 25 °C and 55 °C. Compared to standalone data-driven models, the proposed hybrid architecture reduces prediction error by approximately 50% at 25 °C, exhibiting superior predictive performance and robustness. Full article

Twisted graphene/hexagonal boron nitride (TG/hBN) bilayers, with their tunable moiré potential and atomically clean interfaces, offer an ideal platform for high-performance single-electron transistors (SET). Combining quantum transport simulations with first-principles calculations, we systematically investigate how stackings (AA, AB, BA), twist angles, quantum dot sizes, and gate-island coupling jointly modulate SET performance. Our central finding reveals a clear hierarchy: quantum dot size and stacking configuration dominate charge stability and transport, while twist angle introduces precise control of charge state. All stackings exhibit sharp, symmetric Coulomb blockade peaks, confirming stable single-electron tunneling, and gate coupling remains highly linear across parameters. Strikingly, only AA-stacked devices show a systematic twist-angle-dependent shift in conductance peaks, a direct signature of its perfect atomic registry and extreme angular sensitivity. This work establishes an idealized “size-, stacking-, and twist-angle modulation” design principle and theoretical roadmap based on TG/hBN, providing fundamental insights for future experimental exploration of tunable, low-noise quantum-electronic devices from twisted 2D heterostructures. Full article

Accurate prediction of the state of charge (SoC) of batteries is essential for ensuring the safe, reliable, and uninterrupted operation of electric vehicles (EVs). The prediction fundamentally depends on the ability to accurately predict power consumption. This study investigates the use of GPS-derived information to support SoC prediction, with a particular focus on repeated loop routes such as campus shuttles and closed-circuit EV operations. Real-world driving data are collected using a self-built electric vehicle equipped with a custom battery management system (BMS). These data are used to train three deep learning models, namely gated recurrent unit (GRU), long short-term memory (LSTM), and Transformer, to predict the future SoC of the EV. Experimental results show that the GPS-assisted model consistently outperforms the non-GPS baseline, achieving up to a 23% improvement in prediction accuracy for one-minute-ahead predictions and up to a 76% improvement for ten-minute-ahead predictions. These results demonstrate that GPS-assisted SoC prediction can be effective for forward-looking energy management in practical electric mobility applications. Full article

This paper evaluates and compares four data-driven methods (Gaussian Process Regression (GPR), echo state network (ESN), gated recurrent unit (GRU), and long short-term memory (LSTM)) for lithium-ion capacity prognostics adapted to electric vehicle conditions. This comparison aims to find the most efficient prognosis method considering two constraints: the limitation of computational power and the unavailability of on-board capacity measurement that requires full charge and discharge conditions. The machine learning models are trained using capacity values estimated under vehicle conditions. The ageing data is collected from cycling tests of two battery chemistries, Lithium Fer Phosphate (LFP) and Nickel Manganese Cobalt (NMC), with different ageing trends. The prognosis algorithms are tuned with three different percentages of the data, allowing for the evaluation of the methods at different ageing stages. The comparison and analysis of the results show that ESN outperforms other methods; it has the lowest prediction error (mean absolute percentage error less than 1.4% at initial ageing of the cells) and the shortest training time, making it the most appropriate method for automotive applications. Full article

This study presents a detailed electrical analysis of AlGaN/GaN/Si HEMTs grown by molecular beam epitaxy, using direct and pulse current, small-signal microwave, and deep-level transient spectroscopy (DLTS) techniques to investigate transport characteristics and defect-related effects. DC measurements revealed self-heating effects and leakage currents, while RF analysis highlighted the devices’ high-frequency capabilities alongside parasitic effects linked to deep-level traps. Pulsed I–V characterization demonstrated gate-lag and drain-lag behaviors associated with dynamic charge trapping. DLTS identified electron traps, emphasizing their critical role in device degradation and switching performance. The strong correlation between trap states and electrical behavior underlines the importance of defect control for enhancing efficiency and reliability. Full article

The continuous scaling of microelectronic technology nodes has imposed fundamental physical constraints on conventional floating-gate (FG) non-volatile memory, driving the adoption of charge-trapping memory such as Silicon–Oxide–Nitride–Oxide–Silicon (SONOS) technology. SONOS devices offer advantages in scalability, endurance, and compatibility with advanced CMOS processes, yet their high-temperature reliability remains challenging due to charge loss mechanisms influenced by device structure and material properties. In this work, we systematically evaluate the reliability of two-transistor SONOS memory fabricated using a 28 nm high-K metal gate (HKMG) process. A refined temperature-dependent charge loss model (T-model) is introduced, which, by incorporating a characteristic temperature parameter (T₀) that captures the dynamic shift in activation energy, fundamentally departs from the constant-activation energy assumption of the conventional Arrhenius model. This approach more accurately describes charge retention behavior across a wide temperature range. Experimental results demonstrate excellent device performance, including endurance exceeding 10⁴ program/erase cycles at 85 °C and data retention over 10 years at 85 °C. The T-model shows strong agreement with measured data, providing a physically grounded framework for predicting long-term reliability. This study not only validated a novel charge loss model, providing insights for predicting the failure time of SONOS memory, but also demonstrated that HKMG-integrated SONOS memory exhibits high reliability. Full article

Ion-Sensitive Field-Effect Transistors (ISFETs) have been extensively used to detect various biomolecules, as the intrinsic charge of these molecules can change the transistor’s current or threshold voltage. Recently, realizing ISFET biosensors with better performance has attracted much attention. This paper proposes a novel ISFET biosensor by using the advantage of Tunnel Field-Effect Transistor (TFET). The device characteristics and sensing performance are systematically investigated by Silvaco Atlas TCAD simulations. Due to the novel structural design, the proposed sensor achieves a maximum current sensitivity (S_IDSmax) of 99.99% and a threshold voltage sensitivity (S_VTH) of 124%. To provide optimization guidelines, this work further explored the effect of geometric dimensions and gate dielectric materials on device performance. The excellent performance of the proposed biosensor makes it a promising candidate for future low-power, high-sensitivity biodetection applications. Full article

This study analyzed the low-frequency noise characteristics of nanosheet field-effect transistors (NSFETs) using technology computer-aided design (TCAD) simulations. In particular, the effects of shallow trench isolation (STI) depth and gate–insulator interface trap density on the device’s flicker noise power spectral density (PSD) were systematically evaluated. The simulation results show that as STI depth increases, excessive trap charges formed in the STI oxide can deplete or invert the substrate beneath the STI layer, reducing the threshold voltage of parasitic transistors and thereby increasing flicker noise. In contrast, the shallow STI structure’s trapped charge density was found to be lower than in thicker structures. Additionally, when an HfO₂–ZrO₂ (HZO)-based ferroelectric insulator is applied, improved gate–field control and reduced trap-induced noise are observed compared to HfO₂. Optimization results indicate that the optimal noise performance is achieved with an STI depth of 3 nm and a SiO₂/silicon interface trap density of 1 × 10¹⁰ eV⁻¹cm⁻². This study provides a design direction for low-noise NSFETs through structural (STI) and material (interface traps and HZO) optimization and is expected to contribute to the development of next-generation low-power, high-reliability logic devices. Full article

Reliability testing for Single Event Effects (SEEs) requires accurate localization of heavy-ion tracks from projection images. Conventional localization often relies on handcrafted features and geometric fitting, which is sensitive to noise and difficult to accelerate in hardware. This paper presents a lightweight detector based on YOLOv5n that treats charge tracks in Topmetal pixel sensor projections as distinct objects and directly regresses the track angle and intercept, along with bounding boxes, in a single forward pass. On a synthetic dataset, the model achieves a precision of 0.9626 and a recall of 0.9493, with line-parameter errors of 0.3930° in angle and 0.4842 pixels in intercept. On experimental krypton beam data, the detector reaches a precision of 0.92 and a recall of 0.96, with a position resolution of 52.05 μm. We further deploy the model on an Xilinx Alveo U200, achieving an average per-frame accelerator latency of 3.1 ms while preserving measurement quality. This approach enables accurate, online track localization for SEE monitoring on Field-Programmable Gate Array (FPGA) platforms. Full article

This paper presents the FPGA implementation and verification of a lightweight one-dimensional convolutional neural network (1D-CNN) pipeline for real-time battery state-of-charge (SoC) estimation in automotive battery management systems. The proposed model employs separable 1D convolution and global average pooling, and applies aggressive structured pruning to reduce the number of parameters from 3121 to 358, representing an 88.5% reduction, without significant accuracy loss. Using quantization-aware training (QAT), the network is trained and executed in INT8, which reduces weight storage to one-quarter of the 32-bit baseline while maintaining high estimation accuracy with a Mean Absolute Error (MAE) of 0.0172. The hardware adopts a time-multiplexed single MAC architecture with FSM control, occupying 98,410 gates under a 28 nm process. Evaluations on an FPGA testbed with representative drive-cycle inputs show that the proposed INT8 pipeline achieves performance comparable to the floating-point reference with negligible precision drop, demonstrating its suitability for in-vehicle BMS deployment. Full article

Stretchable semiconductors capable of maintaining electrical performance under large mechanical deformation are essential for reliable wearable electronic devices. However, polymer semiconductors often suffer from electrical degradation when subjected to tensile strain. In this study, electrical stability under strain was achieved by using a rubber-blended poly(2,5-bis(2-octyldodecyl)-3,6-di(thiophen-2-yl)diketopyrrolo[3,4-c]pyrrole-1,4-dione-alt-thieno[3,2-b]thiophene) (DPPT-TT) polymer semiconductor based on a conjugated polymer/elastomer phase separation-induced elasticity (CONPHINE) structure. Unlike most previous studies on fully stretchable thin-film transistors (TFTs), which primarily report overall performance changes under mechanical strain, this work systematically identifies the dominant origin of electrical performance degradation through a stepwise electrical analysis encompassing the gate insulating layer, the semiconductor layer, and complete devices. Bottom-gate top-contact (BGTC) and bottom-gate bottom-contact (BGBC) devices were fabricated on rigid Si/SiO₂ substrates to examine the intrinsic properties of the DPPT-TT/styrene-ethylene-butylene-styrene (SEBS) CONPHINE film. As a result, the device exhibits 90% mobility retention even at 100% tensile strain applied parallel to the charge transport direction. Quantitative resistance analysis using the Y-function method reveals that variations in channel resistance play a dominant role in strain-induced performance degradation, whereas changes in contact resistance contribute only marginally. These findings demonstrate that stabilizing channel resistance, rather than contact resistance, is important for achieving high mobility retention under large mechanical deformation, thereby providing concrete and quantitative design guidelines for reliable stretchable TFTs. Full article

Accurate forecasting of citywide electric vehicle (EV) charging load is critical for alleviating station-level congestion, improving energy dispatching, and supporting the stability of intelligent transportation systems. However, large-scale EV charging networks exhibit complex and heterogeneous spatio-temporal dependencies, and existing approaches often struggle to scale with increasing station density or long forecasting horizons. To address these challenges, we develop a modular spatio-temporal prediction framework that decouples temporal sequence modeling from spatial dependency learning under an encoder–decoder paradigm. For temporal representation, we introduce a global aggregation mechanism that compresses multi-station time-series signals into a shared latent context, enabling efficient modeling of long-range interactions while mitigating the computational burden of cross-channel correlation learning. For spatial representation, we design a dynamic multi-scale attention module that integrates graph topology with data-driven neighbor selection, allowing the model to adaptively capture both localized charging dynamics and broader regional propagation patterns. In addition, a cross-step transition bridge and a gated fusion unit are incorporated to improve stability in multi-horizon forecasting. The cross-step transition bridge maps historical information to future time steps, reducing error propagation. The gated fusion unit adaptively merges the temporal and spatial features, dynamically adjusting their contributions based on the forecast horizon, ensuring effective balance between the two and enhancing prediction accuracy across multiple time steps. Extensive experiments on a real-world dataset of 18,061 charging piles in Shenzhen demonstrate that the proposed framework achieves superior performance over state-of-the-art baselines in terms of MAE, RMSE, and MAPE. Ablation and sensitivity analyses verify the effectiveness of each module, while efficiency evaluations indicate significantly reduced computational overhead compared with existing attention-based spatio-temporal models. Full article

This paper investigates the degradation characteristics of a DC/DC converter operating under cold redundancy conditions when subjected to total ionizing dose (TID) effects. An optimized RCC isolated auxiliary power supply circuit was evaluated through ⁶⁰Co γ-ray irradiation up to 100 krad(Si) at dose rates of 3.89, 8.89, and 13.89 rad (Si)/s, with electrical characterizations performed at both the system level and the device level, focusing on the critical VDMOS transistors. The results indicate that the main output voltage and conversion efficiency remain essentially stable after irradiation, whereas the auxiliary supply voltage and efficiency degrade significantly, leading to a pronounced reduction in the controller supply margin. Device-level measurements reveal a negative threshold voltage shift of approximately 0.5–1.0 V with clear dose-rate dependence, while the subthreshold swing shows no obvious variation, suggesting that the degradation is primarily dominated by oxide-trapped charge effects. In addition, a substantial increase in drain current at low gate voltages is observed, which may further exacerbate restart risks under cold redundancy conditions. These findings demonstrate that the auxiliary power supply and startup margin constitute critical vulnerability points of cold-redundant DC/DC converters under TID stress and should therefore be primary targets for radiation-hardened design. Full article