Impact of Gate Oxide Thickness on the Failure Mechanisms of AC Bias Temperature Instability in SiC MOSFETs

Abstract

Silicon carbide (SiC) MOSFETs are critical for next-generation power electronics, yet their reliability is challenged by alternating-current Bias Temperature Instability (AC BTI). While charge trapping and Recombination-Enhanced Defect Reaction (REDR) are known degradation pathways, the specific role of gate oxide thickness in determining the dominant mechanism remains unclear. This study investigates the degradation behaviors of SiC MOSFETs with varying oxide thicknesses under 150 kHz Dynamic Gate Stress. By maintaining a constant electric field, we decouple the effects of oxide thickness using high-frequency C-V, quasi-static gate current (I_GS) characteristics, and transconductance analysis. Results reveal that thin-oxide devices exhibit parallel C-V shifts and stable transconductance, indicating degradation driven by deep-level charge trapping. Conversely, thick-oxide devices display significant C-V stretch-out, negligible I_GS peak shifts, and severe transconductance degradation, accompanied by irreversible threshold voltage drift. We conclude that despite identical electric fields, the higher driving voltages in thick-oxide devices trigger severe interface state generation consistent with the REDR model, whereas thin-oxide devices are dominated by bulk oxide trapping. These findings highlight the necessity of thickness-dependent optimization strategies for SiC power devices.

1. Introduction

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have become the core building block of next-generation power electronic systems by virtue of their outstanding intrinsic physical properties, including a wide bandgap, a high critical breakdown electric field, and excellent thermal conductivity [1,2,3]. These unique characteristics make them an indispensable component for high-efficiency power electronic applications such as electric vehicle (EV) traction inverters, photovoltaic power generation systems, and solid-state transformers [4,5]. However, despite the continuous advancement in the commercialization of silicon carbide (SiC) power devices, the long-term reliability of the gate oxide remains a critical technical bottleneck limiting their large-scale industrial application [6]. Influenced by carbon clusters and the transition region at the SiC/SiO₂ interface, the interface trap density (D_it) of SiC MOSFETs is typically several orders of magnitude higher than that of silicon-based MOSFETs. This issue severely constrains the threshold voltage (Vth) stability of these devices [7].

Among the various reliability issues afflicting SiC MOSFETs, Bias Temperature Instability (BTI) is one of the most detrimental failure mechanisms. While static direct-current (DC) BTI has been thoroughly investigated in the existing literature [8,9], research attention has recently shifted to Alternating-Current Bias Temperature Instability (AC BTI)—also known as Gate Switching Instability (GSI) or Dynamic Gate Stress (DGS) [10]. This phenomenon occurs during the dynamic switching operation of Pulse Width Modulation (PWM) converters, which constitute the core topology of modern power electronic converters. Experimental studies confirm that, compared to static stress conditions, the dynamic switching process induces a more pronounced and complex threshold voltage (Vth) drift [11,12]. For instance, Jiang et al. elucidated that the switching transient itself acts as a driving force for gate oxide degradation in SiC MOSFETs [11], while Salmen et al. indicated that the bipolar switching process plays a critical role in the generation of interface defects [13].

Despite substantial research efforts dedicated to AC BTI, the underlying physical mechanism governing this phenomenon remains highly controversial, with two distinct theoretical frameworks prevailing in the relevant literature: charge trapping and detrapping in pre-existing oxide traps, and the generation of new interface states at the SiC/SiO₂ interface [14,15]. The latter is commonly described by the Recombination-Enhanced Defect Reaction (REDR) model, in which the energy released from electron–hole recombination facilitates the cleavage of precursor bonds (e.g., Si–H bonds) at the SiC/SiO₂ interface [9,15]. Recent investigations have employed advanced material characterization techniques—such as the split capacitance–voltage (C-V) method [16] and gate charge monitoring [17]—to identify the specific locations of these degradation-induced defect sites. Nevertheless, most existing studies have focused primarily on the effects of external stress parameters (e.g., switching frequency, duty cycle) [18]. In contrast, the influence of intrinsic device structural parameters—specifically gate oxide thickness (t_ox)—on the dominant AC BTI degradation pathway (i.e., bulk oxide trapping versus interfacial bond dissociation) remains largely underexplored in current research [19].

To bridge this critical knowledge gap, this paper presents a systematic and comprehensive study on the role of gate oxide thickness in the AC Bias Temperature Instability (AC BTI) degradation mechanism of SiC MOSFETs. By maintaining a constant electric field within the gate oxide, multi-dimensional characterization methods are utilized to effectively decouple the independent influence of oxide thickness, thereby revealing the physical origins underlying the distinct degradation paths between thick- and thin-oxide SiC MOSFETs.

2. Materials and Methods

2.1. Device Under Test (DUT) and Experimental Setup

In this study, two groups of commercial planar-gate N-channel 4H-SiC MOSFETs were selected to investigate the impact of gate oxide thickness on AC BTI degradation mechanisms. The key electrical and structural parameters of the devices are summarized in

Table 1. DUT key parameters.

Device	VDSmax	VGSmax	ID	RDS(on)	Toxide	Gate Structure
DUTA	1200 V	+22/−8 V	121 A	18 mΩ	40 nm	Planar
DUTB	1200 V	+19/−8 V	112 A	20 mΩ	35 nm	Planar

. As shown in Table 1, both DUT A and DUT B are 1200 V-class SiC MOSFETs with comparable on-resistance (R_DS(on) $\approx$ 20 mΩ) and current ratings (I_D $\approx$ 110–120 A), indicating similar chip sizes and conduction capabilities. The critical difference lies in the maximum gate voltage rating (V_GS,max). DUT A allows for a higher positive gate bias (+22 V) compared to DUT B (+19 V). This discrepancy directly reflects the difference in gate oxide thickness: DUT A employs a thicker gate oxide to support higher absolute drive voltages, whereas DUT B utilizes a thinner oxide optimized for lower voltage operation. This structural distinction is the fundamental variable in our comparative study.

The devices feature identical cell geometries and channel doping concentrations but differ significantly in their gate oxide thickness (t_ox), 40 nm for DUT A and 35 nm for DUT B, as specified by the manufacturer, as summarized in Table 1. These values are not listed in public datasheets, due to proprietary reasons, but were verified in this study through high-frequency capacitance–voltage (C-V) measurements. DUT A represents a high-voltage design characterized by a thicker gate oxide, whereas DUT B represents a medium-voltage design with a thinner oxide layer. To ensure the reliability and reproducibility of the study, the devices under test (DUTs) selected for this evaluation are commercial off-the-shelf (COTS) 1200 V SiC MOSFETs. Furthermore, to rule out geometry-dependent degradation phenomena (such as electric field crowding at trench corners) and isolate the gate oxide thickness as the sole structural variable, both DUT A and DUT B feature a standard planar-gate architecture. Furthermore, as officially confirmed by the device manufacturer, both DUT A and DUT B were fabricated utilizing the exact same standard production process flow. Critical fabrication parameters—including the thermal oxidation temperature, post-oxidation annealing (POA) conditions, and channel doping concentrations—are completely identical for both device types. The sole variable in their manufacturing process was the oxidation time, carefully controlled to achieve the targeted gate oxide thicknesses of 40 nm and 35 nm, respectively. This strict process consistency perfectly preserves the single-variable experimental design, ensuring that any observed divergence in degradation mechanisms is exclusively attributable to the oxide thickness variation.

A dedicated reliability test system PSL-DHTGB(Wuxi Nengxin Testing Technology Co., Ltd., Wuxi, China) was utilized for high-precision dynamic stress testing. As shown in Figure 1, the experimental setup is primarily composed of the following core modules:

• High-Frequency Function Signal Generator: Generates standard square-wave signals as the Dynamic Gate Stress (DGS) source, with precise control over signal frequency and duty cycle.
• High-Speed Gate Drive Circuit: A custom-designed PCB circuit with minimized parasitic inductance, which prevents voltage overshoot or oscillation during high-speed switching and ensures authentic, distortion-free stress waveforms are applied to the device gate.
• Precision Thermal Chamber: All dynamic stress and electrical characterization procedures in this study were strictly performed at a constant room temperature of 25 °C. While Bias Temperature Instability (BTI) in practical power device operation is inherently temperature-dependent, this specific ambient condition was deliberately selected to achieve fundamental mechanism decoupling. By minimizing the ambient thermal energy contribution, we effectively suppressed the widespread thermally activated charging and discharging of deep bulk traps, which would otherwise obscure the electric-field-driven effects. This strict single-variable approach allows us to isolate and highlight the structural degradation driven purely by high electric fields and non-radiative carrier recombination. Consequently, the severe and irreversible defect generation (e.g., the REDR mechanism) observed at 25 °C provides direct evidence that the mechanism bifurcation between the thick- and thin-oxide devices is intrinsically driven by their differing carrier transport dynamics, rather than being a thermally assisted aging process.

Throughout the dynamic stress phase, the drain and source terminals of the DUTs Vbias stress condition, ensuring that stress is applied exclusively across the gate oxide layer and the High-Temperature Reverse Bias (HTRB) effect potentially induced by the drain-source voltage ($V_{DS}$) is excluded.

2.2. Dynamic Gate Stress (DGS) Conditions

To rigorously isolate the effect of oxide thickness from electric field intensity, a constant electric field stress strategy was employed. The peak gate–source voltage (V_GS) applied to each device was carefully calibrated based on its specific oxide thickness to ensure that the maximum electric field across the oxide (E_ox) remained consistent between the two groups. The electric field is defined as

$$E_{ox}={\displaystyle \frac{V_{GS}-V_{FB}}{t_{ox}}}\approx {\displaystyle \frac{V_{GS}}{t_{ox}}}$$

(1)

where V_FB is the flat-band voltage. Consequently, DUT A was subjected to a higher driving voltage (V_{GS_High}), while DUT B was driven at a lower voltage (V_{GS_Low}), satisfying the condition E_{ox_A} ≈ E_{ox_B} (as shown in Table 1). The specific stress parameters were set as follows:

Frequency: The AC stress frequency was explicitly set to 150 kHz. This frequency was selected not only because it aligns precisely with the typical switching operations of state-of-the-art SiC power converters (e.g., EV on-board chargers and DC–DC converters), but also because the corresponding microsecond-level pulse width efficiently isolates the dynamic response of fast interface states from the slow bulk trapping phenomena typically observed under DC stress.

Duty Cycle: 50%. This ensures the device spends equal time in the on and off states during each cycle, achieving a balanced positive and reverse gate stress.

Temperature: Room temperature (25 °C). This is chosen to establish a baseline, which eliminates interference from additional thermally activated mechanisms (e.g., ion drift) induced by high temperatures and allows the study to focus exclusively on electric field-driven degradation effects.

Stress Duration: 10¹¹ cycles. This complies with current international standards such as AQG 324 [20].

2.3. Characterization Methodology

To decouple the degradation mechanisms, a comprehensive multi-dimensional characterization suite was utilized. All post-stress electrical characteristics, including static I-V and dynamic C-V measurements, were performed using a Keysight B1505A Power Device Analyzer (Keysight Technologies, Inc., Santa Rosa, CA, USA). The stress test was periodically interrupted at logarithmic time intervals to monitor parameter evolution. To ensure data accuracy and reproducibility, the following specific extraction methods were applied:

High-Frequency C-V Measurement: Capacitance–voltage (C-V) curves were measured at 1 MHz to monitor total charge trapping and interface state generation.

The shift in flat-band voltage V_FB serves as a primary indicator for oxide traps, while the change in curve slope (stretch-out) indicates the generation of interface states. Specifically, oxide traps Not act as fixed charges because their energy levels are largely unresponsive to the moving surface Fermi level during the C-V sweep. This constant charge provides a steady electrostatic screening effect, resulting in a rigid parallel shift ΔV_FB without changing the curve’s slope. Conversely, interface states D_it are energetically distributed across the SiC bandgap. As the gate voltage sweeps, the surface Fermi level moves, causing these traps to dynamically capture or emit carriers. This dynamic change in interface charge ΔQ_it requires an additional gate voltage to alter the surface potential, causing the C-V curve to stretch out along the voltage axis.

High-Frequency C-V Measurement: Capacitance–voltage (C-V) curves were measured at 1 MHz to monitor total charge trapping and interface state generation. Yang et al. proposed an accurate datasheet-driven analytical model for SiC MOSFETs, which incorporated stage-dominant Cgs(V_Gs,V_ds) and Cgd(V_Gs,V_ds) with physics-based expressions, providing a theoretical basis for the quantitative analysis of capacitance–voltage characteristics of SiC MOSFETs under variable-bias conditions [21].

Quasi-Static Gate Charging (I_g-V_GS) Spectrometry: To distinguish between fast interface states and slow/fixed oxide traps, quasi-static gate current (I_g) measurements were performed with a slow ramp rate (step: 100 mV, hold: 50 ms). The gate current relates to the differential capacitance as

$$I_g\left(V_{GS}\right)={\displaystyle \frac{d{Q}_G}{dt}}=C_{gg}\left(V_{GS}\right)\cdot {\displaystyle \frac{d{V}_{GS}}{dt}}$$

(2)

A shift in the I_g peak voltage indicates stable charge trapping in the bulk oxide. These stable trapped charges establish a permanent internal electric field that alters the macroscopic electrostatic operating point of the device, requiring a different external gate voltage to reach the critical internal field for carrier injection. In contrast, a lack of shift in the I_g peak suggests the dominance of fast interface states. Due to their very short emission time constants, these fast states emit their captured carriers almost instantaneously during the slow measurement sweep. Because they fail to form a stable, long-lasting electrostatic shield, the voltage position of the I_g peak remains unshifted.

Transconductance (g_m) Analysis: Linear region transfer characteristics (I_D-V_G) were measured at V_DS = 100 mV. To minimize measurement noise and differentiation artifacts, the raw ID-VG data were smoothed using a Savitzky–Golay filter (window size: 15 points, polynomial order: 2) prior to the transconductance calculation:

Threshold Voltage Extraction: The threshold voltage (V_th) was extracted using the constant-current method at a specific drain current of I_D = 18 mA to ensure consistent comparison across different stress times.

$$g_m={\displaystyle \frac{\partial I_D}{\partial V_{GS}}}\approx {\displaystyle \frac{W}{L}}{C}_{ox}{\mu }_{FE}{V}_{DS}$$

(3)

3. Results

Statistical Validity: It should be noted that the degradation trends presented in the following sections were consistently observed across multiple device samples (N = 5) for each group (thick vs. thin). This confirms that the observed divergence in degradation mechanisms is a statistically significant characteristic of the oxide thickness, rather than an artifact of individual device variation.

3.1. Macro-Perspective: Drift and Distortion in C-V Characteristics

Figure 2 illustrates the evolution of the gate–source capacitance (C_GS) versus gate voltage (V_GS) measured at a high frequency of 1 MHz. To qualitatively separate the contributions of oxide trapped charges (ΔN_ot) and interface state charges (ΔN_it), the total threshold voltage drift (ΔV_th) is analyzed based on the electrostatic relationship:

$$\mathrm{\Delta }{V}_{th}=\mathrm{\Delta }{V}_{ot}+\mathrm{\Delta }{V}_{it}=-{\displaystyle \frac{q\mathrm{\Delta }{N}_{ot}}{C_{ox}}}\pm {\displaystyle \frac{q\mathrm{\Delta }{N}_{it}}{C_{ox}}}$$

(4)

where $q$ is the elementary charge, C_ox is the oxide capacitance per unit area, and ΔN_ot and ΔN_it represent the changes in oxide trap and interface state densities, respectively.

DUT B (Thin Oxide): Rigid Parallel Shift. As shown in Figure 2, the C-V curves of the thin-oxide device exhibit a near-ideal rigid parallel shift post stress. The curves shift positively by approximately 1.21 V across the accumulation, depletion, and inversion regions, while the slope remains unchanged. This behavior implies that ΔV_it ≈ 0 in Equation (4), indicating that the degradation is dominated by ΔN_ot (fixed negative charges) located deep within the oxide bulk, which uniformly screens the gate field without affecting the interface potential distribution.

DUT A (Thick Oxide): Significant Stretch-out and Distortion. In sharp contrast, the thick-oxide device in Figure 2 displays complex degradation behaviors:

Severe Voltage Drift: A larger Vth shift (~1.66 V) is observed compared to DUT B.

C-V Stretch-out: A pronounced reduction in the slope is evident along the rising edge from depletion to inversion (indicated by the double arrow). According to Terman’s theory, this stretch-out is a signature of acceptor-like interface states, where the charging and discharging of defects delay the surface potential bending during the voltage sweep.

C_min Rise:

Notably, an anomalous increase in the minimum capacitance C_min is observed in the high-frequency C-V curves of the stressed thick-oxide devices. This phenomenon is distinct from the parallel voltage shift caused by bulk oxide traps N_ot, and is attributed to the generation of interface states Dit.

In the depletion and weak inversion regions, majority carriers (electrons) are repelled from the interface into the bulk, leaving a depletion region where their concentration is negligible. Consequently, the surface potential is determined by the response of minority carriers (holes). In wide-bandgap SiC, the thermal generation of minority carriers is intrinsically slow, typically leading to a deep depletion state with a low C_min. However, the stress-induced high density of interface states acts as efficient generation–recombination (G-R) centers. These traps facilitate the thermal generation of minority carriers, enabling them to form an inversion layer more rapidly. This enhanced supply of minority carriers limits the expansion of the maximum depletion width W_max and prevents the device from entering deep depletion, thereby resulting in the observed rise in C_min.

3.2. Time-Domain Perspective: Frequency Response and Defect Dynamics via I_g

To overcome the frequency limitations of C-V measurements, quasi-static I_g-V_GS spectrometry was employed. This technique acts as a low-pass filter for interface defect time constants (τ_it), enabling the decoupling of fast states from slow traps.

DUT A (Thick Oxide): The Frequency Filtering Effect. Comparing the C-V curves with the I_g curves in Figure 3a reveals a striking discrepancy. While the 1 MHz C-V measurement shows a massive drift (~1.66 V), the quasi-static I_g peak position remains almost unchanged (drift < 0.2 V).

This phenomenon confirms the presence of fast interface states. In high-frequency C-V tests, defects with capture times longer than the signal period (1 μs) appear frozen, causing a shift. However, during the ultra-slow I_g sweep (d_V/d_t << 1 V/s), these fast states have sufficient time to discharge as the gate voltage sweeps back from inversion. Consequently, the I_g peak, which reflects the instantaneous differential capacitance, shows no memory effect. This high-frequency-drift, low-frequency recovery signature confirms that DUT A degradation is driven by unstable dangling bonds rather than fixed deep traps.

DUT B (Thin Oxide): Time-Constant Independence. Conversely, DUT B exhibits a clear positive shift in the I_g peak as Figure 3b, consistent with the C-V results (~0.3 V). This indicates that the trapped charges have extremely long time constants (τ_trap >> 100 s), characteristic of Deep Oxide Traps. These charges remain trapped even during the slow quasi-static sweep, confirming a mechanism dominated by stable charge injection.

3.3. Microscopic Perspective: Transconductance Degradation and Carrier Scattering

To probe the physical integrity of the interface, the transconductance (g_m) was analyzed. In the linear region (low V_DS), g_m is proportional to the field-effect mobility (μ_FE):

$$g_m={\displaystyle \frac{\partial I_D}{\partial V_{GS}}}\approx {\displaystyle \frac{W}{L}}{C}_{ox}{\mu }_{FE}{V}_{DS}$$

(5)

DUT A (Thick Oxide): Enhanced Coulomb Scattering.

As shown in Figure 4a, the thick-oxide device exhibits a severe peak collapse phenomenon after stress. The peak transconductance (g_m,peak) degrades significantly from 0.137 S to 0.085 S, representing a ~38% reduction. According to Equation (5), this sharp decline directly corresponds to a deterioration in channel mobility (μ_FE). The generation of interface states (N_it) near the conduction band edge acts as potent Coulomb scattering centers, which severely degrade carrier transport efficiency. This provides microscopic evidence that the SiC/SiO₂ interface in DUT A has undergone physical roughening and chemical bond breakage, consistent with the REDR mechanism triggered by high energetic carriers.

DUT B (Thin Oxide): Intact Interface Quality with Charge Trapping.

In stark contrast, the gm characteristics of the thin-oxide device as shown in Figure 4b display a rigid parallel shift without peak degradation. The entire curve shifts to the right, corresponding to the threshold voltage drift (ΔV_th) induced by electron trapping in the bulk oxide (N_ot). Crucially, the peak magnitude of gm remains stable (0.13 S to 0.16 S), indicating that the field-effect mobility is preserved. This behavior confirms that the trapped charges are located deep within the oxide (remote Coulomb scattering), where their scattering potential is screened by the distance. Consequently, the physical interface of the thin-oxide device remains atomically smooth and intact, effectively decoupling Vth instability from mobility degradation.

3.4. Recovery Characteristics: Thermodynamic Criteria for Permanent Damage

The permanence of the degradation provides the final criterion for distinguishing between electronic and chemical processes. Figure 5 plots the threshold voltage recovery over time, which typically follows a logarithmic law:

$$\mathrm{\Delta }{V}_{th}\left(t\right)=\mathrm{\Delta }{V}_{th}\left(t_0\right)-R·\log \left(1+{\displaystyle \frac{t}{{\tau }_0}}\right)\hspace{0.33em}$$

(6)

Prior to this, the Vth characteristics of the two devices under test (DUTs) before and after the tests are summarized in

Table 2. Device Vth variation.

Dut	Pre-Stress (V)	Post-Stress (V)	Post-Recovery (V)
A	3.05	5.428	5.3
B	2.908	3.57	3.44

below:

DUT B (Thin Oxide): Tunneling Detrapping. DUT B shows approximately 20% recovery, following the logarithmic trend of Equation (6). This is characteristic of tunneling detrapping, where electrons in shallow oxide traps tunnel back to the substrate.

DUT A (Thick Oxide): Irreversible Structural Damage. In contrast, DUT A exhibits a quasi-permanent drift with negligible recovery (<6%) over 10⁴ s. From a thermodynamic perspective, the Si-C bond energy is approximately 4.6 eV. The high driving voltage in thick-oxide devices provides sufficient kinetic energy for hot carriers to trigger electron–hole recombination at the SiC/SiO₂ interface. The released energy facilitates the Recombination-Enhanced Defect Reaction (REDR), which breaks the Si-C bonds and transforms near-interface vacancy precursors (such as oxygen vacancies or carbon interstitials) into electrically active interface states. Unlike simple charge trapping in bulk oxide traps, repairing these bond-breaking defects requires high activation energies (>1.5 eV), making spontaneous structural recovery impossible at room temperature. Consequently, the interface states remain active, leading to the irreversible Vth drift observed in DUT A.

Although this study employs a single iso-electric field stress condition (~5.5 MV/cm), the intrinsic correlation between the driving voltage and the REDR activation energy can be quantitatively established through a thermodynamic threshold analysis. The generation of interface defects via REDR is governed by an effective activation energy E_a,eff, which is dynamically modulated by the driving voltage according to the established REDR theory [22]. According to this well-established solid-state physics model, which has been successfully applied to state-of-the-art SiC MOSFET dynamic reliability studies [23], the generation of interface defects is governed by an effective activation energy ($E_{a,eff}$). This barrier is dynamically lowered by the non-radiative recombination process triggered during the switching transients, as expressed in Equation (7):

$$E_{a,eff}=E_{a,int}-E_{rec}\left(V_{GS}\right)$$

(7)

where E_a,int represents the intrinsic energy barrier required to dissociate strained near-interface precursor bonds (theoretically reported to be in the range of 1.5 eV to 2.5 eV for Si-C/Si-O networks [24]). E_rec(V_GS) is the excess energy released from the non-radiative electron–hole recombination, which is directly supplied by the electrical driving force.

In the thick-oxide device (DUT A), the high absolute driving voltage (V_GS = 22 V) drives significant carrier injection. When these carriers undergo non-radiative recombination at interface defect centers, the localized energy dissipated via multi-phonon emission is bounded by the 4H-SiC bandgap (~3.26 eV). Because this voltage-supplied recombination energy strictly exceeds the required intrinsic dissociation barrier ($E_{rec}\approx 3.26 \mathrm{eV}>E_{a,int}\approx 2.5 \mathrm{eV}$), the effective activation energy is reduced to near zero ($E_{a,eff}\le 0$).

Consequently, the applied 22 V driving voltage serves as a sufficient thermodynamic trigger. This strict energy correlation explains the severe and irreversible generation of interface states observed in the thick-oxide device without the need for multi-voltage kinetic fitting. In contrast, the thin-oxide device (DUT B), despite operating under the same macroscopic electric field, features a lower absolute driving voltage (19 V) and different tunneling dynamics (e.g., increased ballistic tunneling), which yields an insufficient $E_{rec}$ to overcome $E_{a,int}$, thereby suppressing the REDR mechanism.

4. Discussion

Based on the four-dimensional experimental evidence, we propose a bifurcated mechanism model for AC BTI in SiC MOSFETs governed by gate oxide thickness. This bifurcation can be explained by the interplay between the electric field and the absolute carrier energy.

Thick-Oxide Regime (REDR-Dominated):

Although the electric field Eox was kept constant in our experiments, the thicker oxide necessitates a significantly higher absolute gate driving voltage V_GS. According to the Lucky Electron Model, the probability of channel carriers gaining sufficient kinetic energy to trigger bond dissociation scales with the total potential drop across the inversion layer and oxide transition region.

The higher V_GS in thick-oxide devices imparts higher kinetic energy to carriers (hot carriers), enabling them to overcome the activation energy (E_a~1.5 eV) required for breaking Si-C or Si-H bonds. Upon non-radiative recombination at the interface, this energy is released, triggering the defect reaction:

$$\mathrm{Si-C}+\left(e^{-}+h^{+}\right)\to \mathrm{Sidangling}+\mathrm{Cinterstitial}$$

(8)

The resulting dangling bonds (Si_dangling) manifest as fast interface states, causing the observed C-V stretch-out and severe mobility degradation.

Thin-Oxide Regime (Trapping-Dominated):

In contrast, at lower absolute driving voltages (typical for thin-oxide devices), the carrier energy distribution is confined to lower levels, which are insufficient to trigger widespread bond breaking. The degradation is instead governed by Fowler–Nordheim (F-N) tunneling:

To verify the carrier transport mechanism under high electric fields, the theoretical gate leakage current density (J) was analyzed using the Fowler–Nordheim (F-N) tunneling model [25]:

$$J_{FN}={\displaystyle \frac{q^{3}m{E}^2}{8\pi h{\mathrm{\Phi }}_B{m}^{\ast }}}\exp \left(-{\displaystyle \frac{8\pi \sqrt{2m^{\ast }}{\mathrm{\Phi }}_B^{3/2}}{3qhE}}\right)$$

(9)

Due to the strict 30 V non-destructive measurement limit implemented to preserve the devices for the subsequent AC BTI dynamic stress, the full linear F-N tunneling regime was not completely swept. However, the distinct onset of F-N injection observed at the highest applied field boundary ($E_{ox}>6.3$ MV/cm) visually confirms the exceptional initial quality and low pre-existing trap density of the gate oxide.

To ensure absolute theoretical rigor in our physical analysis, rather than employing an empirical extrapolation from this restricted voltage range, the effective tunneling barrier height at the 4H-SiC/SiO₂ interface was adopted directly from established literature [24] as the ideal theoretical baseline (${\mathsf{\Phi }}_B=2.70 \mathrm{eV}$). Other physical parameters are defined as standard constants: $q$ is the elementary charge, $h$ is Planck’s constant, and the effective tunneling electron mass in SiO₂ is $m^{*}=0.52m_0$.

The electric field across the oxide is approximated as $E=V_{GS}/t_{ox}$. To ensure a fair comparison, the dynamic stress voltages were adjusted to maintain a constant peak electric field of approximately 5.5 MV/cm for both devices ($V_{GS}=+22 \mathrm{V}$ for the 40 nm thick-oxide device and +19 V for the 35 nm thin-oxide device). This iso-field condition confirms that the observed degradation is driven by high-field carrier injection mechanisms, perfectly aligning with the theoretical F-N baseline.

Engineering Implications:

These findings have critical implications for the design of reliable high-voltage SiC power devices.

For Device Design: Simply scaling the oxide thickness to limit the electric field (Eox) is insufficient to guarantee reliability. For thick-oxide devices, the quality of the interface passivation (e.g., via NO or POCl3 annealing) is the life-limiting factor.

For Gate Driving: To mitigate REDR in thick-oxide MOSFETs, gate driver designs should avoid excessive positive overdrive voltages.

For Lifetime Modeling: Reliability models must account for the transition from trapping-dominated to interface-degradation-dominated regimes as the voltage rating increases.

5. Conclusions

In this work, the impact of gate oxide thickness on the AC BTI reliability of 4H-SiC MOSFETs was systematically investigated. By employing a constant electric field dynamic stress methodology and a multi-dimensional characterization suite (C-V, I_GS, g_m, and recovery analysis), we successfully decoupled the competitive relationship between charge trapping and interface state generation. The principal conclusions of this study are summarized as follows:

Mechanism Bifurcation: We demonstrated that gate oxide thickness acts as a critical switch for AC BTI degradation mechanisms. Under identical electric field stress (E_ox), thin-oxide devices are dominated by reversible deep-level charge trapping (charge trapping model), whereas thick-oxide devices are dominated by irreversible interface state generation (REDR model).

Thin-Oxide Characteristics: Devices with thinner oxides exhibited a rigid parallel shift in C-V curves, a distinct shift in I_GS peaks, and stable transconductance (g_m). This indicates that the degradation is driven by electron tunneling into pre-existing bulk oxide traps, with the physical SiC/SiO₂ interface remaining intact.

Thick-Oxide Characteristics: Devices with thicker oxides showed severe C-V stretch-out, negligible shifts in I_GS peaks (indicating fast states), and significant mobility degradation (19.7% drop in g_m). This provides strong evidence that the higher absolute driving voltage required for thick oxides imparts sufficient kinetic energy to carriers to trigger Si-C bond dissociation via the REDR mechanism. This process generates coupled interface-region structural vacancies and fast interface states, where the irreversibility of the former prevents the recovery of the latter, leading to permanent structural damage.

Design Implications: These findings challenge the conventional assumption that thicker oxides inherently offer better reliability. For high-voltage SiC MOSFETs employing thick oxides, reliability is limited by the interface bond strength rather than dielectric breakdown. Consequently, optimizing interface passivation processes (e.g., advanced nitridation) is more critical for high-voltage devices than for their low-voltage counterparts.

While this study successfully isolates the impact of gate oxide thickness at a fixed frequency of 150 kHz, it is crucial to acknowledge that the switching frequency also plays a significant role in the overall AC BTI degradation of SiC MOSFETs. Recent studies have demonstrated that AC BTI is highly frequency-dependent [10,26,27]. On one hand, higher frequencies reduce the duration of the steady-state stress per cycle, which alters the charge trapping and emission dynamics in pre-existing oxide traps. On the other hand, recent studies have highlighted that AC BTI mechanisms are strongly modulated by dynamic switching operations, exhibiting distinct threshold voltage drift behaviors compared to static DC stress [28]. An increased switching frequency results in a higher number of transient switching edges ($d{V}_{GS}/dt$) per second. This frequent switching can accumulate massive transient displacement currents and non-equilibrium hot-carrier injections, which may further accelerate the Recombination-Enhanced Defect Reaction (REDR) and lead to more severe irreversible interface damage. Therefore, the coupled effects of gate oxide thickness and variable switching frequencies warrant further systematic investigation in future work.

In summary, this study provides a physical basis for geometry-dependent lifetime prediction models. Future work will focus on the temperature dependence of this mechanism bifurcation to further refine the activation energy models for interface dissociation.