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13 pages, 5421 KB

Open AccessArticle

A 326,000 fps 640 × 480 Resolution Continuous-Mode Ultra-High-Speed Global Shutter CMOS BSI Imager

by Jean-Luc Bacq, Mandar Thite, Roeland Vandebriel, Swaraj Bandhu Mahato, Philippe Coppejans, Jonathan Borremans, Linkun Wu, Kuba Rączkowski, Ismail Cevik, Vasyl Motsnyi, Luc Haspeslagh, Andreas Suess, Brandon Flon, Dan Jantzen, Phil Jantzen, Celso Cavaco and Annachiara Spagnolo

Sensors 2025, 25(23), 7372; https://doi.org/10.3390/s25237372 - 4 Dec 2025

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Abstract

This paper describes an ultra-high-speed monolithic global shutter CMOS image sensor capable of continuous motion capture at 326,000 fps with a resolution of 640 × 480 pixels. The performance is enabled by a novel combination of pixel technology and circuit techniques. The highly [...] Read more.

This paper describes an ultra-high-speed monolithic global shutter CMOS image sensor capable of continuous motion capture at 326,000 fps with a resolution of 640 × 480 pixels. The performance is enabled by a novel combination of pixel technology and circuit techniques. The highly sensitive BSI pixel with a 52 μm pitch employs a fully depleted substrate to facilitate rapid photocarrier transport. In-pixel voltage mode storage enables pipelined readout, while in-pixel analog CDS provides low noise with minimal impact on readout speed. The sensor achieves an equivalent row time of 6.4 ns through separate top and bottom readout together with multiple parallel ADCs per column. Independent row drivers on both the left and right sides ensure the global shutter accuracy needed for the minimum exposure time of 59 ns. The dynamic range is enhanced by on-chip reduction in FPN and by PTC-based data compression. The sensor delivers a throughput of 100 Gpix/sec, transferred off chip via 128 CML channels operating at 6.6 Gbps each. The device is fabricated using a 130 nm monolithic CIS process with BSI postprocessing and is in series production. Full article

(This article belongs to the Special Issue Special Issue on the 2025 International Image Sensor Workshop (IISW2025))

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12 pages, 3446 KB

Open AccessArticle

Wide-Dynamic-Range Lead-Free SWIR Image Sensors Based on InAs Thin-Film Quantum-Dot Photodiodes ^†

by Myonglae Chu, Wenya Song, Joo Hyoung Kim, Tristan Weydts, Vladimir Pejovic, Jiwon Lee, Minhyun Jin, Sang Yeon Lee, Yoora Seo, Hyunyoung Yoo, Jonas Bentell, Abu Bakar Siddik, Isabel Pintor Monroy, Marina Vildanova, Arman Uz Zaman, Tae Jin Yoo, Antonia Malainou, Wagdy Hussein, Annachiara Spagnolo, Gauri Karve, Itai Lieberman, Stefano Guerrieri and Pawel E. Malinowski Show full author list Hide full author list

Sensors 2025, 25(23), 7345; https://doi.org/10.3390/s25237345 - 2 Dec 2025

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Abstract

This work presents a monolithically integrated short-wavelength infrared (SWIR) image sensor based on indium arsenide (InAs) quantum dot photodiodes (QDPDs). The thin-film photodiode (TFPD) architecture enables direct integration on silicon readout integrated circuits (ROICs), eliminating wafer-to-wafer bonding and providing a scalable, RoHS-compliant alternative [...] Read more.

This work presents a monolithically integrated short-wavelength infrared (SWIR) image sensor based on indium arsenide (InAs) quantum dot photodiodes (QDPDs). The thin-film photodiode (TFPD) architecture enables direct integration on silicon readout integrated circuits (ROICs), eliminating wafer-to-wafer bonding and providing a scalable, RoHS-compliant alternative to lead-based colloidal quantum dot (CQD) devices. The proposed 3T pixel design incorporates dual conversion gain (DCG), enabling wide dynamic range imaging. The fabricated prototype achieves external quantum efficiencies of 28% at 1200 nm and 4.8% at 1400 nm, together with a dynamic range of 83.5 dB. A frame-based digital correlated double sampling (CDS) scheme stores the reset level in the digital domain and subtracts it after integration, thereby suppressing reset kTC noise and mitigating random telegraph signal (RTS) noise. Imaging demonstrations highlight SWIR-specific functionalities, including material discrimination, imaging through smoke, and transmission through silicon wafers. A performance comparison with previously reported SWIR pixels further confirms the competitiveness of the proposed InAs QDPD imager. These results establish InAs QDPDs as a promising platform for next-generation SWIR imaging, combining high sensitivity, extended spectral coverage, and scalable integration. Full article

(This article belongs to the Special Issue Special Issue on the 2025 International Image Sensor Workshop (IISW2025))

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11 pages, 3368 KB

Open AccessArticle

Charge-Domain Type 2.2 µm BSI Global Shutter Pixel with Dual-Depth DTI Produced by Thick-Film Epitaxial Process

by Toshifumi Yokoyama, Masafumi Tsutsui, Yoshiaki Nishi, Yoshihiro Noguchi, Masahiko Takeuchi, Masahiro Oda and Fenigstein Amos

Sensors 2025, 25(22), 6997; https://doi.org/10.3390/s25226997 - 16 Nov 2025

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Abstract

We developed a 2.2 µm backside-illuminated (BSI) global shutter (GS) pixel featuring true charge-domain-correlated double sampling (CDS). To enhance the inverse parasitic light sensitivity (1/PLS), we implemented a thick-film epitaxial process incorporating a dual-depth deep trench isolation (DTI) structure. The thickness of the [...] Read more.

We developed a 2.2 µm backside-illuminated (BSI) global shutter (GS) pixel featuring true charge-domain-correlated double sampling (CDS). To enhance the inverse parasitic light sensitivity (1/PLS), we implemented a thick-film epitaxial process incorporating a dual-depth deep trench isolation (DTI) structure. The thickness of the epitaxial substrate was 8.5 µm. This structure was designed using optical simulation. By using a thick epitaxial substrate, it is possible to reduce the amount of light that reaches the memory node. The dual-depth DTI design, with a shallower trench on the readout side, enables efficient signal transfer from the photodiode (PD) to the memory node. To achieve this structure, we developed a process for thick epitaxial substrate, and the dual-depth DTI can be fabricated with a single mask. This pixel represents the smallest charge-domain GS pixel developed to date. Despite its compact size, it achieves a high quantum efficiency (QE) of 83% (monochrome sample: wavelength = 560 nm) and a 1/PLS exceeding 10,000 (white halogen lamp with IR-cut filter). The pixel retains 80% of its peak QE at ±15° incident angles and maintains stable 1/PLS performance even under low F-number (F#) conditions. Full article

(This article belongs to the Special Issue Special Issue on the 2025 International Image Sensor Workshop (IISW2025))

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11 pages, 2345 KB

Open AccessArticle

Operation Under High Ionizing Dose Rates of Gamma or X-Ray Radiation of a 10 µm Radiation Tolerant Global Shutter Pixel

by Pedro Santos, Idham Hafizh, Paul Leroux and Guy Meynants

Sensors 2025, 25(22), 6979; https://doi.org/10.3390/s25226979 - 14 Nov 2025

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Abstract

A 10 × 10 µm² radiation-tolerant voltage-domain global shutter pixel with radiation-hardened by design (RHBD) device modification is developed to operate under high ionizing-dose rates and high total ionizing-dose (TID) levels. Therefore, a modified NMOS transistor layout is used in the pixel [...] Read more.

A 10 × 10 µm² radiation-tolerant voltage-domain global shutter pixel with radiation-hardened by design (RHBD) device modification is developed to operate under high ionizing-dose rates and high total ionizing-dose (TID) levels. Therefore, a modified NMOS transistor layout is used in the pixel to achieve radiation hardness. The pixel design is demonstrated to operate up to 1 MGy or 100 Mrad (SiO₂) TID with minimal degradation. The global shutter pixel also includes correlated double sampling (CDS) to reduce noise and the impact of the collected carriers generated by the flux of gamma or X-ray radiation. Combined with an external flash, global shutter operation allows short exposures, which limits the impact of radiation on dark current and dynamic range. The pixel is designed using 180 nm CMOS Image Sensor (CIS) technology. Full article

(This article belongs to the Special Issue Special Issue on the 2025 International Image Sensor Workshop (IISW2025))

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20 pages, 6888 KB

Open AccessArticle

Performance Characterization and Tuning of a Charge-Splitting High Dynamic Range 4-Tap CMOS Image Sensor

by Yu Feng, Keiichiro Kagawa, Kamel Mars, Keita Yasutomi and Shoji Kawahito

Sensors 2025, 25(22), 6953; https://doi.org/10.3390/s25226953 - 13 Nov 2025

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Abstract

Single-exposure high dynamic range (HDR) imaging is critical for applications such as automotive and surveillance cameras, where motion artifacts and light emitting diode (LED) flicker are significant challenges. Charge-splitting HDR imaging using multi-tap complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) effectively mitigates these issues [...] Read more.

Single-exposure high dynamic range (HDR) imaging is critical for applications such as automotive and surveillance cameras, where motion artifacts and light emitting diode (LED) flicker are significant challenges. Charge-splitting HDR imaging using multi-tap complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) effectively mitigates these issues and offers programmable dynamic range extension, demonstrating significant potential for such applications. In this work, we present a model to describe the performance of the charge-splitting pixel. Then, we experimentally characterize and tune the performance of a 4-tap CIS. Through performance tuning, the image sensor achieves a single-exposure dynamic range (DR) of 126 dB. This represents an improvement of 16 dB over the previously reported 110 dB while maintaining a high signal-to-noise ratio (SNR), with a minimum transition SNR exceeding 30 dB. Full article

(This article belongs to the Special Issue Special Issue on the 2025 International Image Sensor Workshop (IISW2025))

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27 pages, 5439 KB

Open AccessArticle

320 × 240 SPAD Direct Time-of-Flight Image Sensor and Camera Based on In-Pixel Correlation and Switched-Capacitor Averaging

by Maarten Kuijk, Ayman Morsy, Thomas Lapauw, Thomas Van den Dries, Wannes Nevens, Mohamed A. Bounouar, Hans Ingelberts and Daniel Van Nieuwenhove

Sensors 2025, 25(21), 6772; https://doi.org/10.3390/s25216772 - 5 Nov 2025

Viewed by 802

Abstract

Correlation-Assisted Direct Time-of-Flight (CA-dToF) is demonstrated for the first time on a large 320 × 240-pixel SPAD array sensor that includes on-chip high-speed timing support circuitry. SPAD events are processed in-pixel, avoiding data communication over the array and/or storage bottlenecks. This is accomplished [...] Read more.

Correlation-Assisted Direct Time-of-Flight (CA-dToF) is demonstrated for the first time on a large 320 × 240-pixel SPAD array sensor that includes on-chip high-speed timing support circuitry. SPAD events are processed in-pixel, avoiding data communication over the array and/or storage bottlenecks. This is accomplished by sampling two orthogonal triangle waves that are synchronized with short light pulses illuminating the scene. Using small switched-capacitor circuits, exponential moving averaging (EMA) is applied to the sampled voltages, delivering two analog voltages (VQ2, VI2). These contain the phase delay, or the time of flight between the light pulse and photon’s time of arrival (ToA). Uncorrelated ambient photons and dark counts are averaged out, leaving only their associated shot noise impacting the phase precision. The QVGA camera allows for capturing depth-sense images with sub-cm precision over a 6 m range of detection, even with a small PDE of 0.7% at an 850 nm wavelength. Full article

(This article belongs to the Special Issue Special Issue on the 2025 International Image Sensor Workshop (IISW2025))

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14 pages, 7476 KB

Open AccessArticle

Development of 3D-Stacked 1Megapixel Dual-Time-Gated SPAD Image Sensor with Simultaneous Dual Image Output Architecture for Efficient Sensor Fusion

by Kazuma Chida, Kazuhiro Morimoto, Naoki Isoda, Hiroshi Sekine, Tomoya Sasago, Yu Maehashi, Satoru Mikajiri, Kenzo Tojima, Mahito Shinohara, Ayman T. Abdelghafar, Hiroyuki Tsuchiya, Kazuma Inoue, Satoshi Omodani, Alice Ehara, Junji Iwata, Tetsuya Itano, Yasushi Matsuno, Katsuhito Sakurai and Takeshi Ichikawa

Sensors 2025, 25(21), 6563; https://doi.org/10.3390/s25216563 - 24 Oct 2025

Cited by 1 | Viewed by 791

Abstract

Sensor fusion is crucial in numerous imaging and sensing applications. Integrating data from multiple sensors with different field-of-view, resolution, and frame timing poses substantial computational overhead. Time-gated single-photon avalanche diode (SPAD) image sensors have been developed to support multiple sensing modalities and mitigate [...] Read more.

Sensor fusion is crucial in numerous imaging and sensing applications. Integrating data from multiple sensors with different field-of-view, resolution, and frame timing poses substantial computational overhead. Time-gated single-photon avalanche diode (SPAD) image sensors have been developed to support multiple sensing modalities and mitigate this issue, but mismatched frame timing remains a challenge. Dual-time-gated SPAD image sensors, which can capture dual images simultaneously, have also been developed. However, the reported sensors suffered from medium-to-large pixel pitch, limited resolution, and inability to independently control the exposure time of the dual images, which restricts their applicability. In this paper, we introduce a 5 µm-pitch, 3D-backside-illuminated (BSI) 1Megapixel dual-time-gated SPAD image sensor enabling a simultaneous output of dual images. The developed SPAD image sensor is verified to operate as an RGB-Depth (RGB-D) sensor without complex image alignment. In addition, a novel high dynamic range (HDR) technique, utilizing pileup effect with two parallel in-pixel memories, is validated for dynamic range extension in 2D imaging, achieving a dynamic range of 119.5 dB. The proposed architecture provides dual image output with the same field-of-view, resolution, and frame timing, and is promising for efficient sensor fusion. Full article

(This article belongs to the Special Issue Special Issue on the 2025 International Image Sensor Workshop (IISW2025))

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Review

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31 pages, 5331 KB

Open AccessReview

Spiking Neural Networks in Imaging: A Review and Case Study

by Michael Voudaskas, Jack Iain MacLean, Neale A. W. Dutton, Brian D. Stewart and Istvan Gyongy

Sensors 2025, 25(21), 6747; https://doi.org/10.3390/s25216747 - 4 Nov 2025

Viewed by 2130

Abstract

This review examines the state of spiking neural networks (SNNs) for imaging, combining a structured literature survey, a comparative meta-analysis of reported datasets, training strategies, hardware platforms, and applications and a case study on LMU-based depth estimation in direct Time-of-Flight (dToF) imaging. While [...] Read more.

This review examines the state of spiking neural networks (SNNs) for imaging, combining a structured literature survey, a comparative meta-analysis of reported datasets, training strategies, hardware platforms, and applications and a case study on LMU-based depth estimation in direct Time-of-Flight (dToF) imaging. While SNNs demonstrate promise for energy-efficient, event-driven computation, current progress is constrained by reliance on small or custom datasets, ANN-SNN conversion inefficiencies, simulation-based hardware evaluation, and a narrow focus on classification tasks. The analysis highlights scaling trade-offs between accuracy and efficiency, persistent latency bottlenecks, and limited sensor–hardware integration. These findings were synthesised into key challenges and future directions, emphasising benchmarks, hardware-aware training, ecosystem development, and broader application domains. Full article

(This article belongs to the Special Issue Special Issue on the 2025 International Image Sensor Workshop (IISW2025))

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