Search Results (106)

Efficient metadata and page management are essential for sustaining database performance on modern flash-based storage. However, conventional SQLite configurations—rollback journal and WAL—often trigger excessive small writes and frequent synchronization events, leading to high write amplification and degraded tail latency, particularly on UFS and NVMe devices. This study introduces ALEX (Adaptive Log-Embedded Extent Layer), a lightweight VFS-level extension that coalesces scattered 4 KB page updates into sequential, page-aligned extents while embedding compact log records for recovery. The proposed design reduces redundant writes through in-memory page deduplication, minimizes fdatasync()frequency by flushing multi-page extents, and preserves full SQLite compatibility. We evaluate ALEX on both Linux NVMe SSDs and Android UFS storage under controlled workloads. Results show that ALEX significantly lowers write amplification, reduces sync counts, and improves p95–p99 write latency compared with baseline SQLite modes. The approach consistently achieves near-sequential write patterns without modifying SQLite internals. These findings demonstrate that lightweight extent-based coalescing can provide substantial efficiency gains for embedded and mobile database systems, offering a practical direction for enhancing SQLite performance on flash devices. Full article

Recently, the record-level rise in Internet of Things (IoT) devices has produced unparalleled security challenges, particularly for resource-constrained devices operating under limited computational resources, memory, and power. In this context, traditional cryptographic methods not only fail but are also expensive and require extensive resources, given their static nature. In this article, an Adaptive Hybrid Cryptographic Framework (AHCF) is proposed to address the security challenges of resource-constrained IoT devices by adaptively balancing performance and protection levels, which can adaptively adjust cryptographic parameters based on the state of the device at a given time under a specific network environment and security needs. It also effectively balances security level and resource usage and employs low-overhead asymmetric key management with lightweight symmetric cryptography and machine learning-based predictors for the optimal selection of encryption schemes. Experimental testing on multiple IoT platforms has demonstrated its significant benefits, namely 42% less energy consumption, a 38% increase in processor speed, and improved security responsiveness over static deployments. This solution can be applied on boards with as little as 2 KB RAM and 16 KB flash and outperforms existing IoT standards and protocols. Full article

The trend of decreasing endurance of flash memory makes the overall lifetime of SSDs more sensitive to the effects of wear leveling. Under these circumstances, we observe that existing wear-leveling techniques exhibit anomalous behavior under workloads without clear access skew or under dynamic access patterns and produce high write amplification, as high as 5.4×, negating its intended benefits. We argue that wear leveling is an artifact for maintaining the fixed-capacity abstraction of a storage device, and it becomes unnecessary if the exported capacity of the SSD is to gracefully reduce. We show that this idea of capacity variance extends the lifetime of the SSD, allowing up to 2.94× more writes under real workloads. Full article

Intelligent sensing systems are increasingly used in wearable devices, enabling advanced tasks across various application domains including robotics and human–machine interaction. Ensuring these systems are energy autonomous is highly demanded, despite strict constraints on power, memory and processing resources. To meet these requirements, embedded neural networks must be optimized to achieve a balance between accuracy and efficiency. This paper presents an integrated approach that combines Hardware-Aware Neural Architecture Search (HW-NAS) with optimization techniques—weight reshaping, quantization, and their combination—to develop efficient classifiers for a multisensory glove. HW-NAS automatically derives 1D-CNN models tailored to the NUCLEO-F401RE board, while the additional optimization further reduces model size, memory usage, and latency. Across three datasets, the optimized models not only improve classification accuracy but also deliver an average reduction of 75% in inference time, 69% in flash memory, and more than 45% in RAM compared to NAS-only baselines. These results highlight the effectiveness of integrating NAS with optimization techniques, paving the way towards energy-autonomous wearable systems. Full article

As the CMOS technology approaches its physical and economic limits, further advancement of Moore’s Law for enhanced computing performance can no longer rely solely on smaller transistors and higher integration density. Instead, the computing landscape is poised for a fundamental transformation that transcends hardware scaling to embrace innovations in architecture, software, application-specific algorithms, and cross-disciplinary integration. Among the most promising enablers of this transition is non-volatile memory (NVM), which provides new technological pathways for restructuring the future of computing systems. Recent advancements in non-volatile memory (NVM) technologies, such as flash memory, Resistive Random-Access Memory (RRAM), and magneto-resistive RAM (MRAM), have significantly narrowed longstanding performance gaps while introducing transformative capabilities, including instant-on functionality, ultra-low standby power, and persistent data retention. These characteristics pave the way for developing more energy-efficient computing systems, heterogeneous memory hierarchies, and novel computational paradigms, such as in-memory and neuromorphic computing. Beyond isolated hardware improvements, integrating NVM at both the architectural and algorithmic levels would foster the emergence of intelligent computing platforms that transcend the limitations of traditional von Neumann architectures and device scaling. Driven by these advances, next-generation computing platforms powered by NVM are expected to deliver substantial gains in computational performance, energy efficiency, and scalability of the emerging data-centric architectures. These improvements align with the broader vision of both “More Moore” and “More than Moore”—extending beyond MOS device miniaturization to encompass architectural and functional innovation that redefines how performance is achieved at the end of CMOS device downsizing. Full article

This paper presents a framework that enables programmers to deploy embedded real-time firmware of Internet of Things (IoT) devices more conveniently than using plain C/C++-language programming, by abstracting away from low-level details and the ad hoc management of multiple, diverse network technologies. Moreover, unlike other proposals, the framework is able to accommodate both time and event-driven applications. Experimental results show that for Modbus-CAN communication, the worst-case time overhead of the framework is less than 6% of the total combined processing and communication time. Its memory requirement is less than 5% and 4% of the Flash memory and RAM available on a typical IoT microcontroller. The framework also compares favorably with respect to two other approaches in terms of the sustainable minimum cycle time, memory overhead, and level of programming abstraction when tested on a simple real-time algorithm. Full article

The accurate real-time estimation of the remaining useful life (RUL) of lithium-polymer (LiPo) batteries is a critical enabler for ensuring the safety, reliability, and operational efficiency of unmanned aerial vehicles (UAVs). Nevertheless, achieving such prognostics on resource-constrained embedded platforms remains a considerable technical challenge. This study proposes an end-to-end TinyML-based framework that integrates embedded sensor data fusion with an optimized feedforward neural network (FFNN) model for efficient RUL estimation under strict hardware limitations. The system collects voltage, discharge time, and capacity measurements through a lightweight data fusion pipeline and leverages the Edge Impulse platform with the EON™Compiler for model optimization. The trained model is deployed on a dual-core ARM Cortex-M0+ Raspberry Pi RP2040 microcontroller, communicating wirelessly with a LabVIEW-based visualization system for real-time monitoring. Experimental validation on an 80-gram UAV equipped with a 1100 mAh LiPo battery demonstrates a mean absolute error (MAE) of 3.46 cycles and a root mean squared error (RMSE) of 3.75 cycles. Model testing results show an overall accuracy of $98.82\%$, with a mean squared error (MSE) of 55.68, a mean absolute error (MAE) of 5.38, and a variance score of 0.99, indicating strong regression precision and robustness. Furthermore, the quantized (int8) version of the model achieves an inference latency of 2 ms, with memory utilization of only 1.2 KB RAM and 11 KB flash, confirming its suitability for real-time deployment on resource-constrained embedded devices. Overall, the proposed framework effectively demonstrates the feasibility of combining embedded sensor data fusion and TinyML to enable accurate, low-latency, and resource-efficient real-time RUL estimation for UAV battery health management. Full article

In this study, we propose a neuromorphic computing system based on a 3D-NAND flash architecture that utilizes analog input voltages applied through wordlines (WLs). The approach leverages the velocity saturation effect in short-channel MOSFETs, which enables a linear increase in drain current with respect to gate voltage in the saturation region. A NAND flash array with a TANOS (TiN/Al₂O₃/Si₃N₄/SiO₂/poly-Si) gate stack was fabricated, and its electrical and reliability characteristics were evaluated. Output characteristics of short-channel (L = 1 µm) and long-channel (L = 50 µm) devices were compared, confirming the linear behavior of short-channel devices due to velocity saturation. In the proposed system, analog WL voltages serve as inputs, and the summed bitline (BL) currents represent the outputs. Each synaptic weight is implemented using two paired devices, and each WL layer corresponds to a fully connected (FC) layer, enabling efficient vector-matrix multiplication (VMM). MNIST pattern recognition is conducted, demonstrated only a 0.32% accuracy drop for the short-channel device compared to the ideal linear case, and 0.95% degradation under 0.5 V threshold variation, while maintaining robustness. These results highlight the strong potential of 3D-NAND flash memory, which offers high integration density and technological maturity, for neuromorphic computing applications. Full article

As a critical storage technology, the material selection and structural design of flash memory devices are pivotal to their storage density and operational characteristics. Although van der Waals materials can potentially take over the scaling roadmap of silicon-based technologies, the scaling mechanisms and optimization principles at low-dimensional scales remain to be systematically unveiled. In this study, we experimentally demonstrated that the floating-gate length can significantly affect the memory window characteristics of memory devices. Experiments involving various floating-gate and tunneling-layer configurations, combined with TCAD simulations, were conducted to reveal the electrostatic coupling behaviors between floating gate and source/drain electrodes during shaping of the charge storage capabilities. Fundamental performance characteristics of the designed memory devices, including a large memory ratio (82.25%), good retention (>50,000 s, 8 states), and considerable endurance characteristics (>2000 cycles), further validate the role of floating-gate topological structures in manipulating low-dimensional memory devices, offering valuable insights to drive the development of next-generation memory technologies. Full article

Low-power embedded devices are widely used in sensor networks, monitoring systems, and industrial applications. These devices typically rely on internal flash memory, where storage is constrained by bootloaders, communication stacks, and other software. Adding external memory increases cost and energy consumption, making efficient memory utilization essential. This article presents key design concepts for developing an efficient, lightweight, and reliable embedded filesystem. It introduces an improved version of the configurable flash filesystem (CFFS), designed to maximize memory utilization, minimize flash wear, and support portability across hardware platforms and operating systems. Reliability mechanisms integrated into CFFS are also discussed. We compare CFFS with widely used low-power embedded filesystems—LittleFS, SPIFFS, and FDS—highlighting its advantages in memory efficiency and reduced flash memory wear. Experimental results demonstrate that CFFS achieves up to 99% memory utilization while significantly reducing erase operations. Full article

The bandgap-engineered tunneling oxide (BE-TOX) structure has been proposed to address the incompatibility between erase efficiency and retention performance in NAND flash memory. Previous studies have primarily focused on single flash memory cells, whose architecture significantly differs from that of 3D NAND flash memory. Thus, the BE-TOX structure requires further research and optimization to improve device performance. In this study, the impact of varying proportions of the SiO₂/SiO_xN_y/SiO₂ (O1/N/O2) structure on performance is investigated using Technology Computer-Aided Design (TCAD) simulations. The results indicate that as the thickness of the N layer increases, the program/erase (P/E) speed improves, but reliability deteriorates. By adjusting the ratio of the O1 and O2 layers, the P/E speed can be optimized, and an optimal thickness can be identified. The simulation results demonstrate that the phenomenon is attributed to the combined effects of different barrier heights for charge tunneling and variations in band bending across the material layers. This study paves the way for further designing BE-TOX structures with balanced P/E performance and reliability. Full article

Miniature robots in small-diameter pipelines require efficient and reliable environmental perception for autonomous navigation. In this paper, a tiny machine learning (TinyML)-based resource-efficient pipe feature recognition method is proposed for miniature robots to identify key pipeline features such as elbows, joints, and turns. The method leverages a custom five-layer convolutional neural network (CNN) optimized for deployment on a robot with limited computational and memory resources. Trained on a custom dataset of 4629 images collected under diverse conditions, the model achieved an accuracy of 97.1%. With a peak RAM usage of 195.1 kB, flash usage of 427.9 kB, and an inference time of 1693 ms, the method demonstrates high computational efficiency while ensuring stable performance under challenging conditions through a sliding window smoothing strategy. These results highlight the feasibility of deploying advanced machine learning models on resource-constrained devices, providing a cost-effective solution for autonomous in-pipe exploration and inspection. Full article

The demand for intelligent monitoring systems tailored to elderly living environments is rapidly increasing worldwide with population aging. Traditional acoustic scene monitoring systems that rely on cloud computing are limited by data transmission delays and privacy concerns. Hence, this study proposes an acoustic scene recognition system that integrates edge computing with deep learning to enable real-time monitoring of elderly individuals’ daily activities. The system consists of low-power edge devices equipped with multiple microphones, portable wearable components, and compact power modules, ensuring its seamless integration into the daily lives of the elderly. We developed four deep learning models—convolutional neural network, long short-term memory, bidirectional long short-term memory, and deep neural network—and used model quantization techniques to reduce the computational complexity and memory usage, thereby optimizing them to meet edge device constraints. The CNN model demonstrated superior performance compared to the other models, achieving 98.5% accuracy, an inference time of 2.4 ms, and low memory requirements (25.63 KB allocated for Flash and 5.15 KB for RAM). This architecture provides an efficient, reliable, and user-friendly solution for real-time acoustic scene monitoring in elderly care. Full article

The rapid expansion of data has made global access easier, but it also demands increasing amounts of energy for data storage and processing. In response, neuromorphic electronics, inspired by the functionality of biological neurons and synapses, have emerged as a growing area of research. These devices enable in-memory computing, helping to overcome the “von Neumann bottleneck”, a limitation caused by the separation of memory and processing units in traditional von Neumann architecture. By leveraging multi-bit non-volatility, biologically inspired features, and Ohm’s law, synaptic devices show great potential for reducing energy consumption in multiplication and accumulation operations. Within the various non-volatile memory technologies available, flash memory stands out as a highly competitive option for storing large volumes of data. This review highlights recent advancements in neuromorphic computing that utilize NOR, AND, and NAND flash memory. This review also delves into the array architecture, operational methods, and electrical properties of NOR, AND, and NAND flash memory, emphasizing its application in different neural network designs. By providing a detailed overview of flash memory-based neuromorphic computing, this review offers valuable insights into optimizing its use across diverse applications. Full article

In this work, we analyze the thermodynamic principles underlying modern data storage systems, including Random Access Memory (RAM), hard disk drive (HDD), flash memory, magnetic RAM (MRAM), ferroelectric RAM (FeRAM), and phase-change RAM (PCRAM), as well as other less well-known data storage mechanisms. The analysis is conducted in the context of data storage and processing in relation to Landauer’s principle, with special emphasis on hysteresis. Analogous to how heat engines are characterized by thermodynamic cycles, data storage systems are examined in terms of the hysteresis loop of their fundamental data unit. We explore the role of heat in data storage systems. Afterward, we introduce the concept of temperature gradient memory (TeGraM) along with a detailed layout of a realizable device. Experimental results demonstrating this technology are also presented. Full article