Search Results (47)

High Bandwidth Memory couples many DRAM dies to a host through independent channels, and a memory controller presents each channel to the workload as either available or isolated. This paper takes that binary service interface as the modeling primitive and builds a closed-form framework for evaluating stack and system behavior on top of it. Each die is treated as a binary component whose reliability is composed from DRAM, through-silicon via and micro-bump contributions, with the via bundle itself modeled as a threshold subsystem; the dies are then aggregated as a threshold structure over the stack, and stacks are aggregated over the system. The result is an evaluation whose cost grows linearly rather than exponentially with the number of dies, and which yields not only reliability but the full distribution of delivered bandwidth, its moments, and the sensitivity of system availability to each component. Three design questions are answered directly: where to direct reliability investment, how many stacks to provision for a given availability target, and which bandwidth threshold minimizes cost when bandwidth and reliability requirements are imposed together. The approximations the framework makes are bounded rather than assumed. A three-state baseline quantifies the error introduced by the binary representation and shows it is governed by a single measurable quantity, and distribution-free inequalities bound the effect of correlation among component failure mechanisms, which proves negligible in the regime where HBM parts are qualified. Application to a representative stack identifies DRAM cell reliability as the dominant bottleneck and shows that a single spare via per bundle is sufficient at typical defect rates. Full article

Conventional cooling schemes that rely on rigid heat-sink-to-die coupling in vertical stacks fail to track the dynamic, non-uniform heat map of high-performance artificial-intelligence (AI) chips employing chiplet-based heterogeneous integration, giving rise to local hot spots. To eliminate this mismatch, we present a leaf-vein-inspired fractal microchannel tailored for such AI processors. Its hierarchical bifurcation–confluence topology adaptively reshapes the flow field, delivering ultra-low thermal resistance, high heat-transfer coefficients, and uniform dissipation. Coupled with reconfigurable chiplet placement, the design is evaluated through FEM-based orthogonal experiments that rank the influence of coolant, channel diameter/depth, inlet/outlet position, substrate thickness, and flow rate via range analysis and Analysis of Variance (ANOVA). A machine-learned surrogate model of junction temperature is then fed to Particle Swarm Optimization (PSO) for multi-parameter optimization. When re-simulated with the optimal parameter set, the symmetric fractal network lowered the AI chip junction temperature from 127.80 °C to 30.97 °C, a 76% improvement, offering a theoretical basis for hotspot mitigation in advanced heterogeneous AI packages. Full article

Numerical simulations of the forming limit diagram (FLD) for SUS430/Al1050/TA1 laminated metal composites (LMCs) are conducted through the crystal plasticity finite element (CPFE) model integrated with the Marciniak–Kuczyński (M–K) theory. Representative volume elements (RVEs) that reconstruct the measured crystallographic texture, as characterized by electron backscatter diffraction (EBSD), are developed. The optimal grain number and mesh density for the RVE are calibrated through convergence analysis by curve-fitting simulated stress–strain responses to the uniaxial tensile data. The established multi-scale model successfully predicts the FLDs of the SUS430/Al1050/TA1 laminated sheet under two stacking sequences, namely, the SUS layer or the TA1 layer in contact with the die. The Nakazima test results validate the effectiveness of the proposed model as an efficient and accurate predictive tool. This study extends the CPFE–MK framework to multi-layer LMCs, overcoming the limitations of conventional single-layer models, which incorporate FCC, BCC, and HCP crystalline structures. Furthermore, the deformation-induced texture evolution under different loading paths is analyzed, establishing the relationship between micro-scale deformation mechanisms and the macro-scale forming behavior. Full article

This work presents a highly compact and scalable 1.2-kV SiC MOSFET half-bridge building-block module enabled by a die-integrated 3D PCB packaging technology. Compared with conventional DBC-based or TO-247-based SiC half-bridge modules, the proposed design reduces the physical volume and weight by more than 90% while maintaining full compatibility with standard PCB manufacturing processes. The vertically laminated DC+/DC− conductors and symmetric PCB–die–PCB stack establish a tightly confined commutation loop, resulting in a measured power-loop inductance of 2.2 nH and a 3.8 nH gate-loop inductance—representing up to 94% and 89% reduction relative to discrete device implementations. Because the parasitic parameters are intrinsically well-balanced across replicated units and the mutual inductance between adjacent modules remains extremely small, the structure naturally supports current sharing during parallel operation. Thermal and insulation evaluations further confirm the suitability of copper filling via high-Tg laminated PCB substrates for high-power SiC applications, achieving withstand voltages exceeding twice the rated bus voltage. The proposed module is experimentally validated through finite-element parasitic extraction and 950 V double-pulse testing, demonstrating controlled dv/dt behavior and robust switching performance. This work establishes a manufacturable and parallel-friendly packaging approach for high-density SiC power conversion systems. Full article

Microelectronic packaging is crucial for protecting, powering, and interconnecting semiconductor chips, playing a critical role in the functionality and reliability of electronic devices. With the growth in complexity and miniaturization of these products, the implementation of efficient inspection techniques becomes crucial in preventing failures that may result in device malfunctions. This review paper examines the progress made in utilizing Scanning Acoustic Microscopy (SAM) to assess the structural integrity of microelectronic systems within the broader field of Nondestructive Evaluation/Testing (NDE/T) methods. With an exclusive emphasis on SAM, we point out SAM technological advancements in multi-die stacking, Through Silicon Vias (TSV), and hybrid bonding inspection that improve inspection sensitivity and resolution required to be prepared for upcoming challenges accompanying 3D- and heterogeneous integration architectures. Some of these approaches compromise the depth of inspection for the benefit of lateral resolution, while others do not sacrifice the in-depth range of evaluation. These developments are of the utmost importance in addressing the substantial obstacles associated with examining microelectronic packages, facilitating the early detection of potential failures, and enhancing the reliability and robustness of semiconductor devices. Furthermore, our discussion consists of the fundamental principles and practical approaches of SAM. It also examines recent investigations that integrate SAM with machine learning concepts and the application of deep learning models in order to automate defect detection and characterization, thus substantially augmenting the efficiency of microelectronic package assessments. Full article

Current manufacturing trends in 3D integration are resulting in a notorious increase in power density, and the use of conventional cooling methods may not be sufficient for cooling future 3D ICs with several chip dies. Moreover, with very thin chip dies, implementing alternative cooling methods based on etching microchannels in every chip die may not be technologically feasible. In this study, we suggest implementing microchannels only in the top, unthinned layer of silicon. In this case, the crucial parameter influencing cooling efficiency is the thermal conductance between vertically stacked chip dies. Therefore, an extensive numerical study is conducted, which quantifies the thermal performance of such single-layer microchannel heat exchangers as a function of inter-die thermal conductance, in addition to other chip parameters. Several important conclusions are presented based on these analyses. In particular, for various 3D stacks, this study allows the determination of the concrete threshold values of inter-die thermal conductance relative to which thermal performance degradation starts to become significant. Full article

GH4706 Ni-based superalloy is widely used for aero-engine turbine disks operating below 700 °C, where high-temperature ductility is critical to avoid cracking during die forging and service. However, the microscopic mechanisms by which stabilization treatment regulates its high-temperature ductility remain insufficiently clarified. This study systematically investigated the tensile deformation behavior at a high temperature of 650 °C of the GH4706 Ni-based superalloy after stabilization treatment. Transmission electron microscopy (TEM) and secondary ion mass spectrometry (SIMS) were employed to characterize microstructural evolution and elemental redistribution to clarify the microscopic mechanisms by which stabilization treatment enhanced the high-temperature ductility of the GH4706 alloy. The experimental results indicated that better high-temperature plasticity was obtained, although tensile strength decreased slightly after stabilization. This improvement was mainly attributed to the precipitation of the η phase (Ni₃Ti) and its synergistic interaction with the matrix, which effectively enhanced the plastic deformation capacity of the GH4706 alloy at elevated temperatures. Moreover, η phase precipitation and elemental segregation enhanced grain boundary stability, thus inhibiting crack initiation and delaying necking. SIMS analysis revealed that boron, phosphorus, and sulfur showed significant segregation along grain boundaries during 650 °C tensile testing following stabilization—an effect considered crucial to the observed ductility enhancement. TEM observations further indicated that the interaction between η phase precipitation and the nucleation and evolution of stacking faults during deformation together reduced local stress concentrations and promoted uniform plastic deformation. Full article

2.5D integrated circuits (ICs), which utilize an interposer to stack multiple dies side by side, represent a promising architecture for improving system performance, integration density, and design flexibility. However, the complex interconnect structures present significant challenges for post-fabrication testing, especially when scheduling test paths under constrained test access mechanisms. This paper addresses the test-path scheduling problem in interposer-based 2.5D ICs, aiming to minimize both total test time and cumulative inter-die interconnect length. We propose an efficient orthogonal learning-based differential evolution algorithm, named OLELS-DE. The algorithm combines the global optimization capability of differential evolution with an orthogonal learning-based search strategy and an elites local search strategy to enhance the convergence and solution quality. Comprehensive experiments are conducted on a set of benchmark instances with varying die counts, and the proposed method is compared against five state-of-the-art metaheuristic algorithms and CPLEX. Experimental results demonstrate that OLELS-DE consistently outperforms the competitors in terms of test cost reduction and convergence reliability, confirming its robustness and effectiveness for complex test scheduling in 2.5D ICs. Full article

In this paper, a discrete element method (DEM) coupled with a finite element method (FEM) was used to elucidate the impact of packing structures and size ratios on the cold die compaction behavior of pure copper powders. HCP structure, SC structure, and three random packing structures with different particle size ratios (1:2, 1:3, and 1:4) were generated by the DEM, and then simulated by the FEM to analyze the average relative density, von Mises stress, and force chain structures of the compact. The results show that for HCP and SC structures with a regular stacking structure, the average relative densities of the compact were higher than those of random packing structures, which were 0.9823, 0.9693, 0.9456, 0.9502, and 0.9507, respectively. Compared with their initial packing density, it could be improved by up to 21.13%. For the bigger particle in HCP and SC structures, the stress concentration was located between the adjacent layers, while in the small particles, it was located between contacted particles. During the initial compaction phase, smaller particles tend to occupy the voids between larger particles. As the pressure increases, larger particles deform plastically in a notable way to create a stabilizing force chain. This action reduces the axial stress gradient and improves radial symmetry. The transition from a contact-dominated to a body-stress-dominated state is further demonstrated by stress distribution maps and contact force vector analysis, highlighting the interaction between particle rearrangement and plasticity. Full article

End plates are important multi-functional components of the fuel cells. They provide structural support and are responsible for channeling the reactant gases, by-product water, and fuel cell coolant in and out of the fuel cell stack. Among various materials used for end plates, aluminum alloy is used due to its high strength and low density. But its corrosion resistance depends on the environment. The operating fuel cell conditions may cause the fuel cell coolant to become more acidic or basic in nature and thus can lead to corrosion of end plates. In this work, a common die-cast aluminum alloy, AlSi10Mg(Fe), is used for end plates, and its corrosion behavior in direct contact with the fuel cell coolant is analyzed. The electrochemical characterization of uncoated and anodized aluminum alloy was achieved using electrochemical impedance spectroscopy, potentiodynamic and potentiostatic polarization tests at room temperature and at the operating temperature of the fuel cell at 80 °C. It was found that for the uncoated aluminum alloy, the corrosion sensitivity is slightly increased when the temperature increases. In comparison, the anodized aluminum alloy reveals a decrease in corrosion sensitivity after 100 h of potentiostatic control, indicating an ongoing passivation of the surface due to the formation of aluminum oxides/hydroxides and aluminum alcohol corrosion products. Full article

The drawability and microstructural homogeneity of twinning-induced plasticity (TWIP) steel were improved during the wire drawing process by utilizing a temperature gradient along the wire’s radial direction. The surface temperature of the wire increased by applying heat to the die during the drawing process, thereby creating a temperature gradient across the wire during wire drawing. The drawability of the wire subjected to the temperature gradient with warm die (WD) increased by approximately 33% compared to that of conventional wire drawing with cold die (CD). The higher temperature of about 300 °C at the surface region of the wire with the WD suppressed the twinning rate at the surface region owing to the increase in the stacking fault energy (SFE) from 34 to 55 mJ/m², leading to a uniform twinning rate along the wire’s radial direction compared with the CD wire, finally resulting in the improvement of the homogeneity in the microstructure and mechanical properties of TWIP steel. As a result, the drawability of the TWIP steel improved. Therefore, the general conclusion was derived that controlling the SFE within the area of the workpiece by tailoring the temperature can improve the formability in TWIP steels during the plastic forming process. Full article

Grains of commercially pure titanium (CP-Ti) can be refined via rotary-die equal-channel angular pressing (RD-ECAP) to meet higher application requirements. However, the grain refinement mechanism of CP-Ti during RD-ECAP has not been fully studied. Herein, CP-Ti was processed up to four passes by RD-ECAP to obtain an ultrafine-grained structure. The microstructure evolution, refinement mechanism, and dynamic recrystallization (DRX) behavior was investigated by TEM and EBSD analysis. The results revealed that after two passes, banded structures with numerous LAGBs inside were detected, while after four passes, most grains were equiaxed with HAGBs and the average grain size was about 0.5 μm. The fraction of HAGBs reached 78.6% for the four-pass sample, which was higher than that of two-pass sample. The fraction of deformed grains declined and the proportion of recrystallized grains increased as the pass number increased from two to four. The misorientation gradient analysis showed that subgrains with LAGBs evolved into new grains with HAGBs gradually to generate ultrafine grains. The refinement mechanism of CP-Ti during RD-ECAP can be concluded as continuous DRX (CDRX). In addition, the relationship between DRX type and the processing conditions as well as stacking fault energies (SFEs) of metals was innovatively explored, providing a new approach for predicting microstructure. Full article

In this study, we introduce a stagger-stacked DDR module that comprises one IPD chip (top die) along with four memory chips initially. The steady-state thermal characteristics of this configuration were empirically assessed using a dedicated thermal test vehicle. The purpose of this research is to investigate the module’s junction temperature by adjusting four factors: the thermal conductivity of the molding plastic, chip thickness, chip misalignment length, and the thermal conductivity of the adhesive film. We observed that the junction temperature decreases with an increase in the chip staggered length. An improved orthogonal experimental method was utilized to achieve the optimal design of the module. The optimal junction temperature has decreased by 4.74% compared to the initial value. Additionally, three alternative packaging technologies—cantilever, pyramid, and a combination of cantilever and pyramid—were evaluated for the benchmarking of the thermal performance. Ultimately, the stagger-stacked package demonstrated a reduction in the junction temperature by 3.62%, 7.95%, and 5.63%, respectively, when compared to the three traditional stacked packages. Full article

The quality and productivity of die castings are directly influenced by the injection system performance of the die-casting machine, making advanced performance monitoring of paramount importance. However, with the present technology, it is impossible to discriminate between the hydraulic components that influence the operation of a pressured injection system due to their sheer number and complexity. On the other hand, it is challenging to pinpoint the pressured injection system while it is in the poor performance stage due to the complexity and variety of the working conditions in actual production as well as the lack of data. In this paper, the hydraulic principle of the pressure injection system is examined, and a simulation model of the pressure injection system is built by adjusting the values of various components and running simulation experiments to produce a sample set. The sample set is fed into an intelligent evaluation approach that combines BP neural networks, convolutional neural networks (CNN), and long short-term memory networks (LSTM). The above intelligent algorithm is used to obtain both the performance index of the pressurized injection system and the components that lead to the low-performance index. The Dempster-Shafer (DS) theory is used to perform information fusion on the component classification results, and a new neural network is designed to perform information fusion on the performance metric evaluation results. The combined results are the final classification and regression results. Later, simulation tests are used to compare and validate the method. The findings demonstrate that the proposed intelligent algorithm outperforms previous algorithms in terms of accuracy and stability. In terms of component classification, the average accuracy for BP-LSTM is 87.83%, CNN-LSTM is 90.63%, after stacking it is 93.31%, and the proposed method is 95.67%. For performance evaluation, the average R2 of BP-LSTM is 0.88 and the average MAE is 3.09; the average R2 of CNN-LSTM is 0.908 and the average MAE is 2.64; and the average R2 of the proposed method is 0.947 and the average MAE is 1.86. Full article

The large differential-thermal extrusion (LDTE) process, a novel approach for efficiently fabricating a high-strength Mg-10.3Gd-4.4Y-0.9Zn-0.7Mn (wt.%) alloy, is introduced in this work. Unlike typical isothermal extrusion processes, where the ingot and die temperatures are kept the same, LDTE involves significantly higher ingot temperatures (~120 °C) compared to the die temperature. For high-strength Mg-RE alloys, the maximum isothermal extrusion ram speed is normally limited to 1 mm/s. This research uses the LDTE process to significantly increase the ram speed to 2.0 mm/s. The LPTE-processed alloy possesses a phase composition that is similar to that of isothermal extruded alloys, including α-Mg, 14H-type long-period stacking ordered (LPSO) and β-Mg₅(Gd, Y) phases. The weakly preferentially oriented α-Mg grains in the LDTE-processed alloy have $<10\overline{1}0>$_Mg//ED fibrous and <0001>_Mg//ED anomalous textures as their two main constituents. After isothermal aging, high quantitative densities of prismatic β′ and basal γ′ precipitates are produced, which have the beneficial effect of precipitation hardening. With a yield tensile strength of 344 MPa, an ultimate tensile strength of 488 MPa, and an elongation of 9.7%, the alloy produced by the LDTE process exhibits an exceptional strength–ductility balance, further demonstrating the potential of this method for efficiently producing high-strength Mg alloys. Full article