Search Results (29)

The increasing power density of 2.5D and 3D chiplets imposes severe thermal constraints that have a direct impact on the performance and long-term reliability of high-performance computing systems. Stacked and laterally integrated dies, which generate hundreds of watts per package, create localized hotspots and inconsistent temperature fields, major obstacles to scalable heterogeneous integration. Research efforts have addressed these challenges by finite element and compact heat modeling, thermal interface material optimization (TIM), and advanced cooling solutions such as micro-channel liquid cooling and cold racks. While these approaches provide valuable insights, most remain case-specific, focusing on isolated packages or single design variables, and lack a general methodology for assessing thermal feasibility at an early stage. This review consolidates and critically analyzes contributions to thermal modeling at the package level, interposer thermal spreading, thermal characterization of TIMs, and the development of cooling technologies. A comparative review of published studies indicates a consistent threshold: 2.5D stacks are viable under air cooling at approximately 300 W, whereas 3D stacks require liquid or hybrid cooling in conjunction with high-performance thermal interface materials at about 350 W. The investigations identify interposer conductivity, thermal interface material thickness, and hotspot power distribution as the primary sensitivity elements. This study explores Thermal Feasibility Maps (TFMs), defined as multidimensional charts parameterized by architecture, cooling regime, and material stack. TFMs provide a systematic framework for comparing design trade-offs and support architecture cooling co-design in advanced chiplet systems. Full article

Inorganic gap filling technology is an effective method to improve reliability and heterogeneous integration density in 2.5D and 3D integration. It uses plasma-enhanced chemical vapor deposition (PECVD) to deposit silicon dioxide (SiO₂) filler layers in gaps between chiplets. This technology is used to replace the Epoxy Mold Compound (EMC) commonly used in traditional packaging. However, as an inorganic filling material, SiO₂ poses reliability challenges such as cracking and peeling during or after deposition. Furthermore, there lacks quantitative characterization and modeling of the microscale mechanical properties, thermal stress distribution, and fracture failure risk in the filler layer. By combining nanoindentation technology with three-point bending tests, this study reports a comprehensive characterization route for quantitative characterization of mechanical behavior of the filler. A finite element method (FEM) model was also established to predict the thermomechanical reliability of the gap filling process. Raman spectroscopy measured data confirm the model’s reliable predictive ability. The results reveal the impact of filler thickness on the stress. The microscale SiO₂ mechanical characterization method and the thermal stress and fracture risk FEM prediction model in this study not only address the limitations of traditional testing and simulation but also provide support for process optimization and structural design of gap filling in high-density 2.5D/3D packaging. This work promotes the understanding of inorganic filling process reliability in chiplet integration. Full article

Densely integrated microarchitectures spanning three-dimensional integrated circuits (3D-ICs), chiplet-based designs, and system-in-package (SiP) assemblies make heat a first-order security concern rather than a mere reliability issue. This review consolidates the landscape of thermal side-channel attacks (TSCAs) on densely integrated microarchitectures: we systematize observation vectors and threat models, clarify core concepts and assumptions, compare the most credible evidence from the past decade, and distill the main classes of defenses across the hardware–software stack. We also explain why hardening against thermal leakage is integral to cyber–physical system (CPS) security and outline the most promising research directions for the field. The strategic relevance of this agenda is reflected in current policy and funding momentum, including initiatives by the United States Department of Homeland Security and the Cybersecurity and Infrastructure Security Agency (DHS/CISA) on operational technology (OT) security, programs by the National Science Foundation (NSF) on CPS, and Canada’s Regional Artificial Intelligence Initiative and Cyber-Physical Resilience Program (RAII, >CAD 35 million), to bridge advanced microelectronics with next-generation cybersecurity. This survey offers a clear, high-level map of the problem space and a focused baseline for future work. Full article

Artificial intelligence is redefining the computing landscape. Chiplets and heterogeneous integration have become the key strategies for current and next-generation processors. In the wake of Moore’s law slowing down, system integration through advanced packaging has emerged as the leading approach to achieve the highest performance per cost. Overall, the system is converging around substrate which is the main component of packaging. Glass stands out as the superior integration platform for chiplet-based systems. Glass substrates provide unmatched electrical and mechanical properties leading to unprecedented design and integration flexibility at a lower cost than competitive technologies. Three key advantages make glass the platform of choice: the ability to tune material properties, the ability to structure glass, and the feasibility of processing on a large panel scale. This review details the fundamentals of glass processing and manufacturing, innovative integration techniques, and cutting-edge research that collectively position glass substrate as a superior option for the next-generation systems for AI and beyond. Finally, we outline how technology must be shaped in the coming years to drive system scaling. Full article

The increasing complexity and cost of manufacturing monolithic chips have driven the semiconductor industry toward chiplet-based designs, where smaller, modular chiplets are integrated onto a single interposer. While chiplet architectures offer significant advantages, such as improved yields, design flexibility, and cost efficiency, they introduce new security challenges in the horizontal hardware manufacturing supply chain. These challenges include risks of hardware Trojans, cross-die side-channel and fault injection attacks, probing of chiplet interfaces, and intellectual property theft. To address these concerns, this paper presents ChipletQuake, a novel on-chiplet framework for verifying the physical security and integrity of adjacent chiplets during the post-silicon stage. By sensing the impedance of the power delivery network (PDN) of the system, ChipletQuake detects tamper events in the interposer and neighboring chiplets without requiring any direct signal interface or additional hardware components. Fully compatible with the digital resources of FPGA-based chiplets, this framework demonstrates the ability to identify the insertion of passive and subtle malicious circuits, providing an effective solution to enhance the security of chiplet-based systems. To validate our claims, we showcase how our framework detects hardware Trojans and interposer tampering. Full article

Modern gas sensor technology is becoming an important part of our lives. Hence, there has been considerable effort over the past 25 years towards the goal of creating low-cost gas sensors by employing modern microelectronics technology to manufacture both the sensing element and the signal conditioning circuitry on single silicon chips. CMOS sensors based on CMOS-SOI-MEMS technology seemed to be a good candidate for the monolithic approach. In this study, we critically review this approach. We show the advantages of chiplet-based designs for gas sensors that are based on CMOS-SOI-MEMS technology, dubbed GMOSs. The design of a monolithic GMOS system based on the voltage mode reading of a GMOS transistor connected in a three-terminal configuration is presented and validated for the first time. This study led to the understanding that a chiplet-like design should be preferred since the sensor and the readout circuitry of traditional gas sensors exhibit conflicting technological requirements. The innovation of this work is both in the readout design that it posits and in the resulting paradigm shift. Full article

Metalworking fluids (MWFs) are crucial in the manufacturing industry, playing a key role in facilitating various production processes. As each machining operation comes with distinct requirements, the properties of the MWFs have to be tailored to meet these specific demands. Understanding the properties of different MWFs is fundamental for optimizing processes and improving performance. This study centered on characterizing the thermal behavior of various cutting oils and water-based cutting fluids over a wide temperature range and sheds light on the specific tribological behavior. The results indicate that water-based fluids exhibit significant shear-thinning behavior, whereas cutting oils maintain nearly Newtonian properties. In terms of frictional performance, cutting oils generally provide better lubrication at higher temperatures, particularly in mixed and full-fluid film regimes, while water-based fluids demonstrate greater friction stability across a wider range of conditions. Among the tested fluids, water-based formulations showed a phase transition from solid to liquid near 0 °C due to their high water content, whereas only a few cutting oils exhibited a similar behavior. Additionally, the thermal conductivity and heat capacity of water-based fluids were substantially higher than those of the cutting oils, contributing to more efficient heat dissipation during machining. These findings, along with the reported data, intend to guide future researchers and industry in selecting the most appropriate cutting fluids for their specific applications and provide valuable input for computational models simulating the influence of MWFs in the primary and secondary shear zones between cutting tools and the workpiece/chiplet. Full article

An energy- and area-efficient non-return-to-zero (NRZ) transmitter with feedforward equalization (FFE) is proposed for an extra-short-reach (XSR) data interface in chiplet-based system in packages (SiPs) and multi-chip modules (MCMs). At the system level, the final-stage 2:1 multiplexer (MUX) in the transmitter is combined with the driver to reduce the hardware and power consumption; at the circuit level, charge-steering-based moderate-swing signal processing further reduces the circuit power consumption and inter-symbol interference. Fabricated in a 28 nm CMOS process with a core area of 0.032 mm², the prototype NRZ transmitter demonstrates an energy efficiency of 0.42 pJ/b at a data rate of 50 Gb/s with an insertion loss of 10 dB, which makes it a promising candidate for XSR die-to-die (D2D) interfaces. Full article

The ending of Moore’s Law calls for innovations in integrated circuit (IC) technologies and chip designs. Heterogeneous integration (HI) emerges as a pathway towards smart future chips for more Moore time and for beyond-Moore time, featuring systems-on-integrated-chiplets (SoICs) and advanced micro-packaging (μ-packaging). Reliability, particularly with regard to electrostatic charge (ESD) failure, is a major challenge for 3D SoIC chips in μ-packaging, which is an emerging design-for-reliability challenge for future chips. This perspective article articulates that interposer-based ESD protection will be an important potential solution for 3D SoIC chips in μ-packaging against the devastating ESD failure problem. Full article

The rise of 3D heterogeneous packaging holds promise for increased performance in applications such as AI by bringing compute and memory modules into close proximity. This increased performance comes with increased thermal management challenges. This research explores the use of thermal sensing and load throttling combined with federated computation to manage localized internal heating in a multi-3D chip package. The overall concept is that individual chiplets may heat at different rates due to operational and geometric factors. Shifting computational loads from hot to cooler chiplets can prevent local overheating while maintaining overall computational output. This concept is verified with experiments in a low-cost test vehicle. The test vehicle mimics a 3D chiplet stack with a tightly stacked assembly of SoC devices. These devices can sense and report internal temperature and dynamically adjust frequency. The configuration is for ESP32-S3 microcontrollers to work on a federated computational task, while reporting internal temperature to a host controller. The tight packing of processors causes temperatures to rise, with those internal to the stack rising more quickly than external ones. With real-time temperature monitoring, when the temperatures exceed a threshold, the AI system reduces the processor frequency, i.e., throttles the processor, to save power and dynamically shifts part of the workload to other ESP32-S3s with lower temperatures. This approach maximizes overall efficiency while maintaining thermal safety without compromising computational power. Experimental results with up to six processors confirm the validity of the concept. Full article

With the growing demand for high-performance computing (HPC), artificial intelligence (AI), and data communication and storage, new chip technologies have emerged, following Moore’s Law, over the past few decades. As we enter the post-Moore era, transistor dimensions are approaching their physical limits. Advanced packaging technologies, such as 3D chiplets hetero-integration and co-packaged optics (CPO), have become crucial for further improving system performance. Currently, most solutions rely on silicon-based technologies, which alleviate some challenges but still face issues such as warpage, bumps’ reliability, through-silicon vias’ (TSVs) and redistribution layers’ (RDLs) reliability, and thermal dissipation, etc. Glass, with its superior mechanical, thermal, electrical, and optical properties, is emerging as a promising material to address these challenges, particularly with the development of femtosecond laser technology. This paper discusses the evolution of both conventional and advanced packaging technologies and outlines future directions for design, fabrication, and packaging using glass substrates and femtosecond laser processing. Full article

Microwave photonics (MWP) applications often require a high optical input power (>100 mW) to achieve an optimal signal-to-noise ratio (SNR). However, conventional silicon spot-size converters (SSCs) are susceptible to high optical power due to the two-photon absorption (TPA) effect. To overcome this, we introduce a silicon nitride (SiN) SSC fabricated on a silicon-on-insulator (SOI) substrate. When coupled to a tapered fiber with a 4.5 μm mode field diameter (MFD), the device exhibits low coupling losses of <0.9 dB for TE modes and <1.4 dB for TM modes at relatively low optical input power. Even at a 1W input power, the additional loss is minimal, at approximately 0.1 dB. The versatility of the SSC is further demonstrated by its ability to efficiently couple to fibers with MFDs of 2.5 μm and 6.5 μm, maintaining coupling losses below 1.5 dB for both polarizations over the entire C-band. This adaptability to different mode diameters makes the SiN SSC a promising candidate for future electro-optic chiplets that integrate heterogeneous materials such as III-V for gain and lithium niobate for modulation with the SiN-on-SOI for all other functions using advanced packaging techniques. Full article

With the development of system-on-chip (SoC) and chiplet technology in the post-Moore era, an increasing number of chiplets are being integrated into a single chip. Consequently, the functions and complexity that can be realized are growing daily. Simultaneously, the volume of test data required for ultra-large-scale integrated circuits (ULSIs) has risen significantly. However, traditional automatic test equipment (ATE) is constrained by its data storage and bandwidth limitations, and its long technology iteration cycle. These cannot keep pace with the rapid development of design technology. This discrepancy leads to challenges in ULSI testing, such as excessively long test time and difficulties in completing the tests. Test compression technology can effectively address these issues by reducing the performance requirements of the test equipment, which in turn can lower test costs. This paper summarizes the classifications of chip test compression technology and, based on their current development, provides a detailed analysis of key technologies. It includes test compression-oriented coding methods, optimization of scan chain structures, and enhancements in coding for compression efficiency. Finally, a forward-looking perspective on the development of chip test compression technology is presented. The aim is to offer a reference for subsequent research in this field and related areas, as well as to provide technical support for the advancement of ULSI testing in the post-Moore era. Full article

Glass substrate, a new type of substrate with excellent mechanical and electrical properties of glass itself, has great potential to become an ideal platform for heterogeneous integration in chiplet systems for high-performance computing applications. The residual stress of the metal layer generated on the glass surface during the electroplating process is one of the major bottlenecks of glass packaging technologies, resulting in glass-metal layer delamination and glass breakage. This paper demonstrated for the first time a method to regulate the residual stress by manipulating the nanotwin directions of the electroplated Cu. The experimental results show that nanotwins with three different directions (non-directional, vertical, and horizontal) can be manipulated by controlling electroplating conditions (concentration of Cl⁻ and gelatin, stirring speed). The orientations of non-directional, vertical, and horizontal nanotwinned Cu are non-oriented, 110 and 111, respectively. After electroplating, the 111-oriented nanotwinned Cu has the smallest residual stress (39.7 MPa). Annealing can significantly reduce the residual stress of nanotwinned Cu, which has been attributed to the decrease in the geometric necessity dislocation density. 110-oriented nanotwinned Cu had drastic recrystallization, while 111-oriented nanotwinned Cu and non-oriented nanotwinned Cu had only slight recrystallization. After annealing, the residual stress of 111-nt-Cu remains the lowest (29.1 MPa). Full article

With the development of artificial intelligence (AI) and high-performance computing (HPC), the microelectronic industry is challenged with increased device integration density. Chiplet architecture can break through a variety of limitations on the system-on-chip (SoC) to create a high-computility system. However, chiplet heterogeneous integration suffers from high heat flux and serious thermal interaction problems. The factors affecting thermal interaction are not clear. In this paper, a collective parameter model and a distribution parameter model are developed to clarify the optimization method to mitigate thermal interaction. The trends predicted by the parameter model are consistent with the finite element method (FEM) simulation results. Furthermore, to cool the chiplets, a thermal test vehicle is designed and fabricated, and the cooling performance of the test vehicle with different flow rates, different TIMs (Thermal Interfacial Materials) (DOW5888 vs. liquid metal), and different heat modes is experimentally investigated. Compared with DOW5888, the utilization of liquid metal TIM can mitigate thermal interaction by 56% and 76% at flow rates of 0.2 L/min and 0.8 L/min, respectively. Consequently, at a temperature rise of 60 °C and a flow rate of 0.8 L/min, using liquid metal TIM can achieve heat fluxes of 330 W/cm² and 520 W/cm² for two chiplets, respectively. Full article