Thermal Management Challenges in 2.5D and 3D Chiplet Integration: A Review on Architecture–Cooling Co-Design

Abstract

The increasing power density of 2.5D and 3D chiplets imposes severe thermal constraints that have a direct impact on the performance and long-term reliability of high-performance computing systems. Stacked and laterally integrated dies, which generate hundreds of watts per package, create localized hotspots and inconsistent temperature fields, major obstacles to scalable heterogeneous integration. Research efforts have addressed these challenges by finite element and compact heat modeling, thermal interface material optimization (TIM), and advanced cooling solutions such as micro-channel liquid cooling and cold racks. While these approaches provide valuable insights, most remain case-specific, focusing on isolated packages or single design variables, and lack a general methodology for assessing thermal feasibility at an early stage. This review consolidates and critically analyzes contributions to thermal modeling at the package level, interposer thermal spreading, thermal characterization of TIMs, and the development of cooling technologies. A comparative review of published studies indicates a consistent threshold: 2.5D stacks are viable under air cooling at approximately 300 W, whereas 3D stacks require liquid or hybrid cooling in conjunction with high-performance thermal interface materials at about 350 W. The investigations identify interposer conductivity, thermal interface material thickness, and hotspot power distribution as the primary sensitivity elements. This study explores Thermal Feasibility Maps (TFMs), defined as multidimensional charts parameterized by architecture, cooling regime, and material stack. TFMs provide a systematic framework for comparing design trade-offs and support architecture cooling co-design in advanced chiplet systems.

1. Introduction and Background

For almost fifty years, the pace of advancement in computing has been driven by Moore’s observation that transistor density on integrated circuits would increase exponentially [1,2,3]. The initial decades combined this scaling with nearly optimal voltage and power scaling (Dennard scaling), resulting in concurrent improvements in performance, energy efficiency, and cost [4,5]. By the middle of the 2010s, the combination of physical and economic problems showed that Moore’s Law and Dennard scaling were both slowing down. Supply-voltage scaling declined, leakage currents and interconnect limitations became more critical, and power density made it harder to reach higher performance levels [6,7,8,9]. The net result is that Joule heating and related thermal gradients have emerged as primary design constraints in advanced logic and memory systems [7,10,11,12].

Consequently, system architects have transitioned from extensive monolithic SoCs to heterogeneous integration (HI) employing chiplets, which distribute functionality across multiple dies, integrate diverse process nodes, and utilize package-level interconnects to achieve system-level performance [13,14,15,16]. Examples include NVIDIA’s Hopper H100 (2.5D CoWoS) [17], AMD’s MI300 (hybrid 3D) [18], and Intel’s Ponte Vecchio (Foveros+EMIB) [19], NVIDIA Blackwell B200 [20], AMD Instinct MI350X and MI355X [21], AWS Trainium 2 [22], Tesla’s Dojo D1 [23], and the Positron Atlas AI accelerator [24], which exemplify the trend towards multi-die, high-bandwidth computing architectures where thermal and power management are essential for maintaining performance and reliability. These architectures improve thermal coupling between logic, memory, and I/O, but create very uneven power maps that worsen through-stack heat-removal problems, making them worse than those of older monolithic CPUs [25,26,27]. Practical packages consistently surpass average heat fluxes, 100 $\mathrm{W}{\mathrm{cm}}^{-2}$ with localized hot spots reaching or surpassing $1\mathrm{kW}{\mathrm{cm}}^{-2}$ [16,26,28], underscoring the significance of co-design in power delivery, materials, interfaces, and cooling hardware [29,30,31]. Figure 1 summarizes this evolution in semiconductor packaging, from monolithic SoCs to heterogeneous 2.5D and 3D integration, highlighting the associated increases in thermal resistance pathways and localized heat fluxes.

Historically, early System-on-Chip (SoC) architectures relied on predominantly one-dimensional heat conduction through bulk silicon to a lid or heat sink, allowing classical analytical models of spreading resistance and contact conductance to predict junction temperatures with good accuracy [32,33,34,35,36,37]. As transistor densities increased following Moore’s law, power dissipation became more spatially non-uniform and the assumption of uniform heat flux broke down [38,39]. This shift motivated the development of compact thermal models and dynamic RC-network analogs to resolve temperature variations in space and time, laying the foundation for contemporary electro-thermal co-design and early stage thermal-aware placement and routing in modern SoCs [40,41,42,43].

The development of multi-chip modules (MCMs) introduced lateral multi-die packaging on a common substrate, enabling module reuse and yield improvement at the expense of increased lateral thermal resistance [44,45]. Typical epoxy–glass substrates in MCMs exhibit thermal conductivities of 0.3–0.6 $\mathrm{W}{\mathrm{m}}^{-1}{\mathrm{K}}^{-1}$, which are two to three orders of magnitude lower than bulk silicon (≈150 $\mathrm{W}{\mathrm{m}}^{-1}{\mathrm{K}}^{-1}$) [46,47,48]. As package power increased, these low-k substrates became the dominant bottleneck for heat spreading, motivating the use of high-k filler-loaded adhesives, composite underfills, copper redistribution layers, and backside metal spreaders to enhance lateral heat transport and reduce substrate temperature gradients [45].

The change to 2.5D integration, enabled by passive silicon interposers that connect multiple logic and memory chiplets, substantially altered the thermal flow dynamics [49]. In these systems, the silicon interposer has a high in-plane thermal conductivity of about 150 W m⁻¹ K⁻¹, but the underfills and dielectric layers that accompany it have significantly lower cross-plane thermal conductivity, making thermal transport quite anisotropic. Microbumps and hybrid-bond interfaces increase thermal boundary resistance, leading to uneven heating. The temperature field depends on how power is distributed, the thermal resistance between surfaces, and the design of the vertical conduction channel. Simulations and experiments on high-density 2.5D packages, including CoWoS and EMIB, have shown that interposer hotspot temperatures can reach over 120 °C when overall power levels are above 600–700 W [16]. These results indicate that material anisotropy, die placement, and cooling architecture are becoming increasingly interlinked.

In conventional 2.5D packages, interposer overheating at total powers above 600–700 W is primarily a consequence of low external heat-transfer coefficients. Air-cooled assemblies exchange heat with the environment via natural or moderately forced convection, yielding effective package-level coefficients of only $h\approx 5$–50 $\mathrm{W}{\mathrm{m}}^{-2}{\mathrm{K}}^{-1}$ for ambient temperatures $T_{\infty }\approx 20$–$25°\mathrm{C}$ [37,50]. Under these low-h conditions, the cross-plane thermal resistance of underfills, dielectrics, microbumps, and hybrid-bond interfaces becomes rate-limiting, and both calibrated finite-element models and silicon interposer test vehicles report hotspot temperatures above $120°\mathrm{C}$ at such power levels [16]. By contrast, fluidic cooling integrated into silicon interposers or 3D stacks operates with controlled inlet temperatures $T_{\mathrm{in}}\approx 20$–$30°\mathrm{C}$ and achieves $h\sim {10}^4$–${10}^5\mathrm{W}{\mathrm{m}}^{-2}{\mathrm{K}}^{-1}$ using embedded microchannels or jet impingement, as validated by infrared thermography, temperature-sensitive diodes, calorimetry, and conjugate CFD/FEA simulations [51,52,53].

Fully 3D stacking further amplifies these issues by constraining vertical heat removal [54]. Through-silicon vias (TSVs), bonding layers, and dielectric liners introduce significant thermal impedance, while inter-die coupling promotes correlated hotspots and thermo-mechanical stress. As interconnect pitches approach the sub-10 µm regime in technologies such as Intel Foveros and TSMC 3D-SoIC, the effective heat-extraction path lengthens relative to the power density, pushing junction temperatures toward material limits [55]. To alleviate this, research has advanced toward embedded and co-packaged cooling, where microfluidic or two-phase channels are integrated directly into silicon or interposer substrates to enhance through-plane heat transfer [56,57]. These techniques enable local heat fluxes exceeding $100\mathrm{W}{\mathrm{cm}}^{-2}$ while maintaining acceptable thermal gradients.

At the most advanced integration levels, die-to-wafer (D2W) and wafer-to-wafer (W2W) hybrid bonding technologies enable near-monolithic three-dimensional assemblies with exceptional interconnect density and minimal interfacial voiding [58]. Despite their electrical and mechanical benefits, such bonding schemes restrict access for conventional thermal interface materials and underfills, increasing thermal impedance and complicating heat-removal pathways in vertically stacked structures. Consequently, thermal management must be co-optimized with electrical, mechanical, and reliability considerations from the earliest design stages [59,60].

At these power densities, thermal feasibility is governed by both lateral heat spreading in solids and interfacial resistance along the junction-to-ambient path. Heat traverses the die, underfill or interposer, thermal interface materials (TIMs), lids or spreaders, and the final heat sink or cold plate, with the thermal conductivity of each layer and the contact resistance at each interface jointly setting the maximum junction temperature and long-term reliability [32,61,62]. While metals and conventional composites with $k\sim 10$–$400\mathrm{W}{\mathrm{m}}^{-1}{\mathrm{K}}^{-1}$ remain central to these stacks, emerging materials with exceptionally high and often anisotropic conductivity provide new opportunities for directional heat spreading [30,63,64,65,66].

To address this gap, we are exploring Thermal Feasibility Maps (TFMs), a comprehensive framework that integrates analytical models, multi-fidelity and finite-element simulations, and focused experiments to define the operational boundaries that comply with junction-temperature constraints across diverse stacks [31,67]. TFMs transform thermal management from a late-stage limitation to an early co-optimization catalyst, influencing decisions regarding chiplet partitioning, bonding and interposer technologies, heat-spreader anisotropy, and cooling architectures for next-generation HI systems [13,14,16,26]. The overall structure of the paper and the logical progression of this framework are summarized in Figure 2.

2. Fundamentals of Heat Transfer in Heterogeneous Integration

Over the years, the physics of heat transport has shifted from planar SoCs to vertically stacked 3D assemblies. In the past, heat went through homogeneous silicon. Now, it goes through interfaces and geometry, which indicates the complexity of modern thermal transport in heterogeneous integration.

Thermal management in heterogeneous integration poses a multiscale challenge due to the interplay among heat conduction, interfacial resistance, and convective transport, which collectively determine junction temperatures and system reliability. Section 2.1 examines essential heat-transfer methods in sophisticated packages. Section 2.2 elaborates on thermal-resistance models, emphasizing thermal interface materials (TIMs), bonding techniques, interposers, heat distribution, and substrates. Section 2.3 evaluates air, liquid, and two-phase cooling techniques for high-power chiplet systems. Section 2.4 ultimately discusses thermo-mechanical stresses and dependability.

Figure 3 provides a high-level overview of thermal trends across semiconductor generations, illustrating how increasing integration density and switching speeds intensify power density, interfacial resistance, and hotspot formation.

2.1. Heat-Transfer Mechanisms in Advanced Packages

Thermal management in semiconductor packaging follows the same physical principles as macroscale systems, yet nanoscale effects, heterogeneous material interfaces, and extreme power densities magnify its complexity. In modern 2.5D and 3D heterogeneous architectures, heat transfer occurs through a coupled hierarchy of conduction, interfacial resistance, and convection pathways that collectively define the thermal limits of performance and reliability [69].

The impact of temperature relative to other environmental stressors on electronic reliability is illustrated in Figure 4, which summarizes the dominant contributors to failure in electronic equipment.

2.1.1. Mechanism 1: Heat Conduction in Solid Chip and Package Materials

Heat conduction controls how temperature changes within the solid parts of the package, such as the silicon die, interposer, redistribution layers (RDLs), underfills, and the package substrate. Fourier’s law shows how heat flux and temperature gradient are related in a certain area:

$$q=-k\nabla T,$$

(1)

where q is the heat-flux vector (W/m²), k is the thermal conductivity (W/m·K), and $\nabla T$ is the temperature gradient [72].

The thermal conductivity of packaging materials spans nearly four orders of magnitude. Single-crystal silicon exhibits $k\approx 130$–150 $\mathrm{W}{\mathrm{m}}^{-1}{\mathrm{K}}^{-1}$ [47,73], copper ∼385–401 $\mathrm{W}{\mathrm{m}}^{-1}{\mathrm{K}}^{-1}$ [74,75], and epoxy–glass substrates (FR-4) only 0.3–0.8 $\mathrm{W}{\mathrm{m}}^{-1}{\mathrm{K}}^{-1}$ [47]. Glass interposers further limit through-plane conduction ($k\approx$ 0.5–1 $\mathrm{W}{\mathrm{m}}^{-1}{\mathrm{K}}^{-1}$). By contrast, advanced fillers and composites such as AlN, Cu–Mo laminates, and synthetic diamond ($\mathrm{W}{\mathrm{m}}^{-1}{\mathrm{K}}^{-1}$) enable lateral heat spreading.

This wide anisotropy in conductivity drives preferential heat-flow directions. Heat spreads efficiently through lateral copper traces and RDLs but encounters severe impedance through vertical paths across underfills or substrates. Experimental studies using frequency-domain thermoreflectance have shown that buried metal–dielectric interfaces in advanced microelectronic stacks exhibit strong directional dependence in thermal transport, high in-plane conduction through metallic layers, and markedly lower through-plane conduction dominated by interfacial resistance, underscoring the anisotropic nature of heat flow in layered packaging materials [76]. In 2.5D chiplet systems, the interposer and substrate act as critical thermal bridges, and their material selection strongly influences both peak junction temperature and thermomechanical stress.

2.1.2. Mechanism 2: Spreading Resistance and Interfacial Heat Transfer

Thermal spreading and interface resistance are the main factors that affect temperature distribution at sizes less than a millimeter. For a circular isothermal source with a radius of a on a semi-infinite substrate with a thermal conductivity of k, the spreading resistance is as follows:

$$R_{\mathrm{sp}}\approx {\displaystyle \frac{1}{4ka}},$$

(2)

as derived by Carslaw and Jaeger [77,78] and later generalized by Yovanovich [33]. The spreading resistance can account for 20–40% of the total junction-to-ambient thermal impedance in chiplet packages.

In addition to spreading, material interfaces contribute thermal boundary resistance (TBR) arising from phonon mismatch and imperfect adhesion. Typical TBR values range from ${10}^{-8}$–${10}^{-7}$ m²K/W for metal–metal contacts to >${10}^{-6}$ m²K/W for dielectric junctions. Experimental studies have shown that fusion-bonded 3D stacks exhibit interfacial resistances up to $5\times {10}^{-7}$ m²K/W depending on oxide layer thickness and bonding quality.

The combined thermal impedance across an interface is thus expressed as follows:

$$R_{\mathrm{total}}=R_{\mathrm{sp}}+R_{\mathrm{TBR}}.$$

(3)

Mitigating these resistances requires innovations such as Cu–Cu hybrid bonding, nano-filler TIMs, and metal-doped underfills [79,80,81,82].

2.1.3. Mechanism 3: Convective Heat Transfer and Cooling Boundaries

Once heat conducts through the solid layers, it is removed by convection at the coolant interface. Newton’s law of cooling defines this process [72]:

$$q^{″}=h(T_{\mathrm{s}}-T_{\infty }),$$

(4)

where h is the convective heat transfer coefficient, $T_{\mathrm{s}}$ the surface temperature, and $T_{\infty }$ the coolant’s bulk temperature.

Typical values from experimental and the reviewed literature are as follows:

• Natural or forced air: 5–$50\mathrm{W}{\mathrm{m}}^{-2}{\mathrm{K}}^{-1}$ [83];
• Single-phase liquid cooling: ${10}^3$–$2\times {10}^4\mathrm{W}{\mathrm{m}}^{-2}{\mathrm{K}}^{-1}$ [51];
• Two-phase microchannel/jet cooling: >$5\times {10}^4\mathrm{W}/{\mathrm{m}}^2\mathrm{K}$, enabling fluxes well above $100\mathrm{W}{\mathrm{m}}^{-2}{\mathrm{K}}^{-1}$ [84].

These values indicate that standard air cooling is not feasible beyond roughly $100\mathrm{W}/{\mathrm{cm}}^2$, as achieving $\mathrm{\Delta }T\approx 10\mathrm{K}$ would need $h\approx {10}^5\mathrm{W}{\mathrm{m}}^{-2}{\mathrm{K}}^{-1}$. In controlled laboratory environments, specific high-flux cooling systems have demonstrated cooling capacities exceeding 300–400 W/cm². Modern heterogeneous systems use built-in liquid interposers or microfluidic cold plates to control these densities. However, these solutions require more trade-offs, such as pressure drop, flow control, and mechanical stress [85].

The complete junction-to-ambient heat-flow path, including junction-to-case, case-to-sink, and sink-to-ambient thermal resistances, together with lateral and vertical heat-spreading mechanisms, is schematically illustrated in Figure 5.

2.1.4. Transient Heat Conduction and Dynamic Thermal Response

Under non-steady workloads, temperature evolves according to the following:

$$\rho c_p{\displaystyle \frac{\partial T}{\partial t}}=k{\nabla }^{2}T+Q,$$

(5)

where Q is the volumetric heat generation, $c_p$ is the specific heat, and $\rho$ is the density. In AI accelerators and HPC systems, transient heating is a significant design concern due to rapid load switching, which generates sub-millisecond thermal spikes [86]. Reduced-order solvers and compact RC models are frequently implemented in predictive transient analysis.

2.1.5. Junction Temperature and Reliability Constraints

The maximum junction temperature ($T_j$) significantly affects device longevity by influencing electromigration, time-dependent dielectric breakdown (TDDB), and bias-temperature instability (BTI). Design regulations typically require that $T_j$ not exceed 125 °C; however, in stacked or high-power dies, localized hotspots may exceed this threshold without meticulous thermal management. Prolonged temperature gradients can generate thermomechanical stress, resulting in solder fatigue, bond-wire detachment, or delamination. This was demonstrated in recent electro-thermal-mechanical co-design studies [87].

The Coffin–Manson–Arrhenius relationship can be used to describe how long power electronic modules last when they go through thermal cycling:

$$N_f=a{\left(\mathrm{\Delta }{T}_j\right)}^{-\alpha }{e}^{{\displaystyle \frac{E_a}{k_B{T}_{j,m}}}},$$

(6)

where $N_f$ is the number of cycles until failure, $\mathrm{\Delta }{T}_j$ is the change in junction temperature, $T_{j,m}$ is the average junction temperature, a and $\alpha$ are empirical coefficients, $E_a$ is the activation energy, and $k_B$ is the Boltzmann constant. This model shows that both the size and the average rate of temperature change accelerate the processes that cause fatigue-related degradation.

Miner’s rule can be used to figure out how much cumulative lifetime damage happens when stress amplitudes change:

$$C=\sum _i{\displaystyle \frac{n_i}{N_i}},$$

(7)

In this equation, C is the cumulative damage index, $n_i$ is the number of cycles at stress level i, and $N_i$ is the number of cycles till failure at that level. When $C\ge 1$, failure is expected. The junction temperature can be approximated using an electrothermal model as follows:

$$T_j=T_c+P_{\mathrm{loss}}{R}_{\mathrm{th}(\mathrm{j}-\mathrm{c})},$$

(8)

In this context, $T_c$ represents the case or substrate temperature, $P_{\mathrm{loss}}$ denotes the total device power loss, which includes both conduction and switching losses, and $R_{\mathrm{th}(\mathrm{j}-\mathrm{c})}$ indicates the thermal resistance between the junction and the case. This expression directly links power-dissipation profiles to thermal stress and lifetime prediction.

2.2. Thermal Resistance Network and Material Parameters

Full finite-element thermal analysis is often computationally demanding, so early stage thermal evaluation typically uses simplified lumped-resistance networks that resemble electrical RC circuits. These models capture the dominant conduction and convection paths while maintaining high computational efficiency.

2.2.1. Thermal Resistance Models

The overall junction-to-ambient resistance can be expressed as

$$R_{\theta \mathrm{JA}}=R_{\theta \mathrm{JC}}+R_{\theta \mathrm{CS}}+R_{\theta \mathrm{SA}},$$

(9)

where $R_{\theta \mathrm{JC}}$ represents the junction-to-case resistance through the die and package, $R_{\theta \mathrm{CS}}$ is the case-to-sink (thermal interface) resistance, and $R_{\theta \mathrm{SA}}$ corresponds to the sink-to-ambient resistance, which is mainly governed by convective heat transfer.

This formulation follows the JEDEC JESD51 [88] thermal characterization standards and provides the foundation for compact thermal models commonly used in early package design and feasibility analysis.

To clarify how the overall junction-to-ambient thermal resistance $R_{\theta ,JA}=R_{\theta ,JC}+R_{\theta ,CS}+R_{\theta ,SA}$ evolves when transitioning from 2.5D to 3D integration, we summarize representative values from published data in Table 1 and Table 2. For 2D/2.5D FCBGA logic packages, Intel AN358 (Intel Corporation, Santa Clara, CA, USA) reports ${\theta }_{JC}\approx 0.13$ °C/W and ${\theta }_{SA}\approx 1.35$ °C/W under 400 ft/min airflow [89], placing typical 2.5D values in the ranges $R_{\theta ,JC}\sim 0.1$–$0.3$ °C/W, $R_{\theta ,CS}\sim 0.05$–$0.3$ °C/W, and $R_{\theta ,SA}\sim 1$–3 °C/W. However, experimentally characterized 3D DRAM cubes exhibit ${\theta }_{JC}\approx 3$ °C/W [90], and hybrid-bonded HBM stacks typically show $R_{\theta ,JC}\sim 1.5$–$2.0$ °C/W [91], reflecting an approximate one order-of-magnitude increase in junction-to-case resistance compared to advanced 2.5D modules.

This increase is consistent with reported thermal boundary resistances (TBRs) of ${10}^{-9}$–${10}^{-7}$ m²K/W for metal/semiconductor or oxide interfaces [92,93,94], which accumulate across multiple bonding, underfill, and TSV-related layers in 3D stacks. By contrast, the case-to-sink and sink-to-ambient contributions depend mainly on external cooling hardware and therefore remain in comparable numerical ranges across 2.5D and 3D packages.

Table 2 further provides representative per-area thermal resistances for common TIM and lid stack materials. Greases, gels, and PCMs typically fall in the 0.1–1.0 °C·cm²/W range [89,95], thermal pads exhibit 1–4 °C·cm²/W, TIM1+Cu lid stacks contribute ∼$0.45$ cm²K/W in measured 2.5D test vehicles [96], metallic TIMs fall in the 0.05–0.20 °C·cm²/W range, and hybrid-bonded interfaces achieve the lowest impedances due to extremely small TBRs per-interface [92,93]. These data form the empirical basis for the $R_{\theta ,CS}$ values used in our thermal feasibility analysis.

Table 1. Representative decomposition of thermal resistance components for 2.5D and 3D packages. Ranges compiled from Intel AN358 [89], Agnesina et al. [90], and hybrid-bonded HBM thermal analyses [91].

Package Type	${\mathit{R}}_{\mathit{\theta },\mathit{JC}}$	${\mathit{R}}_{\mathit{\theta },\mathit{CS}}$	${\mathit{R}}_{\mathit{\theta },\mathit{SA}}$	Physical Drivers
2D/2.5D FCBGA (air-cooled)	0.1–0.3	0.05–0.3	1.0–3.0	Intel AN358 reports ${\theta }_{JC}=0.13$ °C/W and ${\theta }_{SA}=1.35$ °C/W at 400 ft/min [89]. Heat path dominated by single-die conduction.
2.5D interposer (lidded)	0.15–0.4	0.05–0.2	1.0–3.0	Silicon interposer adds spreading layers. TIM+lid stack contributes ∼$0.45$ cm2K/W [96].
3D hybrid-bonded HBM stack	1.5–2.0	0.05–0.3	1.0–3.0	Multiple Cu–Cu/oxide bonding interfaces with TBRs in ${10}^{-9}$–${10}^{-7}$ m2K/W range [92,93]. Representative $R_{\theta ,JC}$ summarized by Lee et al. [91].
3D DRAM cube (14-die)	2.5–3.0	0.05–0.3	1.0–3.0	Agnesina et al. report ${\theta }_{JC}\approx 3$ °C/W and ${\theta }_{JB}\approx 5$ °C/W [90]. Stack height, underfill, and TSV density significantly increase $R_{\theta ,JC}$.

Table 1. Representative decomposition of thermal resistance components for 2.5D and 3D packages. Ranges compiled from Intel AN358 [89], Agnesina et al. [90], and hybrid-bonded HBM thermal analyses [91].

Package Type	${\mathit{R}}_{\mathit{\theta },\mathit{JC}}$	${\mathit{R}}_{\mathit{\theta },\mathit{CS}}$	${\mathit{R}}_{\mathit{\theta },\mathit{SA}}$	Physical Drivers
2D/2.5D FCBGA (air-cooled)	0.1–0.3	0.05–0.3	1.0–3.0	Intel AN358 reports ${\theta }_{JC}=0.13$ °C/W and ${\theta }_{SA}=1.35$ °C/W at 400 ft/min [89]. Heat path dominated by single-die conduction.
2.5D interposer (lidded)	0.15–0.4	0.05–0.2	1.0–3.0	Silicon interposer adds spreading layers. TIM+lid stack contributes ∼$0.45$ cm2K/W [96].
3D hybrid-bonded HBM stack	1.5–2.0	0.05–0.3	1.0–3.0	Multiple Cu–Cu/oxide bonding interfaces with TBRs in ${10}^{-9}$–${10}^{-7}$ m2K/W range [92,93]. Representative $R_{\theta ,JC}$ summarized by Lee et al. [91].
3D DRAM cube (14-die)	2.5–3.0	0.05–0.3	1.0–3.0	Agnesina et al. report ${\theta }_{JC}\approx 3$ °C/W and ${\theta }_{JB}\approx 5$ °C/W [90]. Stack height, underfill, and TSV density significantly increase $R_{\theta ,JC}$.

Table 2. Representative per-area thermal resistance ($R^{″}$) ranges for TIM and cap stacks.

Interface Class	${\mathit{R}}^{″}$ (°C·cm2/W)	Materials	Physical Drivers	Ref.
Greases (TIM2)	0.10–0.40	Silicone oil; Al2O3/BN-filled greases	Range corresponds to realistic BLT and pressure. CNT-greases reach lower bound (∼0.18 cm2K/W).	[89,95]
Gels/filled adhesives	0.15–1.00	Silicone gels; Ag-filled epoxy adhesives	Higher BLT; filler loading strongly influences thermal impedance.	[89]
Phase-change materials (PCMs)	0.30–0.70	Wax/polymer TPCM films	Melting collapses BLT; pressure sensitive; commonly 0.3–0.7 cm2K/W.	[89]
Thermal pads/tapes	1.0–4.0	Elastomer pads; PSA-based tapes	Large BLT → highest thermal resistance; unsuitable for high heat flux.	[89]
TIM1 + Cu lid stack	$\approx 0.45$	TIM + copper lid	Measured in 2.5D jet-impingement cooling test vehicle; corresponds to 0.05–0.15 °C/W depending on die area.	[96]
Metallic TIMs	0.05–0.20	InSn; AuSn; sintered Ag	High k (30–80 W/mK) + small BLT (<10 µm) → low impedance.	[92,93]
Hybrid-bonded interfaces	${10}^{-3}$–${10}^{-2}$	Cu–Cu bonding; oxide fusion bonding	Derived from TBR ${10}^{-9}$–${10}^{-7}$ m2K/W; ultra-low impedance when scaled by interface area.	[92,93,94]

Table 2. Representative per-area thermal resistance ($R^{″}$) ranges for TIM and cap stacks.

Interface Class	${\mathit{R}}^{″}$ (°C·cm2/W)	Materials	Physical Drivers	Ref.
Greases (TIM2)	0.10–0.40	Silicone oil; Al2O3/BN-filled greases	Range corresponds to realistic BLT and pressure. CNT-greases reach lower bound (∼0.18 cm2K/W).	[89,95]
Gels/filled adhesives	0.15–1.00	Silicone gels; Ag-filled epoxy adhesives	Higher BLT; filler loading strongly influences thermal impedance.	[89]
Phase-change materials (PCMs)	0.30–0.70	Wax/polymer TPCM films	Melting collapses BLT; pressure sensitive; commonly 0.3–0.7 cm2K/W.	[89]
Thermal pads/tapes	1.0–4.0	Elastomer pads; PSA-based tapes	Large BLT → highest thermal resistance; unsuitable for high heat flux.	[89]
TIM1 + Cu lid stack	$\approx 0.45$	TIM + copper lid	Measured in 2.5D jet-impingement cooling test vehicle; corresponds to 0.05–0.15 °C/W depending on die area.	[96]
Metallic TIMs	0.05–0.20	InSn; AuSn; sintered Ag	High k (30–80 W/mK) + small BLT (<10 µm) → low impedance.	[92,93]
Hybrid-bonded interfaces	${10}^{-3}$–${10}^{-2}$	Cu–Cu bonding; oxide fusion bonding	Derived from TBR ${10}^{-9}$–${10}^{-7}$ m2K/W; ultra-low impedance when scaled by interface area.	[92,93,94]

2.2.2. Thermal Interface Materials (TIMs)

The concept of thermal interface materials (TIMs) [48,97] emerged in the 1960s alongside the miniaturization of electronic components and the growing need to manage heat dissipation in transistors and integrated circuits. Early studies of interfacial heat transfer by Swartz and Pohl established the foundation of interfacial thermal resistance (ITR), defining it as the temperature discontinuity across an interface per unit heat flux [98]. As power densities increased through the 1980s and 1990s, polymer-based greases, phase-change materials, and metallic solders were progressively developed to mitigate the temperature rise between chips and heat spreaders. In modern microelectronics and 3D integration, the interface between semiconductor dies, lids, and heat spreaders remains a fundamental challenge for heat dissipation. TIMs fill the tiny gaps that form because of uneven or rough surfaces. This helps heat flow smoothly between layers and reduces thermal resistance in the device. Figure 6 shows the TIMs bridging the gaps between these components, enhancing thermal contact and promoting uniform heat spreading.

At the interface scale, the total thermal resistance $R_{\mathrm{th}}$ comes from both conduction through the TIM as a whole and contact resistance at its boundaries:

$$R_{\mathrm{th}}=R_{\mathrm{TIM}}+R_{c1}+R_{c2},$$

(10)

where $R_{\mathrm{TIM}}=t_{\mathrm{BLT}}/\left(k_{\mathrm{TIM}}A\right)$ is the bulk conduction term determined by the bond-line thickness $t_{\mathrm{BLT}}$, thermal conductivity $k_{\mathrm{TIM}}$, and contact area A; and $R_{c1},R_{c2}$ represent the thermal contact resistances between the TIM and adjoining surfaces [48,98]. The fundamental definition of interfacial resistance is given by

$$R={\displaystyle \frac{\mathrm{\Delta }T}{J}},$$

(11)

where $\mathrm{\Delta }T$ is the temperature difference across the interface and J is the heat flux density. For convenience, $R_c$ is often expressed in terms of the thermal boundary conductance (TBC) $h_{\mathrm{TBC}}$ as $R_c=1/\left(h_{\mathrm{TBC}}A\right)$.

Fourier’s law of steady-state conduction relates local temperature gradients to heat flux:

$$\mathbf{J}=-k\nabla T,$$

(12)

where k is the intrinsic thermal conductivity of the medium. For effective heat transfer, both the bulk term $t_{\mathrm{BLT}}/k_{\mathrm{TIM}}$ and the interfacial term $1/h_{\mathrm{TBC}}$ must be minimized.

Thermal interface materials (TIMs) have changed over time as device power densities have increased and microelectronic packaging has become more integrated [48,97,99].

• First Generation: Silicone Greases and Filled Polymers—Commercial TIMs began with silicone-based greases or pastes filled with high-thermal-conductivity ceramics like alumina (Al₂O₃) and boron nitride (BN), offering $k\sim 1$–5 W·m⁻¹·K⁻¹ They were inexpensive and reworkable, but pump-out, drying, and bond-line instability during thermal cycling degraded them.
• Second Generation: Phase-Change and Metal-Filled Adhesives—Phase-change materials (PCMs) having melting points between 50 and 70 °C softened to adapt to surface irregularities, therefore decreasing interfacial contact resistance $R_c$ to around 0.1 °C·cm²/W. Simultaneously, silver-filled epoxies and indium-based metal adhesives enhanced contact stability and mechanical adhesion for high-power devices [100,101].
• Third Generation: Metallic Solders and Low-Melting Alloys—Metallic TIMs such as indium–tin (InSn) and gold–tin (AuSn) solders deliver high thermal conductivity ($k=30–80\mathrm{W}{\mathrm{m}}^{-1}{\mathrm{K}}^{-1}$) and ultra-thin bond lines (BLT $<10\mathsf{\mu }\mathrm{m}$), enabling efficient heat transfer in HPC and memory stacks. Yet, CTE mismatch with silicon often leads to fatigue and delamination during thermal cycling.
• Fourth Generation: Nanoengineered Interfaces—Nanoengineered interfaces, including CNT arrays, graphene films, Ag nanoparticle sintering, and Si–Si hybrid bonding [102,103,104], achieve high conductivity ($k>100\mathrm{W}{\mathrm{m}}^{-1}{\mathrm{K}}^{-1}$) and thermal boundary conductance ($h_{\mathrm{TBC}}>300\mathrm{MW}{\mathrm{m}}^{-2}{\mathrm{K}}^{-1}$), nearing phonon transport limits. Yet, complex fabrication and yield loss remain challenges [105,106].

A comparative summary of the four generations of thermal interface materials, including representative materials, thermal performance, reliability considerations, and typical applications, is provided in

Table 3. Evolution of TIM generations and their performance characteristics [48,97,102,103,104].

Generation	Materials	Thermal Conductivity	Features	Reliability Issues	Applications
1st Gen	Silicone grease; Al2O3/BN-filled pastes	1–5	Low cost; easy to apply	Pump-out; drying; thickness drift	CPUs; GPUs
2nd Gen	PCMs; Ag-filled epoxy; In/Sn adhesives	3–10	Softens at 50–70 °C; lowers $R_c$	Aging; phase separation	Servers; telecom
3rd Gen	InSn, AuSn solders; metallic alloys	30–80	Solid conduction; thin BLT (<10 µm)	CTE fatigue; cracking	HPC chips; HBM
4th Gen	CNT/graphene films; Ag sintering; Si–Si bonds	>100	High k, high $h_{\mathrm{TBC}}$; micron-scale	Process complexity; yield loss	AI/HPC GPUs; 3D packages

.

Reliability and Emerging Trends

Thermal reliability of TIMs depends on the interaction between bulk thermal conductivity ($k_{\mathrm{TIM}}$), interfacial conductance ($h_{\mathrm{TBC}}$), and mechanical compliance (elastic modulus E) [69]. Metallic or sintered films provide high thermal performance but limited flexibility, while polymeric composites offer high compliance at the cost of thermal efficiency [97]. Under cyclic loading, void growth, delamination, and microcracking progressively increase total thermal resistance $R_{\mathrm{th}}$.

Recent advances show progress toward mechanically strong, low-resistance interfaces. Localized liquid-metal layers achieve BLTs below 10 µm and interfacial resistances $R_{\mathrm{int}}<0.3$ mm²·K·W⁻¹ [107]. Similarly, graphene–copper hybrid “sandwich” structures [102] and boron nitride nanosheet composites [105] exhibit high $h_{\mathrm{TBC}}$ values (>300 MW·m⁻²·K⁻¹) while maintaining stability under thermal cycling. Surface functionalization and self-assembled monolayers (SAMs) simultaneously lower bulk and contact resistance, establishing a zero-gap TIM design for heterogeneous integration [106].

The long-term reliability of thermal interface materials (TIMs) is governed by thermomechanical stresses, binder volatilization, interfacial crack formation, oxidation, humidity-driven softening, and microstructural rearrangements that collectively increase the effective thermal interface resistance $R_{\mathrm{TIM}}$. To explicitly quantify these mechanisms, we surveyed peer-reviewed experimental studies reporting changes in $R_{\mathrm{TIM}}$ or $Z_{\mathrm{th}}$ under controlled accelerated conditions. The resulting dataset (

Table 4. Quantitative literature values for degradation of thermal interface materials (TIMs) under accelerated thermal aging or thermal cycling. All values are extracted directly from peer-reviewed experimental studies. Normalized rates are computed by dividing the total percentage change by the duration/cycle count, providing the approximate change per ${10}^3$ h or ${10}^3$ cycles, as specifically requested by the reviewer.

TIM Type	Stress Condition	Mechanism	Measured Change in ${\mathit{R}}_{\mathbf{TIM}}$/${\mathit{Z}}_{\mathbf{th}}$	Normalized Rate	Ref.
Thermal paste (steel/ceramic stack)	$180°$C isothermal aging, 70 days (≈1680 h)	Binder dry-out, interfacial cracking	$Z_{\mathrm{th}}$ increased by ≈$300\%$ at $180°$C; unchanged at $60°$C	≈$+180\%$ per ${10}^3$ h (at $180°$C); $0\%$ per ${10}^3$ h (at $60°$C)	[108]
Thermal paste (Al/ceramic stack)	$180°$C aging, 70 days	Dry-out and loss of contact compliance	$Z_{\mathrm{th}}$ increased by >$185\%$	≳$+110\%$ per ${10}^3$ h	[108]
Ag-grease, Sn–3.5Ag solder, Sn foil (Cu/Cu)	$170°$C, 90 days (≈2160 h)	IMC formation, oxidation, voiding	Initial $R_{\mathrm{TIM}}$ advantage fully lost; becomes equal to bare Cu/Cu	≈$+50\%$ to $+70\%$ per ${10}^3$ h (TIM benefit erased)	[109]
Silicone pad/gel TIMs (multiple commercial)	$85°$C/85%RH for 2173 h; $125°$C for 1016 h	Moisture softening or polymer relaxation	At $85°$C/85%RH: change between $-40\%$ and $+4\%$; at $125°$C: $R_{\mathrm{TIM}}$ decreased ≈$14\%$	$-18\%$ to $+2\%$ per ${10}^3$ h (85 °C/85%RH); $-14\%$ per ${10}^3$ h (125 °C)	[110]
Filled silicone putty (“Putty B”)	Thermal cycling $-55/125°$C, 765 cycles	Cracking near $T_g$, filler migration	$R_{\mathrm{TIM}}$ increased by >$50\%$ after 765 cycles	≈$+65\%$ per ${10}^3$ cycles	[110]
Graphene epoxy composite TIM	Power cycling to $120°$C, up to 500 cycles	Filler network densification (beneficial)	Thermal conductivity increased by 15–$25\%$; $R_{\mathrm{TIM}}$ correspondingly reduced	≈$+30$–$50\%$ improvement per ${10}^3$ cycles	[111]

) spans polymer-based pastes, metallic and alloy TIMs, silicone pads and putties, and emerging high-k composite TIMs. Across this literature, thermal pastes aged at $180°$C exhibit severe degradation (∼185–300% increase in $Z_{\mathrm{th}}$), corresponding to normalized rates exceeding $+110$–$180\%$ per ${10}^3$ h. High-temperature metallic TIMs such as Ag-based greases, Sn–3.5Ag solders, and Sn foils similarly lose their initial thermal benefit over 90 days at $170°$C. In contrast, silicone pads subjected to humidity stress may soften and show reduced $R_{\mathrm{TIM}}$, whereas deep thermal cycling of filled putties produces more than 50% degradation over 765 cycles (∼$+65\%$ per ${10}^3$ cycles). Notably, high-k graphene–epoxy composites show improved thermal performance under cycling, with k increasing by 15–25% after 500 cycles due to filler-network densification. This quantitative comparison reveals the broad spread of TIM degradation rates and directly highlights the trade-off between initial thermal performance and long-term reliability across TIM chemistries.

2.2.3. Interposers and Heat Spreading

An interposer is an intermediary substrate, such as Si or glass, that redistributes I/O at a fine pitch between chiplets/dies and the package. It also provides short, dense wiring and vertical connections using TSV/TGV structures. It emerged in the 2000s with TSV-enabled 2.5D/3D integration, separating die technology from package limits and enabling heterogeneous integration [112]. In current systems, the interposer serves as both an electrical redistribution medium and a lateral thermal spreading plane, influencing junction temperatures and spatial gradients between chiplets.

A representative silicon interposer architecture highlighting redistribution layers, micro-bumps, through-silicon vias, and underfill regions is shown in Figure 7.

Types of Interposers

Three major interposer technologies have evolved:

• Silicon Interposers (TSV-Based): It dominates high-performance 2.5D integration (e.g., Xilinx FPGAs (Advanced Micro Devices, Inc., Santa Clara, CA, USA), GPUs with HBM) due to their fine wiring density (<1 µm L/S) and precise via formation [113,114]. Their thermal conductivity ($k_{\mathrm{Si}}\approx 120$–150 W·m⁻¹K⁻¹) enables adequate lateral heat spreading, although their coefficient of thermal expansion (CTE ≈ 2.6 ppm/K) mismatch with organic substrates causes warpage and stress [115]. TSVs introduce localized stress and anisotropy in heat conduction, which must be managed via via-pitch optimization and underfill design [116,117].
• Glass Interposers (TGV-Based): Low-cost, low-loss alternative to silicon [118,119,120]. Properties: excellent dimensional stability, smooth surface, scalable large-panel fabrication. Limitation: low thermal conductivity ($k_{\mathrm{glass}}\approx 1$ W·m⁻¹K⁻¹). Effect: 10–15 °C higher junction temperature [119]. Solution: use Cu planes or thermal vias. Advantages: low dielectric loss, good manufacturability [121].
• Organic and Fan-Out Interposers (TSV-less/“2.1D–2.3D”): Emerging organic bridge and fan-out redistribution layer (RDL) technologies eliminate TSVs altogether [122,123]. These interposers use thin polymer dielectrics and Cu redistribution networks on organic cores, offering superior CTE matching with PCB substrates (6–18 ppm/K) and lower cost. However, they suffer from poor through-thickness thermal conductivity and limited fine-pitch routing (∼2–3 µm L/S) [115]. Organic interposers and bridge solutions (e.g., Intel EMIB [124]) have proven capable of delivering high I/O bandwidths at lower cost and mechanical stress.

Normalized Lateral Temperature Rise Between Chiplets

Lateral thermal coupling is governed by the in-plane thermal conductivity and heat-spreading resistance of the interposer. The classical spreading-resistance formulation developed by Yovanovich [33] provides a widely used analytical basis:

$$R_{\mathrm{sp}}\approx {\displaystyle \frac{1}{4kt}}\left[1+{\displaystyle \frac{2}{\pi }}ln\left({\displaystyle \frac{L}{a}}\right)\right],$$

where k is the in-plane conductivity, t the interposer thickness, and $L/a$ a geometric factor. The temperature rise between chiplets follows directly:

$$\mathrm{\Delta }T=P{R}_{\mathrm{sp}}.$$

These expressions have been validated in multi-die thermal studies, including the compact and experimentally calibrated models reported by Poppe et al. [45]. Using published conductivities, Table 5 reports normalized $\mathrm{\Delta }T$ values for representative chiplets on each substrate type.

Thermal-Conductivity Anisotropy

Multilayer packaging materials, particularly polymer-based dielectrics and fan-out build-up structures, often exhibit strong anisotropy between in-plane and cross-plane conduction. Following conventional practice in thermal composite characterization [125], anisotropy is expressed as follows:

$$\gamma ={\displaystyle \frac{k_{\text{in-plane}}}{k_{\text{cross-plane}}}}.$$

As shown in Table 5, silicon is nearly isotropic, glass interposers show moderate anisotropy due to TGV/Cu integration, and organic/fan-out materials exhibit the highest anisotropy consistent with their Cu/polymer build-up structure.

CTE Mismatch and Warpage Susceptibility

Thermo-mechanical warpage is strongly influenced by the mismatch between the coefficient of thermal expansion (CTE) of silicon and the interposer material. The standard measure of mismatch is

$$\mathrm{\Delta }\alpha =\left|{\alpha }_{\mathrm{interposer}}-{\alpha }_{\mathrm{Si}}\right|,$$

which follows directly from Timoshenko’s foundational bi-material curvature theory [126], a cornerstone of packaging mechanics and thermal stress analysis [127,128]. Warpage curvature scales proportionally with mismatch, temperature excursion, and layer geometry:

$${\kappa }_{\mathrm{bend}}\propto {\displaystyle \frac{\mathrm{\Delta }\alpha \mathrm{\Delta }T}{t_{\mathrm{eq}}}}.$$

Table 6 summarizes verified CTE values, mismatches, and representative warpage magnitudes reported in reliability studies of glass and organic packaging structures [129,130].

By grounding thermal spreading, anisotropy, and thermo-mechanical mismatch in experimentally reported data and established analytical frameworks, this subsection provides a quantitatively normalized comparison across interposer technologies. These additions reinforce and extend the qualitative review by introducing the literature-verified metrics relevant for evaluating silicon, glass, and organic/fan-out interposers.

Table 5. Experimentally reported thermal properties for three interposer classes. $\mathrm{\Delta }T$ values are analytical estimates (this work) for two 20 × 20 mm chiplets at 80 W each, using published k values. Analytical estimates based on spreading-resistance scaling using the literature k values. Trends are consistent with detailed CFD studies [131].

Material	k (W/mK)	${\mathit{k}}_{\mathbf{in}}/{\mathit{k}}_{\mathbf{cross}}$	$\mathrm{\Delta }\mathit{T}$ (K) †	Ref.
Silicon	130–150	≈1	10–15 (est.)	[132]
Glass (TGV)	1.1–1.4 (bulk)	1.5–2.0	16–22 (est.)	[119,133,134]
Organic/Fan-out	0.3–0.6	2–3	24–32 (est.)	[125,135]

^†$\mathrm{\Delta }T$ values are analytical estimates based on spreading-resistance scaling for two 20 × 20 mm chiplets dissipating 80 W each, using literature thermal conductivity values.

Table 5. Experimentally reported thermal properties for three interposer classes. $\mathrm{\Delta }T$ values are analytical estimates (this work) for two 20 × 20 mm chiplets at 80 W each, using published k values. Analytical estimates based on spreading-resistance scaling using the literature k values. Trends are consistent with detailed CFD studies [131].

Material	k (W/mK)	${\mathit{k}}_{\mathbf{in}}/{\mathit{k}}_{\mathbf{cross}}$	$\mathrm{\Delta }\mathit{T}$ (K) †	Ref.
Silicon	130–150	≈1	10–15 (est.)	[132]
Glass (TGV)	1.1–1.4 (bulk)	1.5–2.0	16–22 (est.)	[119,133,134]
Organic/Fan-out	0.3–0.6	2–3	24–32 (est.)	[125,135]

^†$\mathrm{\Delta }T$ values are analytical estimates based on spreading-resistance scaling for two 20 × 20 mm chiplets dissipating 80 W each, using literature thermal conductivity values.

Table 6. CTE ranges, mismatch with silicon, and representative warpage magnitudes from the literature for advanced packaging structures.

Material	CTE (ppm/K)	$\mathrm{\Delta }\mathit{\alpha }$ vs. Si	Warpage ($\mathrm{\mu }$m)	Ref.
Silicon	2.6–3.0	0–0.4	<20	[132]
Glass (low-CTE)	3.0–10.0	0.7–2.4	30–70	[133]
Organic/Fan-out	10–20	7.4–17.4	50–150	[129,130,136]

Table 6. CTE ranges, mismatch with silicon, and representative warpage magnitudes from the literature for advanced packaging structures.

Material	CTE (ppm/K)	$\mathrm{\Delta }\mathit{\alpha }$ vs. Si	Warpage ($\mathrm{\mu }$m)	Ref.
Silicon	2.6–3.0	0–0.4	<20	[132]
Glass (low-CTE)	3.0–10.0	0.7–2.4	30–70	[133]
Organic/Fan-out	10–20	7.4–17.4	50–150	[129,130,136]

Comparative Thermal, Reliability, and Thermo-Economic Assessment

Table 7. Representative thermal conductivity ranges and reliability characteristics reported in the literature for major interposer types.

Interposer Type	Thermal Conductivity	Thermal Behavior	Reliability Notes
Organic (ABF/BT/LCP)	0.25–0.6	Highest spreading resistance; large lateral gradients	Mature substrate tech; CTE mismatch can raise warpage
Silicon TSV	120–150	Good lateral spreading; well-understood thermal paths	Extensive data on TSV stress and microbump fatigue
Glass TGV	0.8–1.4	Effective thermal path depends strongly on TGV density	Passed 500 TCT and 1000 h HTS in published studies
AlN/SiC ceramics	150–250	Reduced spreading resistance; good thermal stability	Brittle; CTE mismatch considerations
Cu–diamond composites	700–1000	Very high spreading capability	Interface reliability and cost challenges
CVD diamond	1500–2200	Exceptional heat spreading demonstrated in power modules	Bond integrity critical
BAs (cubic)	∼1300	Strong potential for spreading applications	Emerging material; limited packaging data
Microfluidic Si	120–150 + (liquid cooling)	∼40% interposer-temperature reduction vs. air cooling	Requires sealing, fluid compatibility, and microchannel reliability

and

Table 8. Quantified thermal benefits, CAPEX tiers, and OPEX impacts of representative interposer–cooling configurations. All numerical values are taken from peer-reviewed experimental work or validated industrial assessments. CAPEX tiers utilize cost analyses from the literature on glass, silicon, organic, ceramic, and microfluidic packaging.

Configuration	Measured Thermal Improvement ($\mathrm{\Delta }\mathit{T}$)	Pkg. CAPEX (Refs)	Cooling CAPEX	OPEX/Energy Impact (Validated)
Organic substrate + air cooling (baseline)	Baseline reference	Low [122,124]	Low	Baseline OPEX
Silicon interposer + air cooling	Few-K lower vs. organic/glass depending on die density(consistent across Si-interposer thermals)	Medium [114,115]	Low	Minor OPEX benefit from reduced fan/chiller demand
Glass interposer (TGV) + air or cold-plate cooling	Thermal behavior within a few kelvin of Si when TGV density is high	Low–Medium [118,119]	Medium	With cold plates: 10–20% OPEX/energy reduction [137]
Silicon interposer + cold-plate liquid cooling	Tens of kelvin lower junction temperature vs. air in high-power devices	Medium [114]	Medium	15–20% reduction in total data-centre energy/OPEX [137,138]
Hybrid (75% direct liquid cooling + 25% air)	Design-dependent $\mathrm{\Delta }T$; enables higher power density operation	Medium–High [139]	Medium–High	27% reduction in facility cooling power. 15.5% reduction in total-site OPEX [139]
Silicon interposer with embedded microfluidic cooling (in-interposer channels)	40.1% reduction in interposer temperature vs. air at equal heat flux [140], reinforced by [141]	High [140]	High	Higher OPEX savings expected than cold plates (not yet quantified in facility-scale public studies)

summarize the literature-reported thermal conductivities, spreading behavior, and reliability characteristics of major interposer materials, together with their experimentally demonstrated $\mathrm{\Delta }T$ improvements and associated CAPEX/OPEX trends.

Table 7 consolidates material-level attributes such as thermal conductivity, lateral-spreading effectiveness, CTE-driven warpage tendencies, and documented cycling or storage reliability. These values highlight the wide range of thermal and mechanical behaviors that arise across organic, silicon, glass, ceramic, and emerging high-k interposers.

Table 8 complements this by connecting measured thermal improvements to packaging and cooling CAPEX categories and to validated energy/OPEX reductions reported for advanced liquid-cooling deployments. Silicon and glass interposers paired with cold-plate cooling typically provide large junction–temperature reductions and 15–20% energy savings, while hybrid direct-liquid-cooling deployments achieve up to 27% reductions in cooling-power demand. Embedded microfluidic interposers deliver the highest reported thermal gains (e.g., 40.1% interposer-temperature reduction) at correspondingly higher CAPEX.

Together, these tables provide a compact quantitative basis for comparing interposers technologies and cooling strategies in terms of thermal performance, reliability, and economic impact.

Interposers function as both high-density electrical redistribution layers and lateral heat-spreading planes in advanced 2.5D and 3D heterogeneous packages. Their thermal behavior directly governs temperature uniformity across chiplets and thus affects both performance and reliability. Conventional silicon interposers ($k\approx 120$–150 $\mathrm{W}{\mathrm{m}}^{-1}{\mathrm{K}}^{-1}$) offer superior in-plane heat conduction compared to glass or organic substrates ($k\approx 0.3$–1 $\mathrm{W}{\mathrm{m}}^{-1}{\mathrm{K}}^{-1}$), yet still exhibit pronounced anisotropy due to metallization stacks and TSV networks that modulate effective in-plane and through-thickness conductivities [119,134,142]. Under non-uniform power maps typical of AI/HPC accelerators, such anisotropy introduces lateral spreading resistance that can drive double-digit inter-die temperature deltas at constant total package power [113,119,134].

Two primary methods for reducing lateral thermal gradients are gaining attention. The first is using interposers and substrates with higher thermal conductivity, such as SiC/AlN ceramics, composite materials, and new ultra-high-k options. Copper/diamond and metal–diamond composites can provide near-isotropic conduction with $k\sim 700$–$1200\mathrm{W}{\mathrm{m}}^{-1}{\mathrm{K}}^{-1}$ when interfacial thermal boundary resistance (TBR) is well controlled [143,144,145,146,147]. Polycrystalline and CVD diamond heat spreaders or interposers can exceed $1500\mathrm{W}{\mathrm{m}}^{-1}{\mathrm{K}}^{-1}$ but need good CTE matching and bonding to avoid stress and reliability issues [143,144]. Boron arsenide (BAs) is also emerging as a promising cooling substrate, with reported conductivities higher than diamond and initial device results [148,149].

The second method uses the interposer as an active thermal layer by adding microfluidic channels for localized cooling with little electrical impact. Silicon interposers with such cooling show substantial reductions in peak temperature and thermal gradients, supporting co-design for both electrical and thermal performance [112,140]. Glass interposers made by TGV processes are also improving for optical and mm-wave use. Though their intrinsic conductivity is low, metal planes, thermal vias, and local spreaders can partly recover lateral heat flow [118,142,150,151]. Choosing an interposer for AI/HPC depends on maximizing (i) conductivity and anisotropy in the plane and through the thickness, (ii) interfacial TBR, (iii) mechanical/CTE match, and (iv) cost and manufacturability. Combining advanced materials (diamond/BAs/composites) with fluidic cooling and thermal-aware design may considerably lower the temperature differences across chiplets and make them more reliable [119,134,140,143].

Table 9. Representative thermal and mechanical properties of interposer and substrate materials used in advanced packaging.

Material	Thermal Conductivity	CTE	Remarks
Organic (BT, ABF)	0.3–1	15–20	Low-cost, high anisotropy, poor thermal spreading
Glass	0.8–1.5	3–4	CTE match to Si; brittle; used in glass interposers
Silicon	148	2.6–3	Standard CoWoS/EMIB interposer material
Copper	385–410	16–17	Excellent heat spreader; CTE mismatch with Si
AlN ceramic	140–180	4.5–5	Electrically insulating; used in lids and substrates
SiC	120–270	4.0–4.5	High thermal conductivity; strong mechanical integrity
Cu-Mo composite	180–210	7–8	Balanced CTE for Cu-Si integration; good manufacturability
Cu-diamond composite	500–800	5–8	Very high k; limited manufacturability; tunable CTE match
Polycrystalline diamond	1000–2200	1–2	Highest k; excellent stability; high fabrication cost
Graphite (pyrolytic)	1000–1700 (in-plane)	1–2	Highly anisotropic; thin heat spreader in compact systems
CVD diamond-on-Si	800–1500	2.5–3	Promising hybrid interposer for next-generation HPC packaging

summarizes representative materials and their properties, illustrating the trade-offs between thermal performance, CTE alignment, and manufacturability. These data underscore that while high-k materials can substantially suppress lateral thermal gradients, their adoption requires careful co-optimization of thermal, mechanical, and economic constraints to ensure long-term package reliability and scalability.

2.2.4. Bonding

In semiconductor packaging, bonding means the processes that connect dies, packages, and substrates both mechanically and electrically, and now also thermally. It includes wire bonds, solder-based flip-chip connectors, thermocompression, through-silicon vias (TSVs), and direct metal/dielectric hybrid bonding utilized in fine-pitch 2.5D/3D integration and HBM [127,128,152].

Taxonomy of Bonding Types

• Wire bonding (thermosonic/ultrasonic): Mature, low-cost, and tolerant to topography; limited I/O density and longer interconnects increase parasitics and constrain heat removal [127,153]. A schematic illustration of the conventional wire-bonding process is shown in Figure 8.
• Solder bump (C4) and flip-chip reflow: Eutectic or Pb-free microbumps with self-alignment and strong manufacturing base; challenges include pitch scaling below ∼20–30 $\mathsf{\mu }$m, voiding, and thermal–mechanical fatigue of joints [154,155,156]. The flip-chip bonding configuration using solder microbumps is schematically illustrated in Figure 9.
• Thermocompression bonding (TCB): Solid-state joining of Cu/SnAg or Cu/Sn systems achieves finer pitch than reflow but narrows the process window and can exacerbate warpage [157,158,159,160].
• Cu–Cu direct (hybrid) bonding (W2W/D2W/D2D): Concurrent dielectric–metal bonding after planarization and activation enables ultra-fine pitch with low electrical and inter-tier thermal resistance, but is sensitive to surface planarity, Cu oxidation/protrusion, particles, and moisture, affecting interfacial reliability [79,80,161,162,163,164,165,166,167].
• Au–Au thermo-compression/direct bonding: Oxidation-resilient for heterogeneous stacks and MEMS; higher material cost and creep/interdiffusion considera-tions [168,169].
• Adhesive/NCF-assisted bonding: Polymer dielectrics co-cured with contacts (“under-fill-in-place”) boost throughput and gap filling; polymer thermal resistance and moisture uptake require careful design [167,170,171,172,173,174,175].

Evolution and Scaling Trends

Packaging has gone from wire-bonded 2D to flip-chip/WLCSP, then to 2.5D interposers, and now to full 3D-IC with TSVs. Right now, the focus is on hybrid bonding at a pitch of ≤10 $\mathsf{\mu }$m for bandwidth density and thermal routing in HBM/logic stacks. “Bumpless” ideas (BBCube, SoIC, and wafer-on-wafer/chip-on-wafer) shorten interconnects and lower interfacial thermal resistance, but they make it harder to prepare surfaces and keep bonds strong [176,177,178]. Architectural approaches like SMLA (Simultaneous Multi-Layer Access) put stress on thermal envelopes as stack heights rise [179,180].

A comparative overview of the major bonding technologies used in advanced and 3D packaging, highlighting their advantages, limitations, and reliability implications, is provided in

Table 10. Comparison of bonding types for 3D/advanced packaging.

Bonding Type	Advantages	Disadvantages	Ref.
Wire bond	Low cost and repairable	Long paths with higher $L/R/C$ and weaker thermal paths	[127]
Solder microbump	Mature and self-aligning	Pitch wall, joint fatigue/IMC growth, and thermal bottleneck at solder/UBM	[155,156]
TCB	Finer pitch	Pressure-induced warpage and tighter thermal budgets on BEOL/passivation	[157,158,159]
Cu–Cu hybrid bond	Lowest inter-tier $R_{\mathrm{th}}$ resistance	Planarity/particle sensitivity, Cu protrusion/stress, and moisture-related delamination	[79,80,161,162,163,167,181]
Au–Au bond	Oxidation robustness	High cost and limited ultimate I/O vs. Cu–Cu	[168]
Adhesive/NCF	High throughput and good shock compliance	Low polymer k and moisture management are critical	[170,172,173,174]

.

Materials and Interfacial Thermal Properties

Interfaces dominate cross-plane heat flow at submicron stand-off. Cu/Cu interfaces generally have higher interfacial conductance than Cu/Si or Cu/oxide; roughness, native oxide, and passivation layers reduce conductance [182,183]. Hybrid bonding achieves low inter-tier thermal resistance when Cu pad area fraction is high and dielectric gaps are minimized [79,161,162]. Engineered dielectrics (e.g., MgO ILD) trade isolation and cross-plane heat flow in hybrid-bonded stacks [184].

Polymers are thermal bottlenecks; composite fillers (h-BN, Al₂O₃, AlN) and aspect-ratio/functionalization tuning improve effective conductivity and can yield anisotropy while maintaining processability [173,174,175]. In HBM mold/underfill systems, Cu-Ni core-shell fillers can raise k and provide EMI shielding [185].

At the TSV/BEOL level, protrusion control via (111) nanotwinned Cu and bath chemistry mitigates stress while preserving vertical heat paths [186,187,188,189].

Recent Developments and Research Frontiers

Pitch scaling and “bumpless” stacking: BBCube/WOW/COW and C2W hybrid bonding target $<5\mathsf{\mu }$m pitch with improved thermal paths [176,180].

Low-temperature hybrid bonding: Surface activation + low-T anneals balance throughput and reliability for large die [164,165,166,190].

Thermal path engineering: Inter-die thermal benchmarking favors hybrid Cu/dielectric over via-last/dielectric bonds; knobs include Cu pad density, dielectric modulus, and interface cleanliness [79,161,162].

Advanced coolers for 3D IC: Through-chip microchannels, annular micro-pin fins, loop heat pipes, and vapor-chamber/liquid-fin sinks are moving on-package/on stack [191,192,193,194,195].

System-level management: Temperature-aware caching and scheduling, along with functional partitioning, reduce hotspot coincidence.

Interfacial physics: Renewed focus on Cu/Cu vs. Cu/Si interfacial conductance, oxide/roughness, and hydrogen/defect interactions for long-term stability [182,183].

Heterogeneous Integration and Market Developments

Commercial platforms translate bonding advances into productized HI. Intel’s EMIB embeds a small silicon bridge in an organic substrate to realize fine-pitch 2.5D links [124]. Foveros enables face-to-face logic stacking and, more recently, direct hybrid-bonded variants [15,196]. AMD’s 3D V-Cache stacks a 64 MB SRAM die onto a CPU CCD via hybrid bonding [197,198]. TSMC’s SoIC and Samsung’s X-Cube deploy wafer-/die-level hybrid bonding flows for logic and memory stacks [177,199]. These architectures illustrate the transition from discrete chiplet assembly toward truly monolithic 3D systems, driven by co-optimization of bandwidth, power, and form factor at production scale.

2.2.5. Substrates, Lids, and Reliability

In advanced 2.5D/3D systems, the substrate provides mechanical support, signal/power distribution, and a thermal return path, while the lid (cap) protects the die stack and spreads heat toward a sink or coolant. Organic BT/ABF laminates are prevalent for cost and dielectric reasons but exhibit low thermal conductivity ($k\sim 0.3$–3 W m⁻¹ K⁻¹). In contrast, ceramic/ceramic-composite options (Al₂O₃, AlN, SiC) and metal/composite lids (Cu, Cu-Mo, Cu-diamond) are used when higher heat fluxes and tighter thermomechanical budgets must be met [115,127].

Materials, usage, and effective heat spreading: Metal lids (Cu, Cu–Mo) and two-phase spreaders (vapor chambers, micro-channel lids) are widely adopted to homogenize die-level heat flux and reduce peak junction temperatures. Package-level coolers, such as vapor chambers and liquid-fin assemblies, have demonstrated significant reductions in in-plane thermal gradients, with system-level studies showing strong sensitivity to the lid/TIM/interposer stackup. Polymers used as TIMs/underfills are thermal bottlenecks. Still, they can be engineered via high k fillers (BN, Al₂O₃, AlN) to raise effective conductivity and, in some cases, induce anisotropy beneficial to lateral spreading.

CTE mismatch and stress/warpage: A dominant reliability driver is the coefficient of thermal expansion (CTE) mismatch between dissimilar layers (e.g., Cu ≈ 17 ppm K⁻¹, Si ≈ 2.6 ppm K⁻¹). Under a thermal excursion $\mathrm{\Delta }T$, the free thermal strain mismatch is

$$\epsilon =\mathrm{\Delta }\alpha \mathrm{\Delta }T,$$

Under bonding constraints, it produces interfacial shear/normal stresses, package warpage, and cyclic fatigue damage. In TSV/BEOL stacks, residual and cycling stresses can aggravate Cu protrusion, BEOL cracking, and delamination. Representative thermo-physical properties of commonly used cap and substrate materials, including thermal conductivity, elastic modulus, coefficient of thermal expansion, and the resulting mismatch strain relative to silicon, are summarized in Table 11.

Mitigations and design levers: (1) CTE tailoring: Cu–Mo composite lids and SiC/AlN substrates reduce $\mathrm{\Delta }\alpha$ versus pure Cu or organic laminates. (2) Interface engineering: high-conductivity TIMs and underfills with tuned modulus/CTE lower stress transfer while maintaining heat flow. (3) Hybrid bonding density and thermal path: increased Cu pad fraction and minimized dielectric gaps reduce inter-tier thermal resistance, easing package-level thermal budgets. (4) System cooling: vapor chambers, loop heat pipes, and liquid-fin sinks provide high effective spreading when integrated with lids/interposers. These choices must be co-optimized, as stiffer lids raise constraint forces (stress $\propto E\mathrm{\Delta }\alpha \mathrm{\Delta }T$) even while improving thermal spreading. To quantify the impact of cap and substrate selection on thermo-mechanical reliability, estimated peak stresses for representative material combinations under identical junction-to-case thermal resistance are compared in Table 12.

Takeaway: Substrate/lid choices are co-design variables linking thermal targets (junction-to-coolant resistance, hotspot smoothing) to mechanical integrity (warpage, interfacial durability). The detailed modeling of warpage mechanics and thermal–electrical co-optimization is deferred to later sections [115,200].

Table 11. Thermo-physical properties of representative cap and substrate materials, including reference sources. Mismatch strain is computed for $\mathrm{\Delta }T=80$ K relative to silicon.

Material	k (W/mK)	$\mathit{\alpha }$ (ppm/K)	E (GPa)	${\mathit{\epsilon }}_{\mathit{m}}$ (×10−3)	Ref.
Silicon (Si)	148	2.5	150	0.00	[201,202,203]
Copper (Cu)	397	16.7	126	1.14	[203]
Aluminium (Al)	155	22.8	69	1.62	[203]
Aluminum Nitride (AlN)	170	4.5	300	0.16	[204,205]
Silicon Carbide (SiC)	120–270	4.0–4.5	400	0.12–0.16	[206]
Cu–Mo composite	200–220	7.5–8.2	200–210	0.40–0.46	[207]
AlSiC (Al–SiC MMC)	170–200	6.5–7.0	170–200	0.32–0.36	[208]
SiC/Al MMC	160–240	6.0–7.0	190–210	0.30–0.36	[209,210,211]
Organic BT/ABF	0.3–3	12–18	20–25	0.76–1.24	[212,213]

Table 11. Thermo-physical properties of representative cap and substrate materials, including reference sources. Mismatch strain is computed for $\mathrm{\Delta }T=80$ K relative to silicon.

Material	k (W/mK)	$\mathit{\alpha }$ (ppm/K)	E (GPa)	${\mathit{\epsilon }}_{\mathit{m}}$ (×10−3)	Ref.
Silicon (Si)	148	2.5	150	0.00	[201,202,203]
Copper (Cu)	397	16.7	126	1.14	[203]
Aluminium (Al)	155	22.8	69	1.62	[203]
Aluminum Nitride (AlN)	170	4.5	300	0.16	[204,205]
Silicon Carbide (SiC)	120–270	4.0–4.5	400	0.12–0.16	[206]
Cu–Mo composite	200–220	7.5–8.2	200–210	0.40–0.46	[207]
AlSiC (Al–SiC MMC)	170–200	6.5–7.0	170–200	0.32–0.36	[208]
SiC/Al MMC	160–240	6.0–7.0	190–210	0.30–0.36	[209,210,211]
Organic BT/ABF	0.3–3	12–18	20–25	0.76–1.24	[212,213]

Table 12. Estimated peak thermo-mechanical stress at $T_{\mathrm{j}}=105°\mathrm{C}$ ($\mathrm{\Delta }T=80$ K) for equal junction-to-case thermal resistance $R_{\theta ,\mathrm{JC}}$. Values calibrated using FE-based stress–temperature trends and experimentally measured material properties.

Configuration (Cap/Substrate)	Stress (MPa)	Normalized	Reference
Cu lid/Organic substrate	∼110	1.00	[211]
Cu lid/AlN substrate	80–90	0.70–0.80	[204,211]
Al lid/Organic substrate	∼85	0.77	[203,211]
SiC–Al composite lid/Organic substrate	∼67	0.61	[210]
Cu–Mo lid/Organic substrate	60–70	0.55–0.65	[207,211]
Cu–Mo lid/AlN substrate or SiC–Al lid/AlN substrate	45–55	0.40–0.50	[204]

Table 12. Estimated peak thermo-mechanical stress at $T_{\mathrm{j}}=105°\mathrm{C}$ ($\mathrm{\Delta }T=80$ K) for equal junction-to-case thermal resistance $R_{\theta ,\mathrm{JC}}$. Values calibrated using FE-based stress–temperature trends and experimentally measured material properties.

Configuration (Cap/Substrate)	Stress (MPa)	Normalized	Reference
Cu lid/Organic substrate	∼110	1.00	[211]
Cu lid/AlN substrate	80–90	0.70–0.80	[204,211]
Al lid/Organic substrate	∼85	0.77	[203,211]
SiC–Al composite lid/Organic substrate	∼67	0.61	[210]
Cu–Mo lid/Organic substrate	60–70	0.55–0.65	[207,211]
Cu–Mo lid/AlN substrate or SiC–Al lid/AlN substrate	45–55	0.40–0.50	[204]

2.3. Classification of Cooling Technologies

Managing heat in advanced 2.5D and 3D chiplet packages means finding the right balance among high power density, small sizes, and manufacturing constraints. The chosen cooling method affects the junction-to-coolant thermal resistance ($R_{\theta ,\mathrm{jc}}$), reliability, and overall package performance. Recent studies highlight embedded liquid-cooling methods such as microchannels, pin fins, and jet impingement, as these approaches reduce spreading resistance and help avoid bottlenecks between stacked dies and interposers [55,161,162,214].

An overview of the major air, liquid, and two-phase cooling approaches used in electronic packages is illustrated in Figure 10, while a quantitative comparison of these cooling technologies in terms of supported power, thermal resistance, relative cost, and practical constraints is summarized in

Table 13. Comparative assessment of mainstream and advanced cooling technologies used in modern high-power AI/HPC packages. The table highlights supported power envelopes, thermal-resistance ranges, cost scaling relative to air cooling, and compatibility with current accelerator platforms, along with the dominant constraints that limit each cooling method at elevated heat fluxes.

Cooling Technology	Supported Power	Typical Thermal Resistance (°C·cm2/W)	Relative Cost	Common Platforms	Key Limitations
Air Cooling	<500 W	>$0.21$	1×	Mainstream CPUs; low-to-mid power GPUs	High acoustic output; inadequate for elevated heat fluxes
Vapor chamber (two-phase spreader)	400–800 W	0.10–0.18	2–2.5×	High-end CPUs; gaming GPUs; compact accelerators	Orientation sensitivity; spreading limit at very high heat flux
Cold-Plate Liquid Cooling	500–1000 W	0.1–0.2	2–4×	B200/B300 (Blackwell)–class accelerators	Interface resistance can be significant; temperature spread across the module can be non-uniform
Jet-impingement cooling	1200–2500 W	0.03–0.08	4–6×	High-flux AI GPUs; power semiconductor modules	Complex manifolds; high pump head; erosion/flow-instability risk
MLCP (Micro-Channel Liquid Cooling Plate)	>2000 W	<$0.05$	6–10×	Rubin and Feynman–class AI GPUs	Manufacturing complexity; potential leakage concerns; higher overall system cost

.

2.3.1. Air Cooling and Finned Heat Sinks

Air cooling remains the most prevalent thermal management approach for cost-sensitive or moderate-power electronic systems due to its simplicity and low cost. However, its performance is constrained by relatively low convective heat transfer coefficients, typically in the range of $h\approx 10$–$200\mathrm{W}{\mathrm{m}}^{-2}{\mathrm{K}}^{-1}$ under forced convection, depending on fin geometry and air velocity [215,216]. For a plate-fin heat sink, the overall base-to-air thermal resistance can be approximated as follows:

$$R_{\theta ,\mathrm{sink}\to \mathrm{air}}={\displaystyle \frac{1}{h({\eta }_f{A}_{\mathrm{fin}}+A_{\mathrm{base}})}},$$

(13)

where ${\eta }_f$ denotes the fin efficiency, accounting for the temperature gradient along the fin height. This expression assumes uniform heat transfer and neglects spreading resistance effects in the base, which become significant for dense fin arrays or nonuniform heating [72,217].

Design Considerations

Optimization of air-cooled heat sinks involves careful balancing of fin height, thickness, spacing, and flow velocity to minimize $R_{\theta }$ while controlling pressure drop and acoustic noise. Parametric and CFD-based studies have demonstrated that modest variations in fin spacing and thickness can yield measurable improvements in overall heat transfer performance [217,218]. Enhanced fin geometries, such as filleted or tapered profiles, further reduce flow separation and improve fin efficiency, though at the cost of manufacturability complexity [218]. Hybrid designs incorporating copper foam or internal turbulence promoters (e.g., twisted inserts) have been explored to enhance effective surface area and turbulence intensity [219], achieving heat transfer coefficients up to 20–30% higher than those of conventional straight fins.

Performance Envelope

Air-cooled heat sinks usually handle up to about 150 to $200\mathrm{W}$ per module before airflow and size limits prevent further improvement [215]. After this point, much higher air speeds are needed, which increase fan power and noise but provide little benefit. Studies comparing plate-fin and pin-fin heat sinks show that plate-fin heat sinks perform better under forced convection when the base area is the same. Pin-fin designs, on the other hand, allow for more even airflow in all directions and are lighter [216,220].

Advantages and Limitations

Air cooling is simple, affordable, and mechanically reliable. Still, its low heat transfer, uneven temperature distribution, and reliance on airflow and fan design limit its use in high-power systems like AI or HPC processors. Because of these challenges, air cooling is now often used as a starting point or combined with liquid or two-phase cooling in newer platforms.

2.3.2. Heat Pipes and Vapor Chambers

Fundamentals and Transport Limits

Passive, two-phase heat transport using capillary-driven devices known as heat pipes started in the early 1960s. Not long after, these systems were adopted for thermal control in spacecraft [221,222,223,224]. A vapor chamber, or VC, is a flat type of heat pipe. It is mainly used to spread heat laterally rather than to move it in a single direction [225,226]. A VC consists of a sealed, evacuated enclosure containing a porous wick saturated with a working fluid. Heat applied to the evaporator surface causes liquid to evaporate; the generated vapor expands through the central core toward the condenser, where it releases latent heat and condenses. The condensate is returned to the evaporator by capillary pumping in the wick, closing a passive, steady-state cycle [223,226].

To maintain system operation, the capillary pressure generated by the wick must exceed all pressure losses in the liquid and vapor phases, as well as gravity-induced losses:

$$\mathrm{\Delta }{p}_{\mathrm{cap}}\ge \mathrm{\Delta }{p}_{\ell }+\mathrm{\Delta }{p}_v+\mathrm{\Delta }{p}_g,\mathrm{\Delta }{p}_{\mathrm{cap}}={\displaystyle \frac{2\sigma cos\theta }{r_{\mathrm{eff}}}},$$

(14)

where $\sigma$ is the liquid–vapor surface tension, $\theta$ the contact angle, and $r_{\mathrm{eff}}$ the effective pore radius of the wick [222,223]. The liquid pressure drop in the porous wick follows Darcy’s law for laminar flow through porous media,

$$\mathrm{\Delta }{p}_{\ell }={\mu }_{\ell }{\displaystyle \frac{L_{\ell }}{K}}{\displaystyle \frac{{\dot{m}}_{\ell }}{{\rho }_{\ell }{A}_{\mathrm{wick}}}},$$

(15)

with ${\mu }_{\ell }$ the liquid viscosity, K the permeability, $L_{\ell }$ the flow length, and $A_{\mathrm{wick}}$ the wick flow area [224].

For the vapor core, assuming laminar, incompressible, plane-Poiseuille flow between parallel plates (an accepted first-order model for thin, vast chambers) gives a relation $Q\propto H^3(\mathrm{\Delta }{p}_v/L)$; for constant mass flow, $\mathrm{\Delta }{p}_v\propto 1/H^3$ [226]. Hence, reducing the vapor-core height in ultra-thin VCs markedly increases viscous pressure losses and lowers the capillary transport limit. Under these approximations, the gravitational effects $\mathrm{\Delta }{p}_g$ may be negligible in horizontal or microgravity configurations, but are included here for completeness.

The overall thermal resistance can be expressed as a series sum of component resistances,

$$R_{\mathrm{tot}}=R_{\mathrm{evap}}+R_{\mathrm{vapor}}+R_{\mathrm{cond}}+R_{\mathrm{walls}}+R_{\mathrm{interfaces}},$$

(16)

consistent with standard heat-pipe and vapor-chamber resistance-network models [223]. The corresponding effective (or apparent) thermal conductivity,

$$k_{\mathrm{eff}}={\displaystyle \frac{L}{A}}{\displaystyle \frac{Q}{\mathrm{\Delta }T}},$$

(17)

Reported experimental values for heat pipes and vapor chambers typically range from several hundred to several thousand $\mathrm{W}{\mathrm{m}}^{-1}{\mathrm{K}}^{-1}$, and may approach or modestly exceed that of copper under optimal conditions, generally by less than one order of magnitude [224,225,226].

A cross-sectional schematic of the vapor-chamber structure and the associated two-phase heat-spreading pathways is shown in Figure 11.

Historical Foundations and Early Modeling

Early analytical and experimental work established the theoretical framework for two-phase capillary transport. Katzoff [221] documented one of the first quantitative models of vapor-flow pressure drop and sonic limits in aerospace heat pipes, while subsequent NASA programs detailed practical designs and reliability criteria for long-duration operation in microgravity [222,223].

Prasher [228] advanced the field by formulating a unified conduction-analogy model that quantitatively links the thermal performance of heat pipes and vapor chambers within a single mathematical framework. His model treats the vapor core as an equivalent thermal conductor characterized by an effective thermal conductivity, $k_{\mathrm{eff}}$, defined from the steady-state energy balance as

$$Q=k_{\mathrm{eff}}A{\displaystyle \frac{\mathrm{\Delta }T}{L}},$$

(18)

where Q is the total heat transport rate, A is the effective cross-sectional area, and L is the transport length between the evaporator and condenser sections. By correlating $k_{\mathrm{eff}}$ to the vapor mass flow rate $\dot{m}$ and latent heat of vaporization $h_{fg}$,

$$k_{\mathrm{eff}}={\displaystyle \frac{\dot{m}{h}_{fg}L}{A\mathrm{\Delta }T}},$$

(19)

The model captures the latent heat-driven phase-change transport through a conduction-equivalent framework that can be directly implemented in finite-element or finite-volume solvers. This simplification enables rapid design-sensitivity and parametric analyses for electronic cooling configurations without the need for full two-phase flow simulations. Validation against experimental data demonstrated that the predicted effective thermal resistance agreed within approximately 10–15% of measured values for heat fluxes up to 100 W/cm², confirming the robustness of the conduction-based approximation for both cylindrical heat pipes and planar vapor chambers.

In one of the numerical investigations of vapor-chamber behavior, Koito et al. [227] developed an axisymmetric two-phase model to describe coupled thermal–fluid transport within a flat, disk-type vapor chamber. Their formulation incorporated vapor, liquid-wick, and solid-wall regions, with the continuity, momentum, and energy equations for each phase solved using the SIMPLE algorithm. This work represented an early effort to resolve the internal distributions of velocity, pressure, and temperature in vapor chambers through direct numerical simulation. The authors demonstrated that, under typical operating conditions ($q=24\mathrm{W}{\mathrm{cm}}^{-2}$, $T_{\mathrm{air}}=25°\mathrm{C}$), vapor pressure variations were minimal ($\mathrm{\Delta }{p}_v\approx 3.4\mathrm{Pa}$), and circulation of the working fluid was sustained primarily by capillary forces within the sintered copper wick (porosity $\approx 0.40$) and a central wick column of radius $4.3\mathrm{mm}$. Comparison with experimental temperature measurements showed good agreement, validating the model and establishing a foundational framework for subsequent thermal–fluid modeling of vapor-chamber heat spreaders.

Design Evolution and Experimental Studies

Wong et al. [229] proposed a novel vapor chamber (VC) design in which a parallel-grooved top plate replaced the conventional wick-covered top condenser wall with inter-groove openings. The peaks of the groove walls were in direct thermal contact with the sintered wick layer on the bottom plate, so that the grooves simultaneously served as vapor channels, condensation surfaces, and mechanical stiffeners, eliminating the need for internal support studs. This configuration enhanced condensate return and reduced the liquid-flow resistance $R_{\ell }$, resulting in a total vapor chamber thermal resistance $R_{\mathrm{vc}}$ ranging from approximately $0.08\mathrm{K}/\mathrm{W}$ to $0.04\mathrm{K}/\mathrm{W}$ for heat inputs Q = 80–460 W, corresponding to heat fluxes up to about $120{\mathrm{W}/\mathrm{cm}}^2$. The improvement stemmed primarily from reduced liquid-flow resistance and improved heat transport coupling between the evaporator and condenser, rather than from a quantified reduction in vapor-flow resistance.

Tang et al. [230] proposed a multi-artery vapor chamber architecture that integrates sintered copper-powder rings surrounding solid copper columns to serve as arterial liquid channels. These porous rings establish direct hydraulic linkage between the condenser and evaporator wicks, thereby minimizing the effective liquid return path $L_{\ell }$ and reducing the total capillary pressure loss,

$$\mathrm{\Delta }{P}_{\mathrm{cap}}\propto {\displaystyle \frac{\sigma }{r_{\mathrm{eff}}}}-{\rho }_{\ell }g{L}_{\ell }.$$

This configuration enhances the maximum capillary supply limit $Q_{\max }$, ensuring continuous liquid replenishment at the evaporator surface. Experimental results demonstrated a substantial increase in the critical heat flux, with no capillary or boiling limit observed up to $q^{″}=300\mathrm{W}/{\mathrm{cm}}^2$, validating the efficacy of the multi-artery design.

Peng et al. (2013) [231] developed an aluminum flat-plate heat pipe integrating perforated fins brazed within a vapor chamber (VC) to enhance internal vapor–liquid interaction and convective surface area. The study analyzed the effects of working fluid, filling ratio, and vacuum degree on the steady-state temperature distribution and thermal resistance, demonstrating improved heat transport under optimized conditions. Although the configuration exhibited reduced thermal resistance ($R_{\mathrm{th}}=\mathrm{\Delta }T/Q$), the authors did not explicitly quantify fin efficiency (${\eta }_f$) or the thermal spreading factor; the improvements were inferred from the measured temperature uniformity across the condenser surface.

Tsai et al. [232] conducted an experimental investigation on vapor-chamber (VC) heat spreaders to analyze their thermal performance and validate design evolution through empirical measurements. They formulated the total thermal resistance of the vapor chamber, $R_{\mathrm{vc}}$, as the sum of one-dimensional (through-thickness) conduction and in-plane spreading components, expressed as

$$R_{\mathrm{vc}}=R_{1\mathrm{D}}+R_s.$$

This decomposition was supported by experimental results that showed strong agreement with theoretical heat-spreading models. Furthermore, their findings revealed that the spreading resistance $R_s$ is the dominant contributor to the overall thermal resistance, providing insight for subsequent design optimization of vapor-chamber heat spreaders in practical applications.

Characterization and Scaling Challenges

Weibel and Garimella [226] provided a comprehensive review of transport processes within vapor chambers, showing that the coupled effects of capillarity, viscous pressure losses, and interfacial heat and mass transfer govern performance. As vapor chambers are miniaturized to sub-millimeter thicknesses, the viscous pressure drop in the confined vapor core increases markedly, while the available capillary pumping pressure within the wick decreases. Their analysis further indicates that liquid-vapor interfacial resistances arising from phase-change kinetics at the evaporator and condenser surfaces become a significant contributor to the overall thermal resistance in ultra-thin configurations. They recommend integrated, multi-scale modeling approaches that couple vapor flow, liquid return, and interfacial heat transfer processes to predict dry-out and temperature non-uniformities accurately.

Bulut et al. [225] conducted a detailed survey of more than fifty experimental and numerical investigations of vapor chambers for electronics cooling. Their review shows that reported equivalent or “effective” thermal conductivities span roughly ${10}^3$–${10}^4$ W m⁻¹ K⁻¹, depending on wick morphology, permeability, working fluid, and geometric configuration. They attribute this wide range primarily to variations in wick microstructure and vapor-core geometry, as well as to differences in measurement procedures. The review emphasizes that minimizing vapor pressure drop, optimizing wick permeability, and reducing interfacial resistance are key strategies to maintain uniform temperature distributions and enhance heat-transport capacity in compact, high-heat-flux vapor chambers.

Hybrid and Integrated Systems

Hybrid thermal management architectures integrating vapor chambers (VCs), heat pipes (HPs), and phase change materials (PCMs) have been explored to exploit both latent heat storage and high in-plane conductivity.

Ghanbarpour et al. [233] numerically analyzed distinct PCM-filled and VC-based heat sinks under natural and forced convection. Their results showed that PCMs effectively damp transient temperature excursions during melting, while VCs maintain a lower steady-state thermal resistance $R_{\mathrm{th}}$, achieving a ∼$25\%$ lower $\mathrm{\Delta }T$ than PCM-only designs.

Muneeshwaran et al. [234] experimentally demonstrated a VC base with embedded cylindrical HPs and parallelogram fins, reducing $R_{\mathrm{th}}$ by up to 61% relative to a flat plate and enhancing base-to-fin temperature uniformity through two-dimensional vapor spreading and axial HP conduction.

Wang et al. [235] developed an integrated VC–HP module incorporating sintered copper-powder wicks and radial vapor–liquid coupling channels. The device sustained capillary-driven liquid return under anti-gravity conditions, maintaining $R_{\mathrm{th}}\approx 0.157\mathrm{K}{\mathrm{W}}^{-1}$, though orientation dependence remained due to gravity-assisted return in upright operation.

Collectively, these studies delineate complementary integration mechanisms rather than a single PCM–VC hybrid with orientation-independent behavior.

Representative transport metrics and limiting mechanisms reported for conventional vapor chambers and flat heat pipes are summarized in

Table 14. Representative transport metrics for conventional vapor chambers and flat heat pipes. Values are extracted from Wong et al. [229], Tang et al. [230,236], Tsai et al. [232], Varol et al. [237], and Zhao et al. [238]. All data correspond to near-optimal operating conditions reported experimentally. The limiting mechanism is identified based on observed dry-out, boiling, or vapor-flow constraints.

Study Device	Thickness [mm]	Footprint [mm2]	Heat Load	${\mathit{R}}_{\mathbf{tot}}$ [K/W]	Peak $\mathrm{\Delta }\mathit{T}$ [K]	Limit Mechanism	Orientation Sensitivity
Grooved Cu VC [229]	3.0	$50\times 50$	$Q=80$–460 W; $q^{″}\le 120\mathrm{W}/{\mathrm{cm}}^2$	0.08–0.04	2–4	None observed; capillary limit not reached	Weak (0–45°)
Multi-Artery VC [230,236]	3.0–4.0	$40\times 40$	$q^{″}$ up to $300\mathrm{W}/{\mathrm{cm}}^2$	∼$0.10$	3–5	No boiling/dry-out up to 300 W/cm2	Negligible
Sintered Cu VC [232]	2.5–3.0	40–60 mm side	Q up to ∼150 W	0.10–0.20	2–6	Spreading-dominated; capillary limit high	Moderate tolerance
Partially Heated VC [237]	3.0	$56\times 56$	$Q=25$–87 W	0.24 @ 87 W	3–5	Local flux sensitivity; no dry-out	Very weak (0–90°)
PEMFC-integrated VC [238]	∼2.0	$50\times 50$ active area	Stack heat ∼100 W	<$0.20$	<3	Capillary margin large; stable two-phase flow	Minimal

.

A corresponding set of performance metrics and transport limitations for ultrathin vapor chambers and ultra-thin flat heat pipes is provided in

Table 15. Representative performance metrics and transport limitations for ultrathin vapor chambers (UTVCs) and ultra-thin flat heat pipes (UFHPs). Data drawn from Shi et al. [239], Chen et al. [240], Gu et al. [241], and baseline comparisons from Bulut et al. [225] and Weibel and Garimella [226]. Area-normalized conductance $G_A=k_{\mathrm{eff}}/t$ highlights the performance advantage of UTVCs.

Device	Thickness t [mm]	Vapor Height H [mm]	${\mathit{k}}_{\mathbf{eff}}$	${\mathit{G}}_{\mathit{A}}$	${\mathit{R}}_{\mathbf{tot}}$ [K/W]	Dominant Limit	Comments
Baseline Conventional VC  [225,226]	3.0	1.0	$3\times {10}^3$–$7\times {10}^3$	1.0–2.3	0.05–0.20	Capillary or spreading	$\mathrm{\Delta }{p}_v\ll \mathrm{\Delta }{p}_{\mathrm{cap}}$; thick devices
Shi et al. (UFHP) [239]	0.65	0.20	$\mathcal{O}\left({10}^3\right)$	∼$1.5$	$\mathcal{O}\left(1\right)$ (est.)	Vapor-pressure limit emerging	$\mathrm{\Delta }{p}_v$ increases $\sim 125\times$ vs. 1 mm VC; good uniformity at low–mid flux
Chen et al. (Coplanar UTVC) [240]	0.27	0.10–0.15	>$1\times {10}^4$	>37	≈$0.08$	Interfacial + wick; vapor loss mitigated	Ultra-thin, high $G_A$; vapor-path shortening offsets $H^{-3}$ penalty
Gu et al. (AM Al VC with Gyroid Wick) [241]	2.0–3.0	∼$1.0$	$(1$–$2)\times {10}^4$ (peak)	3–5	∼10–20% lower vs. machined VC	Enhanced capillary head	Gyroid lattice offers high porosity, tuned permeability
Industrial-Class UTVC (typ.)	0.30–0.50	0.10–0.20	${10}^4$ (est.)	10–25	0.1–0.2 (est.)	Vapor-pressure sensitivity	Used in smartphones; strong performance at thin form factors

.

Ultra-Thin Vapor Chambers (UTVCs): Transport Limits and Comparison with Conventional VCs

Chen et al. [240] introduced a coplanar UTVC architecture with total thickness $t\approx 0.27\mathrm{mm}$, wherein vapor channels and liquid-return paths are placed on the same lateral plane. This geometry minimizes the effective vapor-flow length $L_v$, substantially reducing $\mathrm{\Delta }{p}_v$ despite the very small vapor-core height. The device achieves an effective thermal conductivity exceeding $k_{\mathrm{eff}}>{10}^4\mathrm{W}{\mathrm{m}}^{-1}{\mathrm{K}}^{-1}$, corresponding to an area-normalized thermal conductance $G_A=k_{\mathrm{eff}}/t\gtrsim 3.7\times {10}^7\mathrm{W}{\mathrm{m}}^{-2}{\mathrm{K}}^{-1}$, and a minimum through-thickness thermal resistance of $R_{\mathrm{tot}}\approx 0.08\mathrm{K}/\mathrm{W}$. These values place Chen et al.’s UTVC an order of magnitude above the $G_A$ range typically observed in millimeter-scale copper VCs ($G_A\approx 1$–$2.3\mathrm{MW}{\mathrm{m}}^{-2}{\mathrm{K}}^{-1}$), as summarized in Table 14.

Shi et al. [239] fabricated an ultra-thin flat heat pipe (UFHP) incorporating a ∼$0.20\mathrm{mm}$ vapor core within an overall stack thickness of $t\approx 0.65\mathrm{mm}$. The $76\times 46{\mathrm{mm}}^2$ steam chamber is formed using copper foils, a fine wire-mesh wick, and internal posts to prevent mechanical collapse. Under optimized filling and horizontal operation, the device maintained excellent isothermality, with surface temperature non-uniformity $\mathrm{\Delta }{T}_{\mathrm{surf}}\lesssim 2°\mathrm{C}$ at multi-watt heat inputs. Numerical analyses of the same architecture indicate that reducing the vapor-core height to $H\approx 0.20\mathrm{mm}$ sharply increases the viscous vapor pressure drop, consistent with the Weibel–Garimella scaling $\mathrm{\Delta }{p}_v\propto H^{-3}$. Reducing H from $1\mathrm{mm}$ (typical of conventional VCs) to $0.2\mathrm{mm}$ increases $\mathrm{\Delta }{p}_v$ by a factor of ∼125 for the same mass flux, causing axial vapor-temperature gradients and approaching the capillary limit at elevated heat flux. This behavior is reflected in the limiting-mechanism classification in Table 15.

MEMS-compatible UTVC designs continue to mature. Filippou et al. [242] and Tang et al. [236] review thin-film wick architectures, porous microstructures, and hermetic bonding schemes enabling sub-millimeter vapor chambers. Additively manufactured (AM) geometries also expand UTVC design space: Gu et al. [241] demonstrated aluminum VCs with gyroid-lattice wicks, achieving significant reductions in overall thermal resistance relative to conventionally machined references.

Quantitative Comparison with Conventional Vapor Chambers

Table 14 and Table 15 summarize representative transport limits in conventional ($t\sim 2$–$3\mathrm{mm}$) and ultra-thin ($t\sim 0.27$–$0.65\mathrm{mm}$) vapor chambers. Conventional VCs from Wong et al. [229], Tang et al. [230,236], and Tsai et al. [232] exhibit $R_{\mathrm{tot}}\approx 0.04$–$0.2\mathrm{K}/\mathrm{W}$ and typically remain capillary-limited with substantial margin; vapor-flow pressure drop is negligible because $H\sim 1\mathrm{mm}$. Moreover, orientation sensitivity is weak: Varol et al. [237] and Zhao et al. [238] observe little variation in $R_{\mathrm{VC}}$ over $0°$–$90°$ tilt.

In contrast, UTVCs provide 10–20× higher area-normalized thermal conductance ($G_A$) than conventional VCs of identical footprint, primarily due to their 3–10× smaller thickness. However, the reduced vapor-core height ($H\sim 0.1$–$0.2\mathrm{mm}$) introduces significant $\mathrm{\Delta }{p}_v$ penalties that must be mitigated through (i) shortened vapor-flow paths, (ii) high-capillarity composite wicks, and (iii) minimized interfacial resistances. The coplanar architecture by Chen et al. demonstrates that when these constraints are jointly optimized, UTVCs can achieve $R_{\mathrm{tot}}$ comparable to the best millimeter-scale VCs while maintaining a sub-0.3 mm profile. Thus, UTVCs excel in applications requiring extremely small vertical form factors and high in-plane spreading, provided the geometry suppresses vapor-pressure-induced limitations that would otherwise dominate at ultrathin scales.

Industrial Translation: iPhone 17 Pro Vapor Chamber

The 2025 iPhone 17 Pro (Apple, Inc., Cupertino, CA, USA) introduces an ultrathin, laserwelded vapor chamber integrated directly into the aluminium frame. Public teardown analyses indicate that a sealed two-phase cavity containing deionised water is bonded to the forged-aluminium unibody, enabling in-plane heat spreading from the A19 Pro SoC via a flattened vapor chamber structure [243]. Because Apple has not released device-level thermal resistance, maximum heat-load capability, or hot-spot temperature data, this example is used strictly as qualitative industrial evidence rather than quantitative validation.

A representative teardown image illustrating the integration of a smartphone-class vapor chamber is shown in Figure 12.

Quantitative metrics (

Table 16. Representative experimental studies of ultra-thin vapor chambers (UTVCs), summarizing form factor, wick structure, and quantitative thermal performance metrics.

Study	Thickness	Footprint	Wick Type	Max Power (W)	Key Metrics	Ref.
Zhang et al. (2024)	0.39 mm	82 × 58 mm	Cu mesh + SWM	26	$k_{\mathrm{eff}}\approx 3.84\times {10}^3$ W m−1 K−1	[245]
Chen et al. (2022)	–	UTVC survey	Various	∼90	$R_{\mathrm{th}}\sim 0.12$ K/W; $k_{\mathrm{eff}}>1.3\times {10}^4$ W m−1 K−1	[240]
Cao et al. (2024)	∼1.0 mm	Compact	Cu mesh + microgrooves	90	$R_{\mathrm{th}}=0.175$ K/W; $k_{\mathrm{eff}}\sim 1.42\times {10}^3$ W m−1 K−1	[246]

) for ultra-thin vapor chambers (UTVCs) with smartphone-class footprints are available from peer-reviewed sources. Zhang et al. [245] report a $0.39$ mm thick UTVC (82 mm × 58 mm) using a composite coppermesh and spiralwoven wick, achieving an effective thermal conductivity of $\sim 3.84\times {10}^3$ W m⁻¹ K⁻¹ and a maximum power of 26 W. Chen et al. [240] demonstrate that optimized UTVCs can reach thermal resistances as low as $0.12$ K W⁻¹ and effective conductivities exceeding $1.3\times {10}^4$ W m⁻¹ K⁻¹ for heat loads up to 90 W. Similarly, Cao et al. [246] report a composite-wick UTVC of approximately 1 mm thickness achieving a thermal resistance of $0.175$ K W⁻¹ at 90 W.

Accordingly, the iPhone 17 Pro is excluded from all quantitative comparison charts in this review. All quantitative analyses herein rely solely on experimentally validated, peer-reviewed data.

Quantitative performance metrics for representative ultra-thin vapor chambers with smartphone-class form factors, including thickness, footprint, wick structure, and thermal figures of merit, are summarized in Table 16.

Over six decades of development, vapor chambers have evolved from spacecraft heat pipes [221] into ultra-thin, additively manufactured, and hybrid PCM-integrated devices. Continued advancements focus on reducing vapor-flow resistance, enhancing wick capillarity, and preserving mechanical stability at minimal thicknesses. Emerging designs featuring bioinspired and coplanar wicks, PCM–VC hybrids, and direct structural integration highlight the maturity and adaptability of vapor-chamber technology for high-heat-flux thermal management applications.

2.3.3. Single-Phase Liquid Cold Plates (LCPs)

Single-phase liquid cold plates (LCPs) are compact heat exchangers that move coolant through internal channels, such as straight, manifolded, pin-fin, or jet/impingement-assisted designs, closely connected to high-heat-flux components. They are used in data centers and advanced semiconductor packaging because they transfer heat more effectively than air and fit well in servers and racks. In data centers, water or water–glycol mixtures are most common for their thermal properties, but it is important to consider corrosion, scale, and material compatibility when choosing and treating these fluids [247].

The idea of near-junction, single-phase microchannel cooling began with the work of Tuckerman and Pease [51]. Their etched-silicon microchannel heat sink (width $\approx 50\mathsf{\mu }$m, depth $\approx 300\mathsf{\mu }$m) achieved steady heat fluxes approaching $790\mathrm{W}{\mathrm{cm}}^{-2}$ with water at a pressure drop of roughly $213\mathrm{kPa}$, demonstrating that microscale forced convection could maintain sub-100 °C junctions even under extreme local power densities. This work established the microchannel and cold-plate paradigm that underpins contemporary LCPs, influencing decades of design evolution summarized in later reviews and experimental validations [247,248].

Governing Energy and Momentum Balances

For steady single-phase operation, the energy balance and inlet-referenced thermal resistance are

$$Q=\dot{m}{c}_p(T_{\mathrm{out}}-T_{\mathrm{in}}),R_{\mathrm{th},\mathrm{in}}={\displaystyle \frac{T_{j,max}-T_{\mathrm{in}}}{Q}}.$$

(20)

Local convection and pressure loss follow

$$h={\displaystyle \frac{Q}{A_s(T_s-T_f)}},\mathrm{Nu}={\displaystyle \frac{h{D}_h}{k}}=C{\mathrm{Re}}^m{\mathrm{Pr}}^n,\mathrm{\Delta }P=f{\displaystyle \frac{L}{D_h}}{\displaystyle \frac{\rho u^2}{2}},$$

(21)

and are embedded in reduced-order or block-element models for rapid co-optimization of layout and geometry [249].

Effectiveness–NTU Formulation and Consistent Resistance

Because LCPs purposefully operate with nontrivial coolant temperature rise, Equation (20) must be reconciled with heat-exchanger theory. Defining the cold-plate effectiveness and number of transfer units,

$$\epsilon ={\displaystyle \frac{Q}{\dot{m}{c}_p(T_{h,i}-T_{c,i})}},\mathrm{NTU}={\displaystyle \frac{UA}{\dot{m}{c}_p}},\epsilon =1-e^{-\mathrm{NTU}}(C_r\to 0),$$

(22)

Martínez et al. [248] demonstrated experimentally that the traditional $R_{\mathrm{th},\mathrm{in}}$ becomes inconsistent once $\epsilon \gtrsim 0.19$ (roughly $\mathrm{NTU}\gtrsim 0.21$). They derive and validate an LMTD-consistent correction to map the legacy resistance to a heat-exchanger-consistent quantity:

$$R_{\mathrm{LMTD}}=R_{\mathrm{th},\mathrm{in}}{\displaystyle \frac{-ln(1-\epsilon )}{\epsilon }}$$

(23)

Which collapses data across power, inlet temperature, flow rate, and internal flow configuration [248]. Designing cold plates at higher $\epsilon$ reduces required flow and improves heat-recovery potential [248].

Hydraulic–Thermal Co-Optimization

Reduced-order design optimizers model the plate as a coarse grid of elemental blocks (straight, elbow, tee) with friction-factor and heat-transfer correlations, enabling multi-objective searches (minimize $T_s$ and $\mathrm{\Delta }P$) under nonuniform heat maps. Experiments on an optimized aluminum water-cooled plate report $R_{\mathrm{th}}\approx 0.065\mathrm{K}{\mathrm{W}}^{-1}$ at practical velocities, with orders-of-magnitude lower design time than full topology optimization [249].

Materials and Coolant Selection

Copper and aluminum remain the primary cold-plate materials; silicon and LTCC variants are used when electrical isolation or co-fabrication dominate, at the expense of conductivity. Water’s high k and $c_p$ make it the most effective working fluid for LCPs, but corrosion and scaling must be mitigated (e.g., plating, inhibitors, cleanliness). Fluorinated liquids offer stability but with environmental/cost penalties; hydrocarbon refrigerants demand additional safety engineering. These trade-offs, and comparative property data, are synthesized in Wu et al. [247].

Advanced Packaging and Heterogeneous MCMs

MCM/HI packages present strongly nonuniform heat maps (chiplets up to ∼$140\mathrm{W}{\mathrm{cm}}^{-2}$ on emulators). Experiments with pin-fin cold plates on a four-heater (1.2 cm × 1.2 cm each) MCM emulator quantify the thermohydraulic response vs. flow rate and power distribution; validated 3D models match heater temperatures and $\mathrm{\Delta }P$, demonstrating the value of geometry/flow-field co-design to suppress $T_{j,max}$ under realistic nonuniform loading [250].

(i) Use Equation (23) (LMTD-consistent) for plate comparisons once coolant $\mathrm{\Delta }T$ is non-negligible; avoid legacy $R_{\mathrm{th},\mathrm{in}}$ beyond $\epsilon \approx 0.19$ [248]. (ii) Co-optimize layout and cross-section with reduced-order models, verifying finalists by CFD/experiment [249]. (iii) Select inlet/outlet topology to balance maldistribution and service constraints; diagonal/centered parallel arrangements are often advantageous [247]. (iv) Match material/coolant to facility water chemistry, fouling risk, and environmental targets [247]. (v) For MCMs, allocate flow nonuniformly (manifolds, zoning, pin-fin regions) toward hotspots and validate against spatial power maps [250].

A conceptual comparison between conventional liquid cold-plate cooling and embedded microchannel cooling, highlighting the elimination of an additional thermal interface (TIM2) and the resulting reduction in spreading and convective resistances, is illustrated in Figure 13.

2.3.4. Embedded Microchannel Liquid Cooling

Embedded Microchannel Liquid Cooling (EMLC) refers to the incorporation of micro-scale fluidic channels into the silicon substrate, interposer, or packaging of an electronic device, thereby facilitating coolant flow in proximity to active junctions. By integrating the cooling structure rather than affixing an external cold plate, EMLC reduces thermal interface resistance (e.g., TIM, IHS, solder) and significantly shortens the heat-conduction pathway between the device and the coolant.

EMLC is becoming a strong option for managing heat in new 2.5D and 3D chiplet systems, where power levels are often too high for standard air or cold-plate cooling. Tests show that embedded manifold microchannels, just 50 $\mathsf{\mu }$m wide, can handle heat fluxes up to 1200 W/cm² while maintaining steady surface temperatures [251]. Similarly, Fu et al. [252] fabricated near-junction microchannels integrated with micropillar arrays, achieving comparable heat-flux levels with minimal temperature gradients. Lian et al. [253] further demonstrated a 2.5D GaN/HEMT interposer architecture featuring 30 µm-pitch embedded microchannels that deliver direct device cooling through the substrate. These studies collectively confirm that embedded microchannel cooling operates effectively in the tens-of-micrometers hydraulic-diameter regime ($D_h\approx 30-150\mathsf{\mu }\mathrm{m}$), providing heat-transfer coefficients up to the ${10}^5-{10}^6\mathrm{W}{\mathrm{m}}^{-2}{\mathrm{K}}^{-1}$ range, substantially exceeding values typical of millimeter-scale cold-plate cooling, as documented in comparative analyses by van Erp et al. and Fathi et al. [53,254].

Such near-junction liquid cooling not only enhances thermal performance but also supports co-optimization among package design, power delivery, and thermal management, an essential direction for thermally feasible 3D chiplet integration.

Thermal–Fluid Fundamentals

The enhanced heat-transfer performance of microchannels arises from high surface-area density and boundary-layer compression. The local convective coefficient is defined as

$$h={\displaystyle \frac{Nuk}{D_h}},$$

(24)

where $Nu$ is the Nusselt number and k the thermal conductivity of the coolant. For fully developed laminar flow with constant wall heat flux, $Nu=4.36$ for circular and $Nu=7.54$ for rectangular ducts [255]. The hydraulic pressure drop is given by

$$\mathrm{\Delta }P=f{\displaystyle \frac{L}{D_h}}{\displaystyle \frac{\rho U^2}{2}},$$

(25)

where $f=64/\mathrm{Re}$ for laminar flow, $\mathrm{Re}=\rho U{D}_h/\mu$, and L is channel length. These relations capture the fundamental thermal–hydraulic trade-off inherent in microchannel design [256].

Manifold and Flow Distribution Design

When the flow is uneven in parallel channels, hot spots can form. Using optimized manifold shapes, such as double-H or tree-like branches, helps balance the flow and reduce pressure losses. Yang et al. showed that a compact double-H manifold design leads to more even temperature profiles across large chips. Both experiments and simulations have found that statistically optimized manifolds can lower peak temperatures by up to 15% compared to standard headers [57,254].

Packaging-Level Integration

Integrating microchannels into interposers or power-delivery substrates aligns naturally with 2.5D and 3D chiplet architectures. Tang et al. [257] implemented liquid cooling for 3D-stacked through-silicon via (TSV) modules, while van Erp et al. [53] co-fabricated microfluidic channels in silicon, achieving local heat fluxes exceeding $1000\mathrm{W}/{\mathrm{cm}}^2$. This co-design approach allows the architecture and cooling strategy to be developed concurrently, enabling effective flow zoning in high-power regions.

Reliability and Manufacturing Considerations

EMLC sets strict standards for component manufacturing accuracy, bonding quality, and sealing durability. To maintain structural stability, manufacturers need to use high-aspect-ratio etching on silicon or copper and ensure precise wafer-level bonding. Accelerated life testing, such as thermal cycling, vibration, and corrosion tests, is crucial because any coolant leaks inside the package can cause serious failures [256,258]. Fathi et al. [254] point out that controlling surface roughness and the shape of pore fins has a significant impact on both how fluid flows through the system and the reliability of the structure.

Performance Metrics

To benchmark cooling efficiency, a thermal–hydraulic figure of merit is often used:

$$\mathrm{\Pi }={\displaystyle \frac{h}{\mathrm{\Delta }P}},$$

(26)

or normalized form

$$\eta ={\displaystyle \frac{(h/h_0)}{{(\mathrm{\Delta }P/\mathrm{\Delta }{P}_0)}^{1/3}}},$$

(27)

where $h_0$ and $\mathrm{\Delta }{P}_0$ correspond to reference cold-plate values [256]. Experimental results indicate that microchannels with $50–100\mathsf{\mu }\mathrm{m}$ diameters achieve $200–300\%$ higher $\eta$ than traditional macro-channel cold plates [57,254].

With the rise of multi-kilowatt chiplet modules, EMLC provides a promising solution for managing thermal challenges. Current research explores two-phase microchannels, dielectric nanofluids, and scalable manifold networks that work with organic interposers [53,259]. Integrated electro-thermal and fluidic co-design methods will be key for future architecture and cooling systems.

Industrial Motivation: The MLCP Initiative

The growing thermal demands of generative AI have driven GPU-system power to unprecedented levels. For instance, NVIDIA’s NVL576 ‘Kyber’ rack, part of the ‘Rubin Ultra’ line, is expected to use up to about ~600 kW per rack [260,261]. At these power levels, air-cooling is no longer practical, and even standard cold plates struggle to evenly cool multi-kilowatt modules. To solve this, NVIDIA is said to be working on Microchannel Liquid Cold Plate (MLCP) technology. In this design, the cooling plate is closely integrated with the chip cover or packaging, and tiny flow channels are placed right above the compute die. This setup brings coolant closer to the heat source, reducing the number of thermal interfaces [262,263]. Although there is little publicly available data on performance, supplier reports indicate that MLCPs could cost three to five times as much as regular water-cooling plates [264]. These developments highlight the importance of embedded microchannel cooling for future high-density GPU systems.

2.3.5. Jet Impingement Cooling

Jet impingement cooling (JIC) is a convective heat transfer technique in which one or more high-velocity fluid jets are directed perpendicularly or obliquely onto a heated surface to disrupt the thermal and hydrodynamic boundary layers locally. This process produces very high local and area-averaged heat transfer coefficients, often exceeding ${10}^5\mathrm{W}{\mathrm{m}}^{-2}{\mathrm{K}}^{-1}$, making it highly suitable for high-power semiconductor packaging applications. JIC configurations are generally categorized as free, submerged, or confined jets, depending on the interaction of the impinging flow with the surrounding medium and the target surface.

The fundamental mechanisms governing jet impingement include stagnation-region convection, wall-jet radial flow, and secondary recirculation, each influenced by parameters such as Reynolds number, nozzle diameter, jet-to-target spacing ($H/d$), and flow confinement. Glynn et al. [265] conducted a detailed experimental study on submerged and confined air and water jets, employing nozzle diameters ranging from $0.5$ to $1.5\mathrm{mm}$, Reynolds numbers between $1\times {10}^3$ and $2\times {10}^4$, and jet-to-target spacing ratios of $H/d=1$ to 4. Their results showed that reducing both the nozzle diameter and the jet-to-surface distance leads to a marked increase in the stagnation point and overall heat-transfer coefficients. At smaller spacing ratios ($H/d\approx 1$–2), secondary peaks were observed in the local Nusselt-number distribution, which were attributed to the onset of turbulence and boundary-layer thinning within the wall-jet region.

Recent advancements in JIC have focused on improving spatial uniformity and adapting the technique for electronic and power device cooling. Plant et al. [266] reviewed the evolution of JIC configurations, including single, multiple, and synthetic jet systems, and highlighted the use of nanofluids and swirling jets to augment convective performance. Chaudhari et al. [267] compared synthetic and continuous jet cooling experimentally, reporting similar heat transfer performance while avoiding net mass injection. Klinkhamer et al. [268] achieved heat transfer coefficients approaching $100\mathrm{kW}{\mathrm{m}}^{-2}{\mathrm{K}}^{-1}$ in dielectric liquid jet systems and discussed associated thermal–hydraulic design trade-offs. Berg et al. [269] developed a 27-nozzle dielectric jet module for semiconductor power device cooling, achieving junction temperatures below $80°\mathrm{C}$ with strong agreement between computational and experimental results. Kim et al. [270] optimized a multi-jet configuration for electric vehicle inverter packages using ANN–NSGA-II, demonstrating improved temperature uniformity and reduced pumping losses through micropost-integrated jet surfaces.

Jet impingement cooling offers a high-performance, compact, and scalable solution for thermal management in advanced semiconductor packaging. This technique accommodates higher heat flux compared to traditional channel or cold-plate cooling methods.

2.3.6. Two-Phase Cooling

Two-phase cooling uses both liquid and vapor phases of a fluid to remove heat. When the liquid absorbs enough energy, it starts to boil and turns into vapor. This boiling process requires a large amount of energy, called the latent heat of vaporization. Because of this, two-phase systems can carry away much more heat without a significant rise in temperature. Since most of the heat is removed through boiling, the fluid does not need to move very fast, which means the pumping power can be lower. In systems like microchannel flow boiling and jet impingement, researchers have achieved heat fluxes close to $900\mathrm{W}/{\mathrm{cm}}^2$ and heat transfer coefficients greater than ${10}^5\mathrm{W}/{\mathrm{m}}^2\mathrm{K}$ [271]. This is several times better than what single-phase cooling can do. However, there is a limit to how much heat can be removed. When too much vapor forms and there is not enough liquid to keep the surface wet, the surface can dry out and overheat. This limit is called the critical heat flux (CHF). Zuber’s model gives an estimate for CHF:

$$q_{\mathrm{CHF}}^{″}=0.131h_{fg}{\rho }_v^{1/2}{\left[\sigma g({\rho }_l-{\rho }_v)\right]}^{1/4},$$

(28)

where $h_{fg}$ is the latent heat of vaporization, ${\rho }_v$ and ${\rho }_l$ are the vapor and liquid densities, $\sigma$ is the surface tension, and g is gravity. To prevent dryout and increase the CHF, engineers often use methods such as jet impingement, subcooled liquid injection, or specialized surface designs that bring fresh liquid to the hot areas [272].

System-level implementations demonstrate the feasibility of pumped two-phase cooling for high-power electronics.

Ohadi et al. [273] reported that microchannel evaporators achieved thermal resistance reductions of up to an order of magnitude with pumping power significantly below that of vapor-compression systems.

Marcinichen et al. [274] achieved over 60% energy savings in data-center applications using hybrid two-phase loops with dielectric refrigerants. Continued advances in channel topology, surface texturing, and flow stability control are essential for improving the reliability and scalability of two-phase cooling in next-generation electronic systems.

2.4. Reliability Considerations Under Thermo-Electro-Mechanical Coupling

Thermal fields induce many degradation mechanisms: electromigration (EM) in interconnects and micro-bumps, stress-induced delamination at interfaces, solder fatigue due to thermal cycling, and die/package warpage. Reliability modeling, therefore, integrates temperature, current density, and mechanical fields.

2.4.1. Thermoelasticity, Thermal Strain, and Warpage

In the context of linear thermoelasticity, the infinitesimal strain tensor can be expressed as follows [275,276,277]:

$$\epsilon ={\epsilon }_{\mathrm{el}}+{\epsilon }_{\mathrm{th}},{\epsilon }_{\mathrm{th}}=\alpha \mathrm{\Delta }TI.$$

(29)

In this case, $\alpha$ is the coefficient of thermal expansion (CTE), $\mathrm{\Delta }T=T-T_{\mathrm{ref}}$ is the difference in temperature from the stress-free reference state, and $\mathbf{I}$ is the second-order identity tensor.

The constitutive relation for an isotropic, linear thermoelastic material is expressed as follows [278,279]:

$$\sigma =C:\left(\epsilon -\alpha \mathrm{\Delta }TI\right),$$

(30)

where $\mathbf{C}$ is the fourth-order elasticity (stiffness) tensor that connects stress and elastic strain, this formulation is the basis for the thermoelastic stress analysis used to forecast warping and in multilayer packaging.

In multi-layered assemblies, such fan-out wafer-level or panel-level packages, a thermal mismatch between materials that are not the same (like die, redistribution layer, and epoxy molding compound) causes internal tensions and out-of-plane deformation, which is called warpage [280,281,282,283,284]. The curvature k measures this global deformation and is affected by the CTE mismatch, elastic moduli, and thickness ratio of the layers that make it up.

Stoney’s Thin-Film Approximation

Stoney’s classical formula provides an approximate relationship between the wafer curvature and the stress in the thin film (f) induced by a thermal excursion when a thin film (f) is placed on a much thicker substrate (s) [126,285]:

$$\kappa ={\displaystyle \frac{6(1-{\nu }_s)}{E_s{t}_s^2}}{\sigma }_f{t}_f,{\sigma }_f\approx {\displaystyle \frac{E_f}{1-{\nu }_f}}({\alpha }_f-{\alpha }_s)\mathrm{\Delta }T,$$

(31)

where $E_{(·)}$, ${\nu }_{(·)}$, and $t_{(·)}$ are the Young’s moduli, Poisson ratios, and thicknesses of the layers in question. This relationship represents the fundamental physics of curvature resulting from differential thermal expansion, applicable when $t_f\ll t_s$ and both layers exhibit elastic behavior.

Timoshenko’s Bilayer Model

Stoney’s limit is incorrect when the two layers are about the same thickness. The generalized Timoshenko bi-material curvature expression [126] enhances the analysis by integrating the mechanical and geometric mismatch parameters:

$$\kappa =\mathrm{\Delta }{\epsilon }_m{\displaystyle \frac{6}{t_s}}\mathrm{\Phi }(n,\rho ),n={\displaystyle \frac{{\overline{E}}_f}{{\overline{E}}_s}},\rho ={\displaystyle \frac{t_f}{t_s}},\overline{E}={\displaystyle \frac{E}{1-\nu }},$$

(32)

where $\mathrm{\Delta }{\epsilon }_m=({\alpha }_f-{\alpha }_s)\mathrm{\Delta }T$ is the mismatch strain, and $\mathrm{\Phi }(n,\rho )$ is a nondimensional curvature function approaching the Stoney limit for $\rho \ll 1$.

Implications for Fan-Out Packaging

During the mold curing, debonding, and reflow steps of fan-out wafer-level packaging (FOWLP) procedures, curvature changes dynamically [286,287,288,289]. To accurately forecast warpage, it is necessary to integrate thermoelasticity with viscoelastic relaxation and chemical shrinkage models of epoxy molding compounds [290,291,292]. Analytical solutions (e.g., Stoney or Timoshenko) are still important for design optimization and parametric sensitivity analysis. Finite-element models that include temperature- and cure-dependent moduli, on the other hand, give very accurate warpage simulations [283,284].

2.4.2. TSV-Induced Stress and Keep-Out Zones

Through-silicon vias (TSVs) are essential for creating vertical connections in three-dimensional (3D) integrated circuits. However, they can introduce significant thermal-mechanical stress because copper and silicon expand and contract at different rates. As the copper core cools after bonding or annealing, it contracts more than the surrounding silicon. This difference gives rise to what is known as an eigenstrain:

$${ϵ}^{*}=({\alpha }_{\mathrm{Cu}}-{\alpha }_{\mathrm{Si}})\mathrm{\Delta }T,$$

(33)

This process leads to axisymmetric radial and hoop stress components, ${\sigma }_{rr}\left(r\right)$ and ${\sigma }_{\theta \theta }\left(r\right)$, which decrease with distance from the via [293,294]. Finite-element analyses show that the maximum tensile stress, ${\sigma }_{\theta \theta }$, can reach several hundred megapascals within a few micrometers of the TSV wall, depending on the via radius, dielectric liner stiffness, and thermal load conditions [294,295].

Excessive tensile stress can slow carrier movement in nearby transistors, change device threshold voltages, and even cause microcracks in the silicon matrix [293]. To help prevent these issues, foundry guidelines usually call for a mechanical keep-out zone (KOZ) around each TSV, where active devices are not placed. The KOZ size is set based on results $max\left({\sigma }_{\theta \theta }\right)$ from thermal-mechanical simulations, which measure the maximum stress and link it to transistor degradation [294,296].

Recent research has expanded TSV stress modeling to include both heterogeneous and photonic interposers. Yang et al. showed that TSV-induced stress in silicon-on-insulator photonics interposers can shift the resonance wavelength of silicon ring resonators by about 0.1 nm when the TSV-to-waveguide spacing ratio $d/R\le 3$, supporting the idea of stress-limited KOZs for mixed electronic and photonic integration [296]. In addition, electrical design frameworks that focus on placement now use stress-aware layout optimization to determine optimal TSV positions and KOZ allocations, helping balance timing, performance, and area trade-offs in 2.5D and 3D chiplet systems [297].

2.4.3. Electromigration (EM) and the Blech Threshold in Thermally Constrained 2.5D/3D Stacks

Definition and Physical Origin

Electromigration (EM) happens when metal atoms move because electrons and the atomic lattice exchange momentum at high current density. The flow of electrons pushes atoms along the direction of current, creating a net force given by $F_{\mathrm{em}}=Z^{*}e\rho J$. This process leads to voids at the cathode and buildups at the anode. Over time, this movement can break interconnects or cause shorts between lines, making EM a key factor in the degradation of fine-pitch metallization.

Stress-induced backflow opposes the atomic motion driven by the electron wind in narrow interconnects. Atomic transport stops when the stress gradient is strong enough to balance the electromagnetic force. The Blech threshold [298], named after I. A. Blech, describes a condition where interconnects can avoid EM-induced failure if the product of current density and line length stays below a certain value. Today, reliability-focused design standards are based on this same idea [299].

In advanced 2.5D and 3D chiplet assemblies, current moves through fine-pitch redistribution layers, through-silicon vias, and micro-bumps. Here, Joule heating raises local temperatures. Combined with mechanical forces, this speeds up electromigration. These effects set strict limits on electromigration lifetime and ‘immortality’ thresholds. These thresholds, in turn, determine the limits for power delivery and I/O routing design.

The fundamental mechanism of electromigration-driven atomic transport and void formation in metal interconnects is schematically illustrated in Figure 14.

Arrhenius Lifetime Scaling (Black)

In a specific metallization system, the mean time to failure (MTTF) is determined by Black’s empirical law for a set failure criterion:

$$\mathrm{MTTF}=A{J}^{-n}exp\left({\displaystyle \frac{E_a}{k_{B}T}}\right),$$

(34)

where J is the current density, $n\in [1,2]$ (process- and path-dependent), $E_a$ the activation energy, and A a process-specific prefactor [301]. Equation (34) explicitly shows how thermal rise shortens lifetime exponentially, implying that thermal management is intrinsically an EM mitigation knob. For a target lifetime ${\tau }_{min}$, Equation (34) yields a temperature-dependent current-density ceiling:

$$J\le {\left({\displaystyle \frac{A}{{\tau }_{min}}}\right)}^{1/n}exp\left(-{\displaystyle \frac{E_a}{n{k}_{B}T}}\right),(\mathrm{lifetime}\mathrm{ceiling}).$$

(35)

Back-Stress Arrest and the Blech Product

In confined lines, the movement of atoms caused by electromigration is counteracted by a stress gradient that forms when boundaries block atomic flow. By integrating the one-dimensional force balance between the electron wind and the resulting stress, we arrive at the Blech criterion:

$$JL\le {\displaystyle \frac{{\sigma }_c\mathrm{\Omega }}{Z^{*}e\rho }},$$

(36)

where L is the segment length, ${\sigma }_c$ a critical (allowable) stress, $\mathrm{\Omega }$ the atomic volume, $Z^{*}e$ the effective charge, and $\rho$ the resistivity [298]. Segments satisfying Equation (36) are effectively immortal to EM drift. In 2.5D/3D PDNs, Equation (36) becomes a geometric co-design rule: for a given J and T (and thus $\rho \left(T\right)$), choose RDL run-lengths, via breaks, and $\mu$-bump pitch such that each high-current segment remains below its $JL$ threshold [299]. Because $\rho$ increases with temperature, thermal rise tightens the Blech bound, further coupling thermal design to EM robustness.

Coupled Electro–Thermo–Mechanical Evolution (Korhonen)

The Korhonen-type stress evolution equation provides a more thorough one-dimensional explanation of how back-stress forms in confined interconnects:

$${\displaystyle \frac{\partial \sigma }{\partial t}}={\displaystyle \frac{B\mathrm{\Omega }}{k_{B}T}}{\displaystyle \frac{\partial }{\partial x}}\left[D\left({\displaystyle \frac{\partial \sigma }{\partial x}}-{\displaystyle \frac{Z^{*}e\rho J}{\mathrm{\Omega }}}+{\displaystyle \frac{Q^{*}}{\mathrm{\Omega }}}{\displaystyle \frac{\partial T}{\partial x}}\right)\right],$$

(37)

with biaxial modulus B, diffusivity D, and heat of transport $Q^{*}$ [302]. The first term forms the back-stress response, the second the EM driving force, and the third captures thermomigration, showing that temperature gradients ${\partial }_{x}T$ bias mass transport even at fixed J. In vertical interconnect structures (TSVs and $\mu$-bumps) where current crowding and thermal bottlenecks coincide, EM and thermomigration act cooperatively; thermal management must therefore control both the absolute temperature T (for Equation (34)) and its gradient ${\partial }_{x}T$ (for Equation (37)).

Equations (34)–(37) define complementary design boundaries: (i) a lifetime ceiling on $J\left(T\right)$ from Equation (35); (ii) a geometric (immortality) bound on $JL$ from Equation (36); and (iii) a gradient-aware stability condition from Equation (37). For 2.5D/3D chiplet PDNs, these collectively define thermal–electrical feasibility maps over the architectural floorplan and cooling stack, ensuring that current densities, segment geometries, and temperature fields jointly satisfy EM reliability requirements [299].

2.4.4. Solder/$\mu$-Bump Thermal Cycling Fatigue

In 2.5D and 3D integrated systems, solder and micro-bump ($\mu$-bump) interconnects are exposed to repeated temperature changes because the chip, interposer, and package substrate expand at different rates. Over time, these differences cause plastic shear strain to build up, which can eventually lead to cracks forming and growing in the solder joints [303,304]. The Coffin–Manson ratio is a common method for estimating how long a material will last under these temperature cycles:

$${\displaystyle \frac{\mathrm{\Delta }{\epsilon }_p}{2}}={\epsilon }_f^{\prime }{\left(2N_f\right)}^c,c<0,$$

(38)

where ${\epsilon }_f^{\prime }$ is the fatigue ductility coefficient and $N_f$ is the number of cycles to crack initiation [305,306]. The inelastic strain amplitude $\mathrm{\Delta }{\epsilon }_p$ can be obtained from finite element (FE) simulations or approximated as $\mathrm{\Delta }{\epsilon }_{\mathrm{th}}\sim \mathrm{\Delta }\alpha \mathrm{\Delta }TH/h_{\mathrm{neutral}}$, where $\mathrm{\Delta }\alpha$ is the CTE mismatch, $\mathrm{\Delta }T$ is the temperature swing, and $h_{\mathrm{neutral}}$ is the distance from the neutral point in a warping package.

Fatigue Crack Propagation Models

After crack initiation, fatigue crack growth can be modeled as a function of the inelastic strain energy density $\mathrm{\Delta }{W}_d$ using the Darveaux relation [307]:

$${\displaystyle \frac{da}{dN}}=C{\left(\mathrm{\Delta }{W}_d\right)}^m,N_0=K{\left(\mathrm{\Delta }{W}_d\right)}^{-m^{\prime }},$$

(39)

where C, m, K, and $m^{\prime }$ are empirical constants, and $N_0$ represents the number of cycles to crack initiation. These models have been widely used for JEDEC temperature-cycling qualification and provide a physics-based link between package geometry, materials, and thermomechanical reliability.

Typical crack initiation sites and propagation paths observed in solder and micro-bump interconnects under thermomechanical cycling are illustrated in Figure 15.

Table 17. It compiles major reliability risks in semiconductor packaging, detailing the underlying damage mechanisms, applicable qualification stress tests, and authoritative studies documenting these failure modes.

Failure Mechanisms	Description	Accelerated Stress Tests	Ref.
Interface delamination and induced micro-cracks	Delamination and cracking inside the die or at various package interfaces.	Temperature cycling, thermal shock, HAST, temperature–humidity testing, pressure cooker test (PCT), mechanical bending (CSP structures).	[308,309,310,311,312]
Solder joint fatigue/cracking; BGA and PoP ball failure	Cracking of solder joints and associated creep fatigue damage.	Temperature cycling, power cycling, vibration fatigue testing.	[313,314,315,316]
Corrosion	Moisture- and contaminant-induced degradation; PCB residue- driven corrosion.	Humidity testing, pressure cooker test, HAST, PCT.	[317,318,319,320]
Electromigration (EM)	Current-density-driven degradation at interconnects or solder bumps; metallization mass transport.	High current density, elevated temperature, and directional electromigration stressing.	[321,322,323,324]

compiles major reliability risks in semiconductor packaging, detailing the underlying damage mechanisms, applicable qualification stress tests, and authoritative studies documenting these failure modes.

Experimental and Modeling Advances

Recent studies have improved our understanding of how solder fatigue develops when both thermal and mechanical factors are present. In 2024, Li et al. [304] provided a thorough review of the main thermal fatigue mechanisms in micro-solder joints, focusing on intermetallic compound (IMC) growth, cyclic recrystallization, and void coalescence. They found that fatigue cracks usually start at the IMC/coarsened-Sn interface and move along both intergranular and transgranular paths. Lu et al. [325] showed that void formation reduces thermal conduction, which speeds up thermomechanical damage in flip-chip solder bumps. Suppiah et al. (2017) [326] looked at how reflow profile factors such as peak temperature, time above the liquidus, soak time, cooling rate, and flux application affect the microstructure and durability of solder joints in flip-chip assemblies. They reported that these thermal factors strongly influence IMC formation, while warpage is mainly due to differences in thermal expansion and stresses during reflow.

Abtew and Selvaduray [303] reviewed the transition from leaded to lead-free solder systems and identified SnAgCu (SAC) alloys as the most robust replacement for 60Sn–40Pb based on improved creep resistance. Basaran et al. [327] developed a continuum damage mechanics framework to capture nonlinear viscoplasticity in solder joints subjected to cyclic thermomechanical loading. Kang et al. [328] and Lee et al. [329] found that lead-free solders demonstrate delayed crack initiation but accelerated crack propagation following intermetallic compound (IMC) thickening, highlighting the significance of interfacial stability.

In advanced 2.5D and 3D chiplet systems, fatigue reliability is further constrained by vertical thermal gradients and nonuniform warpage across stacked dies. High local temperature excursions increase $\mathrm{\Delta }{W}_d$, accelerating crack propagation and compromising long-term reliability. Recent advances in data-driven modeling have enhanced finite element-based life prediction frameworks: Jong et al. [330] proposed a physics-informed long short-term memory (PI-LSTM) approach that integrates finite element outputs with experimental data to predict solder joint fatigue life more accurately, while Akhtar et al. [331] developed an AI-driven 3D point cloud framework using finite element analysis (FEA) data to forecast joint lifetimes in complex chiplet architectures. These methods enable rapid reliability screening and parametric sensitivity evaluation early in the design phase. Design measures such as compliant underfills, thinner and higher-conductivity lids, and reduced $\mathrm{\Delta }T$ operation remain effective in lowering $\mathrm{\Delta }{W}_d$ and extending solder joint life. Integrating such predictive models with thermal feasibility maps supports architecture cooling co-design strategies that maintain both mechanical and thermal integrity in future heterogeneous chiplet packages.

Taken together, the sections on heat-transfer mechanisms, thermal resistance networks, interface materials, interposers, and reliability show that thermal feasibility in 2.5D and 3D chiplet systems is set by coupled parameters rather than any single material or cooler. Building on these quantified ranges for resistances, conductivities, and reliability limits, the next section introduces Thermal Feasibility Maps (TFMs) as a framework to organize this parameter space and delineate operating envelopes for heterogeneous chiplet architectures.

3. Toward Thermal Feasibility Maps (TFMs)

3.1. Concept and Definition

Thermal Feasibility Maps (TFMs) are introduced as a general framework to unify heterogeneous thermal reports into a predictive, reusable design methodology. Unlike single-point demonstrations that specify the maximum power for a given stack, TFMs explicitly parameterize the feasibility as a function of three orthogonal axes: interface scale ($t_{\mathrm{TIM}}$, bond line quality), mesoscale spreading ($k_{\mathrm{int}}$, interposer conductivity and power distribution), and cooling class (h, convective ceiling). The output is a feasible power envelope, $P_{\mathrm{feas}}$, bounded by both thermal physics and reliability limits. At the core of this formulation lies the thermal headroom metric,

$$H={\displaystyle \frac{T_{max}-T_{\infty }}{R_{\theta }}},$$

(40)

where $T_{max}$ is the maximum allowable junction temperature, $T_{\infty }$ is the coolant inlet temperature, and $R_{\theta }$ is the effective junction-to-ambient thermal resistance. While this form is classical, TFMs extend it into a multidimensional construct, in which $R_{\theta }$ is decomposed into pathways across interfaces, spreading domains, and convective boundaries.

The novelty of TFMs lies in their ability to normalize diverse literature data onto a common design space: architecture × cooling regime × material stack—allowing power feasibility to be visualized as a continuous surface rather than isolated benchmarks. This enables a unified language for packaging architects: identifying not only where the frontier of cooling performance resides, but also which axis, interface, spreading, or convection most constrains further scaling.

Industry Power Scaling Motivation for TFMs

The thermal design power (TDP) trajectory of modern AI accelerators provides a quantitative imperative for TFMs. Over the past five years, package power has increased nearly an order of magnitude from ∼400 W in NVIDIA’s A100 (2020) to 1000–1400 W in AMD’s MI350X (2025), and projections exceed 2500 W for NVIDIA’s “Rubin” R300 (2028) [332,333,334]. Such growth, driven by dense chiplet integration, HBM3E memory stacks, and ultra-wide interconnect fabrics, has already surpassed the limits of air and single-phase liquid cooling. As summarized in

Table 18. Evolution of AI accelerator power envelopes (2020–2035) illustrating the steep rise in thermal design power (TDP) across major vendors. These data motivate the need for Thermal Feasibility Maps (TFMs) to correlate power scaling with cooling technology boundaries.

Processor/Accelerator	Power (W)	Year	Architecture	Power Class	Notes/Sources
Future HBM8 HPC Modules	>15,000	2035 (proj.)	Multi-die GPU/CPU stack	Extreme	Academic projection for 3D HBM8 modules; two-phase immersion required
NVIDIA R300 (Rubin)	2500–3000	2028 (proj.)	Next-gen GPU	Extreme	Multi-die GPU with HBM3E; immersion-cooled [334].
Positron Atlas	∼2000	2025	Proprietary AI ASIC	Ultra High	Claimed 2× H200 performance at 2000 W [335].
AMD MI450	∼1600	2026 (proj.)	CDNA 4/AI Accelerator	Ultra High	Expected successor to MI350X; 1600 W TDP class [334].
NVIDIA R200	∼1200	2026 (proj.)	Next-gen AI GPU	Ultra High	Intermediate generation between Blackwell and Rubin; projected 1200 W [334].
NVIDIA B200 (Blackwell)	∼1000	2025	Blackwell GPU + HBM3E	Ultra High	Liquid-cooled multi-die package; full-spec TDP near 1.0–1.2 kW [333].
AMD MI350X/MI355X	1000–1400	2025	CDNA 4	Ultra High	Projected HPC-class AI GPUs; TDP ≈ 1.2 kW [21].
AMD MI300X	∼750	2023	CDNA 3	Very High	8× HBM3 integration; ∼700–750 W TDP [18].
NVIDIA H100	∼700	2023	Hopper (SXM5)	Very High	Widely deployed AI training GPU; liquid-cooled variant dominant [17].
AWS Trainium 2	∼500	2024	Custom AI ASIC	High	Used in Amazon EC2 Trn2 clusters [336].
Tesla D1 (Dojo)	400–600	2022	Dojo Node Chip	High	Part of Dojo training tile; air-cooled [23].
NVIDIA A100	∼400	2020	Ampere (SXM4)	High	HPC/AI baseline GPU; liquid/hybrid cooled [332].
Alibaba Hanguang 800	∼300	2021	AI Inference ASIC	Medium	First Chinese AI accelerator; ∼300 W TDP [337].
Meta MTIA v2	90–160	2023	Custom ASIC	Medium	Optimized for recommender workloads; air-cooled [338].
Qualcomm Cloud AI 100	75	2020	Inference ASIC	Low	Datacenter inference chip; fanless operation [339].

, effective heat fluxes now exceed 400 W·cm⁻², rendering conventional methods infeasible and motivating embedded or two-phase cooling strategies. TFMs thus emerge as the necessary co-design instrument for linking power-scaling trends with multi-scale thermal physics.

Table 18 summarizes the evolution of thermal design power across major AI accelerators from 2020 to projected 2035, highlighting the rapid escalation from sub-500 W devices to multi-kilowatt class packages that necessitate advanced cooling strategies and motivate the development of Thermal Feasibility Maps.

3.2. Mathematical Formulation

We formalize the TFM framework through a normalized thermal headroom metric:

$$H={\displaystyle \frac{T_{max}-T_{\infty }}{R_{\theta }(t_{\mathrm{TIM}},k_{\mathrm{int}},h,{\mathrm{\Phi }}_P)}},$$

(41)

where $R_{\theta }$ decomposes as follows:

$$R_{\theta }=R_{\mathrm{TIM}}(t_{\mathrm{TIM}},k_{\mathrm{TIM}})+R_{\mathrm{spread}}(k_{\mathrm{int}},{\mathrm{\Phi }}_P)+R_{\mathrm{conv}}(h,A),$$

(42)

with

• $R_{\mathrm{TIM}}=t_{\mathrm{TIM}}/\left(k_{\mathrm{TIM}}A\right)$, representing the interface conduction term;
• $R_{\mathrm{spread}}$ determined by lateral anisotropy and chip-to-interposer geometry;
• $R_{\mathrm{conv}}\approx 1/\left(hA\right)$, representing convective resistance at the cooler boundary.

Dimensionless normalization through the Biot number,

$$Bi={\displaystyle \frac{hL}{k}},$$

(43)

offers physical interpretability: $Bi\ll 1$ identifies interface-limited designs, whereas $Bi\gg 1$ denotes cooling-limited architectures. Empirically, most current 2.5D/3D packages occupy $Bi\sim 0.1$–1, reflecting co-limitation by both interfaces and convection.

Reducing $t_{\mathrm{TIM}}$ from 20 µm to 2 µm at $k_{\mathrm{TIM}}=5$ W·m⁻¹K⁻¹ lowers $R_{\mathrm{TIM}}$ by a factor of ten, adding ∼200 W headroom for a 400 mm² die. Likewise, upgrading an organic interposer ($k=2$ W·m⁻¹K⁻¹) to silicon ($k=150$ W·m⁻¹K⁻¹) can suppress local hotspots by 15–20 °C under 500 W loads.

The global scale and geographic concentration of data-center infrastructure that underpins high-power AI computing are illustrated in Figure 16, underscoring the system-level importance of thermally efficient and scalable cooling solutions.

3.3. Reliability Guard Bands and Interpretation

The feasible power envelope follows:

$$P_{\mathrm{feas}}\le H={\displaystyle \frac{T_{max}-T_{\infty }}{R_{\theta }(t_{\mathrm{TIM}},k_{\mathrm{int}},h,{\mathrm{\Phi }}_P)}},$$

(44)

and reliability guard bands impose additional constraints by tightening design limits (e.g., maximum warpage, interfacial toughness, fatigue life). In TFMs, these appear as shaded infeasible regions that bound the thermally feasible domain.

TFMs thus translate multi-scale physics and reliability metrics into a unified coordinate system. By projecting interface, spreading, and cooling parameters onto a single axis, TFMs provide not only a design diagnostic but also a prescriptive co-design framework that links power, material, and reliability domains into a single manufacturability envelope.

3.4. Practical Use Cases of Thermal Feasibility Maps (TFMs)

Although TFMs were introduced as a generalized framework for unifying thermal data into a parametric design space, their value is best demonstrated through concrete design decisions that arise in modern heterogeneous integration. Here, we present three representative use cases that map directly onto the three axes of the TFM formulation developed in this work: interface scale, mesoscale spreading, and cooling class. These examples are drawn from operational regimes already discussed above, including chiplet-level heat fluxes approaching 1 kW·cm⁻², low-k organic substrates, and the escalating TDPs of state-of-the-art accelerators (A100→H100→MI350X→R300).

3.4.1. Interface-Scale Decisions (TIM and Bond-Line Optimization)

TFMs can quantify how bond-line thickness and thermal interface conductivity shape the allowable power envelope. As discussed earlier above, bond-line variations in the 1–20 µm range can change the effective thermal resistance by factors of 5–10, rapidly consuming thermal headroom, even with liquid cooling. A TFM slice at fixed $(k_{\mathrm{int}},h)$ shows how reducing $t_{\mathrm{TIM}}$ shifts the operating point along the interface axis and increases $P_{\mathrm{feas}}$, until spreading or convection becomes the dominant limiter. This enables early screening of interface technologies: greases, solders, sintered metals, or advanced composite TIMs within a unified feasibility space rather than through isolated demonstrations.

3.4.2. Interposer and Spreading Choices Under Non-Uniform Power

High-density chiplet systems (e.g., CoWoS, EMIB, MI300, H100) exhibit strongly uneven power maps with local fluxes that exceed several hundred W·cm⁻². The lateral thermal conductivity of the interposer—ranging from low-k epoxy-glass (0.3–0.6 W·m⁻¹K⁻¹) to high-k silicon (150 W·m⁻¹K⁻¹) strongly modifies $R_{\mathrm{spread}}$. TFMs allow designers to sweep $k_{\mathrm{int}}$ and visualize how different interposers shift the operating point from a spreading-limited regime toward a convection-limited one. For example, transitioning from an organic core to a silicon interposer reduces the temperature rise by 10–20 °C under multi-hundred-watt loads, consistent with earlier analyses of chiplet-level heat spreading included in this review. TFMs can make this comparison systematic and predictive, identifying when further material upgrades yield diminishing returns because convection becomes the dominant axis.

3.4.3. Cooling-Class Transitions for Multi-Kilowatt AI Accelerators

Industry TDPs have increased nearly an order of magnitude over five years, from ∼400 W (A100) to 1000–1400 W (MI350X) and projected 2500+ W for future “Rubin” platforms. As described in Section Industry Power Scaling Motivation for TFMs, these power levels exceed the practical limits of air cooling and strain even single-phase cold plates. TFMs can formalize these transitions by treating h as an orthogonal axis: air coolers occupy $h\sim 10$–100 W·m⁻²K⁻¹, single-phase cold plates achieve $h\sim {10}^3$–${10}^4$ W·m⁻²K⁻¹, and embedded/two-phase technologies can exceed ${10}^5$ W·m⁻²K⁻¹, consistent with the performance ranges. Mapping these regimes onto the TFM surface can makes clear where a given stack becomes cooling-limited and provides a quantitative rationale for when migration to two-phase or microfluidic cooling is necessary for thermal reliability.

It demonstrates how TFMs translate the multi-scale physics already reviewed in Section 2 into a predictive and visual design tool. They expose whether interfaces, spreading, or convection dominate a given architecture, quantify feasible power envelopes, and provide a common decision framework that complements the analytical, finite-element, and experimental data surveyed. As power densities continue to climb in heterogeneous integration, TFMs enable early stage, cross-disciplinary co-design that directly supports the requirements of next-generation HI systems.

4. Future Research Directions

4.1. Integration of Electro-Thermo-Mechanical (ETM) Co-Design in Thermal Management of Advanced Semiconductor Packaging

As semiconductor packaging evolves, managing higher power densities and mechanical stresses in complex 2.5D and 3D systems will require integrated electro-thermo-mechanical (ETM) co-design methods. By 2035, advanced 3D chiplet and HBM-stacked designs are expected to reach localized power densities of 300–$600\mathrm{W}/{\mathrm{cm}}^2$ in hotspot areas, with total package power surpassing 10 to 15 kW in high-performance computing modules. At these levels, optimizing only thermal or electrical aspects will not be enough, so a fully integrated ETM co-design approach will be essential [341,342,343].

The first challenge is the lack of standardized multiphysics model representations. Creating unified chiplet and package models that include temperature-dependent electrical properties, heat transfer rates, and stress-strain measurements will support consistent ETM analysis across EDA, foundry, and assembly environments [297,344].

Secondly, another important area is the development of AI-based co-optimization frameworks that simultaneously improve electrical power delivery, thermal management, and mechanical design. These data-driven methods will use reinforcement learning to predict how different domains interact, allowing for earlier multiphysics analysis in the design process [341].

Third, new embedded cooling methods, such as microfluidic and two-phase systems, need to work closely with ETM design. This ensures both electrical and mechanical compatibility and helps achieve thermal resistance below $0.05°\mathrm{C}·{\mathrm{cm}}^2/\mathrm{W}$ [52].

Fourth, as co-packaged optics (CPO) become more common, it is important to optimize optical, thermal, and mechanical factors together. This approach keeps optical alignment stable, reduces wavelength drift caused by temperature changes, and helps maintain a steady bit-error rate even as conditions change [345,346].

Recent advances in research extend electro-thermal management (ETM) co-design toward adaptive and sustainable paradigms. The integration of morphable or tunable packaging materials with temperature-dependent coefficients of thermal expansion (CTE) enables active stress compensation. Furthermore, carbon- and energy-aware ETM optimization quantifies trade-offs among cooling efficiency, embodied carbon, and lifetime reliability. The use of quantum and neuromorphic solvers for coupled ETM simulations is projected to accelerate convergence times by several orders of magnitude relative to traditional finite-element methods.

Ten-Year Roadmap: In the near term, from 2025 to 2027, the main goals are to define ETM data-exchange schemas, develop compact reduced-order models, and match simulation results with silicon test vehicles [342,343]. Between 2028 and 2030, the focus will shift to standardizing ETM model formats and integrating runtime telemetry. This will involve embedding temperature, strain, and voltage sensors within die-to-die fabrics like UCIe and BoW, which will support closed-loop thermal control and in situ model calibration [347]. Starting in 2031, ETM co-design is expected to become self-adaptive, using digital twin ecosystems that update multiphysics models with field telemetry and AI-based learning. Cooling structures will be designed as reusable IP modules, optimized alongside PDN and interconnect architectures, to handle localized heat flux densities above $600\mathrm{W}/{\mathrm{cm}}^2$. ETM optimization frameworks will also include sustainability metrics, helping teams make co-design choices that balance electrical performance, thermal efficiency, mechanical reliability, and environmental impact.

4.2. Emerging Materials and Structures for Interface and Cooling

As 2.5D, 3D, and chiplet-based packaging become more common, new materials are needed for thermal interfaces and cooling to handle higher heat and more complex interconnects.

Thermal Interface Materials:

Polymer–ceramic TIMs are commonly used because they are easy to apply, but their thermal conductivity is limited. To address this, high-k fillers like AlN and h-BN are added [342]. Researchers are also developing two-dimensional materials such as graphene and hexagonal boron nitride to improve in-plane conductivity. Current work focuses on better alignment, improved filler-matrix interface, and reduced interfacial thermal resistance [348]. Liquid metal TIMs made from Ga-In alloys are gaining interest again for their flexibility and high thermal conductance (over 30 to 40 W/m·K), especially when combined with soft polymer matrices to help prevent corrosion and migration [349].

Die-Attach Materials:

Sintered silver is a proven choice for high-power logic and GaN/SiC dies because of its high thermal conductivity and stability during thermal cycling. Researchers have shown that Ag nanopastes can form dense joints at temperatures (below 200 °C). Transient liquid-phase (TLP) bonding systems, including Cu-Sn or Ag-In alloys, are also becoming reliable reflow-free solid-metal options with high remelt thresholds [350].

Heat spreaders and interposers are seeing new materials, such as chemical-vapor-deposited diamond and boron arsenide (BAs), gain attention for their high thermal conductivity. BAs, which have a bulk thermal conductivity exceeding 1000 W/m·K, also show lower thermal boundary resistance than diamond when bonded to GaN. These materials may soon replace traditional options like AlN, copper, and pyrolytic graphite sheets in applications with very high power density, such as HBM and chiplet die tops.

Cooling Fluids and Two-Phase Systems:

As PFAS-based dielectric fluids are being phased out, there is growing interest in PFAS-free options for immersion and two-phase cooling. Researchers are working to improve hydrocarbon-based and biocompatible dielectrics by focusing on their boiling points, latent heat, and compatibility with various materials. Pumped two-phase cold plate systems that use non-fluorinated refrigerants like R-1233zd(E) are showing good results, with the potential to remove more than 500 W/cm² at the chip level.

Embedded Cooling Structures:

Microchannel, pin-fin, and jet-impingement designs are now being tested inside silicon interposers or advanced substrates to address localized hotspots. Thanks to silicon micromachining and wafer-level bonding, these methods bring coolant within 100–200 $\mathsf{\mu }$m of heat sources, which helps remove thermal bottlenecks. Still, ensuring reliability during pressure changes and maintaining electrochemical stability are ongoing challenges.

Together, these material innovations are likely to be used with co-design methods that model electrical, thermal, and mechanical behaviors in advanced packaging. Material property databases that include temperature-dependent k, CTE, modulus, and interface resistance will be essential for accurate multiphysics simulation and ETM signoff.

4.3. Future Research Directions in Digital Twins for Thermal Management

In the future, digital twins for advanced semiconductor packaging will likely become multiscale, multiphysics, and data-calibrated systems. They will bring together chip power, interposer conduction, microfluidic cooling, and thermo-mechanical warpage. These digital twins will be checked regularly using embedded sensors and production data, creating a strong digital link from design to deployment [343,351].

One important area is creating AI-powered thermal models that remain stable over long periods and accelerate decision-making in chiplet layout and thermal planning. Recent approaches, such as physics-informed neural networks and neural operators, have demonstrated high accuracy and scale well [352,353,354].

Machine-learning models that connect bill-of-materials and process parameters to both overall and junction-level thermal resistance can help speed up reliability and qualification cycles. Future studies should focus on measuring uncertainty and adapting these models to different package types

As power densities continue to rise in 3D-stacked and heterogeneous systems, digital twins need to be developed alongside advanced cooling technologies and should track how interfaces degrade over time. Collaborative efforts like the SRC and NIST ‘Smart Twins’ program are working to create common data formats and validation methods, helping the field make steady and reliable progress [355].

5. Conclusions

Thermal management is the main challenge in scaling heterogeneous 2.5D and 3D chiplet packages to meet the high power densities required by modern high-performance computing and AI accelerators. Previous research has improved individual aspects such as thermal interfaces, interposer materials, and cooling solutions, but these advances often overlook how these elements interact across different scales. This review explores Thermal Feasibility Maps (TFMs) as a means of integrating these factors. TFMs connect sensitivities across scales to practical cooling methods and help define a clear design space for early thermal evaluation.

There are three main factors that consistently stand out. At the interface scale, bond-line thickness in the 1–20 µm range can change effective thermal resistance by factors of 5–10, quickly depleting the available thermal margin, even with liquid cooling. At the mesoscale, interposer conductivity varies from 1–3 W·m⁻¹K⁻¹ for organic substrates to 150–200 W·m⁻¹K⁻¹ for silicon or diamond-based materials. This directly affects how heat spreads and how evenly temperatures are distributed. At the macroscale, reported cooling approaches range from air-cooled heat sinks to single-phase and embedded two-phase systems, with convective coefficients h spanning from 10² to above 10⁴ W·m⁻²K⁻¹.

Reliability introduces additional design challenges, such as package warping, interface failures, and restrictions on two-phase stability. To ensure thermal feasibility, it is important to optimize materials, package shape, and cooling methods together rather than relying on a single performance measure. TFMs are most useful because they turn single-value metrics into detailed maps that show the trade-offs between TIM properties, interposer choices, cooling types, and reliability limits.

Future research should include TFMs in multiphysics digital twins and surrogate modeling environments to allow predictive, real-time thermal evaluation for 2.5D and 3D architectures. This approach will help combine architecture and cooling design, supporting reliable kilowatt-class chiplet systems.