Search Results (101)

This study presents a comprehensive investigation of the micro-wetting behavior of SAC305 and SnBi58 solders on chip components. Micro-wetting balance tests, which employ small solder globules, enable direct evaluation of solder wettability on miniature electronic components such as 1206 chip resistors and 1206 and 0603 chip capacitors. Unlike conventional wetting tests that use large solder baths, the micro-wetting method suppresses excessive solder rise, making it suitable for testing small-scale components. The results demonstrate that micro-wetting testing is a reliable method for evaluating solder wettability on chip components when appropriate globule size, test temperature, and experimental parameters such as immersion depth and speed are carefully controlled. Among the tested conditions, 2 mm diameter solder globules are identified as the optimal choice because they offer improved thermal management and reduced surface oxidation. The wetting times measured for SnBi58 are comparable to those obtained for conventional SAC305 solder, whereas the maximum wetting forces are generally lower. However, micro-wetting curves exhibit noticeable fluctuations, which complicate the analysis of additional parameters, such as maximum wetting force and wetting rate, and limit direct comparison with standard reference values. Full article

Transistor-level Integrated Circuit (IC) design is fundamental to modern electronics, yet it remains one of the most expertise-intensive and time-consuming stages of chip development. As circuit complexity continues to rise, the need to automate this low-level design process has become critical to sustaining innovation and productivity across the semiconductor industry. This study presents a fully automated methodology for transistor-level IC design using a novel framework that integrates Grammatical Evolution (GE) with Cadence SKILL code. Beyond automation, the framework explicitly examines how symmetry and asymmetry shape the evolutionary search space and resulting circuit structures. To address the time-consuming and expertise-intensive nature of conventional integrated circuit design, the framework automates the synthesis of both digital and analogue circuits without requiring prior domain knowledge. A specialised attribute grammar (AG) evolves circuit topology and sizing, with performance assessed by a multi-objective fitness function. Symmetry is analysed at three levels: (i) domain-level structural dualities (e.g., NAND/NOR mirror topologies and PMOS/NMOS exchanges), (ii) objective-level symmetries created by logic threshold settings, and (iii) representational symmetries managed through grammatical constraints that preserve valid connectivity while avoiding redundant isomorphs. Validation was carried out on universal logic gates (NAND and NOR) at multiple logic thresholds, as well as on a temperature sensor. Under stricter thresholds, the evolved logic gates display emergent duality, converging to mirror-image transistor configurations; relaxed thresholds increase symmetric plateaus and slow convergence. The evolved logic gates achieve superior performance over conventional Complementary Metal–Oxide–Semiconductor (CMOS), Transmission Gate Logic (TGL), and Gate Diffusion Input (GDI) implementations, demonstrating lower power consumption, a reduced Power–Delay Product (PDP), and fewer transistors. Similarly, the evolved temperature sensor exhibits improved sensitivity, reduced power, and Integral Nonlinearity (INL), and a smaller area compared to the conventional Proportional to Absolute Temperature (PTAT) or “gold” circuit, without requiring resistors. The analogue design further demonstrates beneficial asymmetry in device roles, breaking canonical structures to achieve higher performance. Across all case studies, the evolved designs matched or outperformed their manually designed counterparts, demonstrating that this GE-based approach provides a scalable and effective path toward fully automated, symmetry-aware integrated circuit synthesis. Full article

In this study, we present the design and analysis of a stacked inverter-based millimeter-wave (mmWave) power amplifier (PA) in 90 nm CMOS-targeting wideband Q-band operation. The PA employs two PMOS and two NMOS devices in a fully stacked inverter topology to distribute device stress, remove the need for an RF choke, and increase effective transconductance while preserving compact layout. A resistor ladder biases the stack near $V_{\mathrm{DD}}/4$ per device, and capacitive division steers intermediate-node swings to enable class-E-like voltage shaping at the output. Closed-form models are developed for gain, output power, drain efficiency/PAE, and linearity, alongside a small-signal stacked-ladder formulation that quantifies stress sharing and the impedance presented to the matching networks; L/T network synthesis relations are provided to co-optimize bandwidth and insertion loss. Post-layout simulation in 90 nm CMOS shows $|S_{21}|$ = 10 dB at 39.84 GHz with 3 dB bandwidth from 36.8 to 42.4 GHz, peak PAE of 18.38% near 41 GHz, and saturated output power $P_{\mathrm{sat}}=8.67$ dBm at $V_{\mathrm{DD}}=4$ V, with $S_{11}<-15$ dB and reverse isolation $\approx -16$ dB. The layout occupies $1.6\times 1.6$ mm² and draws 31.08 mW. Robustness is validated via a 200-run Monte Carlo showing tight clustering of $P_{\mathrm{sat}}$ and PAE, sensitivity sweeps identifying sizing/tolerance trade-offs ($\pm 10\%$ devices/passives), and EM co-simulation of on-chip passives indicating only minor loss/shift relative to schematic while preserving the target bandwidth and efficiency. The results demonstrate a balanced gain–efficiency–power trade-off with layout-aware resilience, positioning stacked-inverter CMOS PAs as a power- and area-efficient solution for mmWave front-ends. Full article

This paper presents a W-band high-efficiency and high-output-power power amplifier (PA) based on a 130 nm AlGaN/GaN-on-SiC HEMT process. The PA is designed to deliver optimal output power and gain performance across the entire W-band. A balanced architecture is adopted, combining two amplifier units through Lange couplers. High- and low-impedance microstrip lines are employed for input, output, and inter-stage matching. Each amplifier core adopts a three-stage configuration with gate width ratios of 1:2:4 to enhance gain. The bias network incorporates MIM capacitors and thin-film resistors to improve stability. Measured results indicate a small signal gain exceeding 17 dB under a gate voltage of −2.2 V and a drain voltage of +20 V. Within the 80–86 GHz frequency range, the PA achieves an output power above 34 dBm with a 22 dBm input power, corresponding to a power gain above 12 dB and a power-added efficiency (PAE) greater than 20%. The chip occupies a compact area of 2.65 mm × 3.75 mm. Compared with previously reported works, the proposed PA demonstrates the highest PAE within the 80–86 GHz band. Full article

This paper presents the design and implementation of an ultra-wideband (UWB) and flat gain low noise amplifier (LNA) using 0.15 µm GaAs pHEMT technology, specifically tailored for applications that benefit from multi-band capability, such as satellite communication. The designed LNA consists of three stages: Two stages are cascoded using source degeneration with a resistor for low noise and high linearity, and the third cascaded stage is utilized for high gain. The designed UWB LNA exhibits a measured gain of 17.4 ± 1 dB between 312 and GHz and a 3 dB bandwidth of 12.4 GHz (1.6–14 GHz). It achieves a noise figure (NF) of 2.5–4.3 dB and an output P1dB of 15 dBm. The chip size is $3\times 1$${\mathrm{mm}}^2$, and it operates without the need for any external components. When compared to LNAs in the literature, the proposed design stands out for its flat gain in the specified frequency band, making the LNA particularly attractive for volume-limited and power-constrained applications. Full article

In resistive polymer humidity sensors, the quality of the resistor chips directly affects the performance. Detecting chip defects remains challenging due to the scarcity of defective samples, which limits traditional supervised-learning methods requiring abundant labeled data. While few-shot learning (FSL) shows promise for industrial defect detection, existing approaches struggle with mixed-scene conditions (e.g., daytime and night-version scenes). In this work, we propose a crossed wavelet convolution network (CWCN), including a dual-pipeline crossed wavelet convolution training framework (DPCWC) and a loss value calculation module named ProSL. Our method innovatively applies wavelet transform convolution and prototype learning to industrial defect detection, which effectively fuses feature information from multiple scenarios and improves the detection performance. Experiments across various few-shot tasks on chip datasets illustrate the better detection quality of CWCN, with an improvement in mAP ranging from 2.76% to 16.43% over other FSL methods. In addition, experiments on an open-source dataset NEU-DET further validate our proposed method. Full article

A new control system implemented with a single-stage DC-DC controller to power an LED headlamp for automotive applications is presented in this work. Daytime running light (DRL), low beam (LB), high beam (HB) and adaptive driving beam (ADB) are typical functions requiring a dedicated LED driver solution to fulfill car maker requirements for front-light applications. Single-stage drivers often exhibit a significant overshoot in LED current during transitions from driving a higher number of LEDs to a lower number. To maintain LED reliability, this current overshoot must remain below the maximum current rating of the LEDs. If the overshoot overcomes this limit, it can cause permanent damage to the LEDs or reduce their lifespan. To preserve LED reliability, a comprehensive system has been proposed to minimize the peak of LED current overshoots, especially during transitions between different operating modes or LED string configurations. A key feature of the proposed system is the implementation of a parallel discharging path to be activated only when the current flowing in the LEDs is higher than a predefined threshold. A prototype incorporating an integrated test chip has been developed to validate this approach. Measurement results and comparison with state-of-the-art solutions available in the market are shown. Furthermore, a critical aspect to be considered is the proper dimensioning of the discharging path. It requires careful considerations about the gate driver capabilities, the discharging resistor values, and the thermal management of the dumping element. For this purpose, an extensive study on how to size the relative components is also presented. Full article

Based on the GSMC 180 nm SiGe BiCMOS process, a parallel-summation logarithmic amplifier is presented in this paper. The logarithmic amplifier adopts a cascaded structure of nine-stage fully-differential limiting amplifiers (LA) to achieve high dynamic range. The ten-stage rectifier completes the conversion of amplified voltage to a logarithmic current signal. A log slope adjuster is proposed. It can provide slopes of 17–30 mV/dB by configuring an off-chip resistor to meet the detection requirements of different input power. Meanwhile, a power-down control unit is designed to reduce the power consumption to only 162 μW in standby mode. The post-simulation results show that under 5 V power supply voltage, the dynamic range exceeds 80 dB and the 3 dB bandwidth is 20 MHz–4 GHz. It also has a fast response time of 42 ns with a power consumption of 109 mW in normal operation mode. Full article

This paper presents a highly linear two-stage InGaP/GaAs power amplifier integrated circuit (PAIC) using a dynamic predistorter for 5G small-cell applications. The proposed predistorter, based on a diode-connected transistor, utilizes a supply voltage to accurately control the linearization characteristics by adjusting its dc current. It is connected in parallel with an inter-stage of the two-stage PAIC through a series configuration of a resistor and an inductor, and features a shunt capacitor at the base of the transistor. These passive components have been optimized to enhance the linearization performance by managing the RF signal’s coupling to the diode. Using these optimized components, the AM−AM and AM−PM nonlinearities arising from the nonlinear resistance and capacitance in the diode can be effectively used to significantly flatten the AM−AM and AM−PM characteristics of the PAIC. The proposed predistorter was applied to the 2.6 GHz two-stage InGaP/GaAs HBT PAIC. The IC was tested using a 5 × 5 mm² module package based on a four-layer laminate. The load network was implemented off-chip on the laminate. By employing a continuous-wave (CW) signal, the AM−AM and AM−PM characteristics at 2.55–2.65 GHz were improved by approximately 0.05 dB and 3°, respectively. When utilizing the new radio (NR) signal, based on OFDM cyclic prefix (CP) with a signal bandwidth of 100 MHz and a peak-to-average power ratio (PAPR) of 9.7 dB, the power-added efficiency (PAE) reached at least 11.8%, and the average output power was no less than 24 dBm, achieving an adjacent channel leakage power ratio (ACLR) of −40.0 dBc. Full article

Solar photovoltaic (PV) panels are the best solution to reduce greenhouse gas emissions by fossil fuel combustion, with global capability now exceeding 714 GW due to rapid technological advances in solar panels (SPs). However, SPs’ efficiency and lifespan remain limited due to the absence of advanced fault-detection systems, and they are prone to short circuits (SC), open circuits (OC), and power degradation. Therefore, this large-scale production requires reliable, real-time fault diagnosis to maintain panel performance. However, traditional diagnostic methods implemented using MPPT, neural networks, or microcontroller-based systems often rely on complex computational algorithms and are not cost-effective. So, this paper proposes a diagnostic system composed of six functional blocks to address this issue. The proposed system was initially verified using an Intel DE-10 Lite FPGA board. Once its functionality was confirmed, an ASIC design was proposed for mass production, offering a significantly lower implementation cost and reduced hardware complexity than prior methods. Different circuit designs were developed for each of the six blocks. All designs were created using Cadence software and TSMC 180 nm technology files. The basic components used in these designs include PMOS transistors with 300 nm channel length and 2 µm width, NMOS transistors with 350 nm channel length and 2 µm width, as well as resistors and capacitors. Differential amplifiers with a gain of 40 dB were used for voltage and current sensing from the SP. The chip activation signal generator circuit was designed with an adjustable frequency and generated 120 MHz and 100 MHz signals in this work. The decision-making block, Logic Driver Circuit, was innovatively implemented using a reduced number of transistors. A custom memory block with a reset switch was also implemented to store the fault value detected at the SP. Finally, the proposed ASIC was implemented for fabrication, which is highly cost-effective in mass production and does not require complex computational stages. Full article

This paper presents an in situ time-based sensor designed to provide process authentication. The proposed sensor leverages the inherent metal routing within the chip to measure the RC time-constants of interconnects. However, since the routing metal is typically designed to minimize resistance and capacitance, the resulting small RC time-constants pose a challenge for direct measurement. To overcome this challenge, a “three-configuration” measurement approach is introduced, incorporating two auxiliary components—poly resistor and metal-insulator-metal (MIM) capacitor—to generate three amplified RC time-constants and, subsequently, deduce the routing time-constant. Compared to directly measuring the routing time-constants, this approach reduces measurement error by over 82% while incurring only a 25% area penalty. A straightforward analytical model is presented, taking into account the impact of parasitic capacitances within the discharge path. This analytical model exhibits an excellent concurrence with simulated results, with a maximum difference of only 2.6% observed across all three configurations and a 3.2% variation in the derived routing time-constant. A set of five variants of the time-based sensor are realized using a 130 nm CMOS process. Each variant consists of 44 samples distributed across 11 dies on two wafers. To verify the precision of the proposed sensor, identical resistors and capacitors are fabricated alongside them, forming a direct measurement array (DMA) that is measured using external equipment. After adjusting the routing resistance and capacitance values in the simulations to correspond to the mean values obtained from the DMA measurements, the proposed sensor’s measured results demonstrate a close alignment with simulations, exhibiting a maximum error of only 6.1%. Full article

This paper introduces a compact multi-stage Wilkinson power divider/combiner (WPDC) topology which enables broadband operation with isolation capacitors and requiring only one single isolation resistor. The application of an L network for even-mode impedance matching and a π network for odd-mode impedance matching results in a more compact circuit layout and lower insertion loss compared to conventional WPDC designs. A K- and Ka-band WPDC is designed using a 45RFE process with measurements verifying the proposed topology. The results of a two-stage WPDC show an insertion loss below 0.7 dB, isolation better than 20 dB, and input/output return loss exceeding 12 dB across the frequency range of 18.6 to 33.6 GHz. The corresponding amplitude imbalance is within 0.06 dB, and the phase difference is below 0.8 degrees. The core chip size is 210 μm × 186 μm, which is only 0.018 λ₀ × 0.016 λ₀ at the center frequency of 26.1 GHz. Thus, this integrated passive component holds significant promise as a viable solution for wideband applications. Full article

This paper presents a wide-tuning-range, low-power tunable active inductor (AI) designed and fabricated using 130 nm CMOS technology with six metal layers. To achieve high performance with a relatively small silicon area and low power consumption, the AI structure is carefully designed and optimized using a cascode stage, a feedback resistor, and multi-gate finger transistors. In the proposed circuit topology, inductance tuning is realized by adjusting both the bias current and the feedback resistor. The performance of the circuit is evaluated in terms of tuning range, quality factor, power consumption, and chip area. The functionality of the fabricated device is experimentally validated, and the fundamental characteristics of the active inductor are measured over a wide frequency range using a Cascade GSG probe, with results compared to simulations. Experimental measurements show that, under a 1 V supply, the AI achieves a self-resonant frequency (SRF) of 3.961 GHz and a quality factor (Q) exceeding 1586 at 2.383 GHz. The inductance is tunable between 6.7 nH and 84.4 nH, with a total power consumption of approximately 2 mW. The total active area, including pads, is 345 × 400 µm². Full article

During the thermal analysis of hazardous materials, the thermal instruments available may face the risk of contamination within heating chambers or damage to the instruments themselves. Herein, this work introduces an innovative detection technology that combines thermogravimetric and differential thermal analysis with an integrated MEMS cantilever. Integrating polysilicon thermocouples and a heat-driven resistor into a single resonant cantilever achieves remarkable precision with a mass resolution of 5.5 picograms and a temperature resolution of 0.0082 °C. Validated through the thermal analysis of nylon 6, the cantilever excels in detecting nanogram-level samples, making it ideal for analyzing hazardous materials like ammonium perchlorate and TNT. Notably, it has successfully observed the evaporation of TNT in an air atmosphere. The integrated MEMS cantilever detection chip offers a groundbreaking micro-quantification solution for hazardous material analysis, significantly enhancing safety and opening new avenues for application. Full article

With the rapid growth of data center demand driven by AI, high-speed optical modules (such as 800G and 1.6T) have become critical components. Traditional 800G modules face issues such as complex processes and large sizes due to the separate packaging of EML chips, AlN substrates, and capacitors. This study proposes a high-speed EML module based on silicon integration, where resistors, capacitors, and AuSn soldering areas are integrated onto the silicon substrate, enabling the bonding of the EML chip, reducing packaging costs, and enhancing scalability. Key achievements include: the development of a 100G EML chip; the fabrication of a high-speed silicon integrated carrier; successful Chip-on-Carrier (COC) packaging and testing, with a laser output power of 10 mW, extinction ratio of 10 dB, and bandwidth greater than 40 GHz; and reliability verified through 500 h of aging tests. This study provides an expandable solution for next-generation high-speed optical interconnects. Full article