Search Results (48)

Carbon nanotube field-effect transistors (CNTFETs) are becoming a strong competitor for the next generation of high-performance, energy-efficient integrated circuits due to their near-ballistic carrier transport characteristics and excellent suppression of short-channel effects. However, CNT FETs with large diameters and small band gaps exhibit obvious bipolarity, and gate-induced drain leakage (GIDL) contributes significantly to the off-state leakage current. Although the asymmetric gate strategy and feedback gate (FBG) structures proposed so far have shown the potential to suppress CNT FET leakage currents, the devices still lack scalability. Based on the analysis of the conduction mechanism of existing self-aligned gate structures, this study innovatively proposed a design strategy to extend the length of the source–drain epitaxial region (L_ext) under a vertically stacked architecture. While maintaining a high drive current, this structure effectively suppresses the quantum tunneling effect on the drain side, thereby reducing the off-state leakage current (I_off = 10⁻¹⁰ A), and has good scaling characteristics and leakage current suppression characteristics between gate lengths of 200 nm and 25 nm. For the sidewall gate architecture, this work also uses single-walled carbon nanotubes (SWCNTs) as the channel material and uses metal source and drain electrodes with good work function matching to achieve low-resistance ohmic contact. This solution has significant advantages in structural adjustability and contact quality and can significantly reduce the off-state current (I_off = 10⁻¹⁴ A). At the same time, it can solve the problem of off-state current suppression failure when the gate length of the vertical stacking structure is 10 nm (the total channel length is 30 nm) and has good scalability. Full article

This paper elaborates on the proposal of a new analytical model for a non-ballistic transport scenario for Schottky barrier carbon nanotube field effect transistors (SB-CNTFETs). The non-ballistic transport scenario depends on incorporating the effects of acoustic phonon (A-Ph) and optical phonon (O-Ph) electron scattering mechanisms. The analytical model is rooted in the solution of the Landauer integral equation, which is modified to account for non-ballistic transport through a set of approximations applied to the Wentzel–Kramers–Brillouin (WKB) transmission probability and the Fermi–Dirac distribution function. Our proposed model was simulated to evaluate the total current and transconductance, considering scenarios both with and without the electron–phonon scattering effect. The simulation results revealed a substantial decrease of approximately 78.6% in both total current and transconductance due to electron–phonon scattering. In addition, we investigated the impact of acoustic phonon (A-Ph) and optical phonon (O-Ph) scattering on the drain current under various conditions, including different temperatures, gate lengths, and nanotube chiralities. This comprehensive analysis helps in understanding how these parameters influence device performance. Compared with experimental data, the model’s simulation results demonstrate a high degree of agreement. Furthermore, our fully analytical model achieves a significantly faster runtime, clocking in at around 2.726 s. This validation underscores the model’s accuracy and reliability in predicting the behavior of SB-CNTFETs under non-ballistic conditions. Full article

The creation of carbon nanotubes has sparked a paradigm shift in the post-silicon era because of their decent electronic and optical properties. However, interface traps pose an obstacle in the realization of high-performance carbon nanotube field-effect transistors (CNTFETs). Herein, we systematically investigate the C−V characteristics of CNTFETs and propose a small-signal equivalent model to decouple the effects arising from interface traps. Moreover, intrinsic parameters associated with interface traps can be feasibly extracted using this approach. An analytical capacitance model is further developed to be incorporated into the well-established CNTFET virtual source model, and excellent agreement has been achieved between our simulation and the measured results of the as-fabricated MOSCAP. The models developed here help to gain insight into the physical properties of high-κ dielectric interface traps subjected to different processes and inform strategies to achieve high-performance CNTFETs. Full article

Accurate monitoring of sodium and potassium ions in biological fluids is crucial for diseases related to electrolyte imbalance. Low-dimensional materials such as carbon nanotubes can be used to construct biochemical sensors based on high-performance field effect transistor (FET), but they face the problems of poor device consistency and difficulty in stable and reliable operation. In this work, we mass-produced carbon nanotube (CNT) floating-gate field-effect transistor devices with high uniformity and consistency through micro-/nanofabrication technology to improve the accuracy and reliability of detection without the need for statistical analysis based on machine learning. By introducing waterproof hafnium oxide gate dielectrics on the CNT FET channel, we not only effectively protect the channel area but also significantly improve the stability of the sensor. We have prepared array sensing technology based on CNT FET that can detect potassium, sodium, calcium, and hydrogen ions in artificial cerebrospinal fluid. The detection concentration range is 10 μM–100 mM and pH 3–pH 9, with a sensitivity close to the Nernst limit, and exhibits selective and long-term stable responses. This could help achieve early diagnosis and real-time monitoring of central nervous system diseases, highlighting the potential of this ion-sensing platform for highly sensitive and stable detection of various neurobiological markers. Full article

Carbon nanotube (CNT)–metal Schottky contacts are widely employed in different types of electronic devices, including field effect transistors (FET) and gas sensors. CNTs are normally considered stable on electronic properties with gas adsorptions. In this work, performance changes of the multi-walled carbon nanotube (MWCNT)–metal junctions related to hydrogen adsorptions were illustrated. MWCNT/Pd and MWCNT/Au Schottky junctions based resistive sensors were constructed to investigate the low-pressure gas sensing performances for hydrogen in the range of 10⁻⁶~10⁻³ Pa. Two types of sensors presented opposite behaviors with hydrogen adsorptions, i.e., the sensor resistance rose for the MWCNT/Pd sensor but dropped for the MWCNT/Au sensor with increasing hydrogen pressure. The work function reductions of Pd and CNT are considered the key cause, which could change the Schottky barrier properties dramatically. This behavior may play crucial roles for the accurate utilization of CNT-based Schottky devices. Full article

Carbon nanotube field-effect transistors (CNT-FETs) have shown great promise in infrared image detection due to their high mobility, low cost, and compatibility with silicon-based technologies. This paper presents the design and simulation of a column-level analog front-end (AFE) circuit tailored for carbon-based short-wave infrared (SWIR) photodetectors. The AFE integrates a Capacitor Trans-impedance Amplifier (CTIA) for current-to-voltage conversion, coupled with Correlated Double Sampling (CDS) for noise reduction and operational amplifier offset suppression. A 10-bit/125 kHz Successive Approximation analog-to-digital converter (SAR ADC) completes the signal processing chain, achieving rail-to-rail input/output with minimized component count. Fabricated using 0.18 μm CMOS technology, the AFE demonstrates a high signal-to-noise ratio (SNR) of 59.27 dB and an Effective Number of Bits (ENOB) of 9.35, with a detectable current range from 500 pA to 100.5 nA and a total power consumption of 7.5 mW. These results confirm the suitability of the proposed AFE for high-precision, low-power SWIR detection systems, with potential applications in medical imaging, night vision, and autonomous driving systems. Full article

Benzene, as a typical toxic gas and carcinogen, is an important detection object in the field of environmental monitoring. However, it remains challenging for the conventional resistance-type gas sensor to effectively detect low-concentration (ppb-level) benzene gas molecules, owing to their insufficient reaction activation energy, especially when operating at room temperature. Herein, a field-effect transistor (FET)-type gas sensor using carbon nanotubes as a channel material is proposed for the efficient detection of trace benzene, where carbon nanotubes (CNTs) with high semiconductor purity act as the main channel material, and ZnO/WS₂ nanocomposites serve as the gate sensitive material. On the basis of the remarkable amplification effect in CNTs-based FET, the proposed gas sensor manifests desirable sensitive ability with the detection limit as low as 500 ppb for benzene even working at room temperature, and the sensor also exhibits fast response speed (90 s), high consistency with a response deviation of less than 5%, and long-term stability of up to 30 days. Furthermore, utilizing Tenax TA as the screening unit, the as-proposed gas sensor can achieve the feasible selective detection of benzene. These experimental results demonstrate that the strategy proposed here can provide significant guidance for the development of high-performance gas sensors to detect trace benzene gas at room temperature. Full article

The scaling of bulk Si-based transistors has reached its limits, while novel architectures such as FinFETs and GAAFETs face challenges in sub-10 nm nodes due to complex fabrication processes and severe drain-induced barrier lowering (DIBL) effects. An effective strategy to avoid short-channel effects (SCEs) is the integration of low-dimensional materials into novel device architectures, leveraging the coupling between multiple gates to achieve efficient electrostatic control of the channel. We employed TCAD simulations to model multi-gate FETs based on various dimensional systems and comprehensively investigated electric fields, potentials, current densities, and electron densities within the devices. Through continuous parameter scaling and extracting the sub-threshold swing (SS) and DIBL from the electrical outputs, we offered optimal MoS₂ layer numbers and single-walled carbon nanotube (SWCNT) diameters, as well as designed structures for multi-gate FETs based on monolayer MoS₂, identifying dual-gate transistors as suitable for high-speed switching applications. Comparing the switching performance of two device types at the same node revealed CNT’s advantages as a channel material in mitigating SCEs at sub-3 nm nodes. We validated the performance enhancement of 2D materials in the novel device architecture and reduced the complexity of the related experimental processes. Consequently, our research provides crucial insights for designing next-generation high-performance transistors based on low-dimensional materials at the scaling limit. Full article

Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data plane devices, enabling the centralized control and programmability of network behavior. This paper uses the ternary system to improve the Central Processing Unit (CPU) inside the SDN controller to enhance network management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared to the binary circuit regarding the chip area, propagation delay, and energy consumption. Moreover, the Carbon Nanotube Field-Effect Transistor (CNTFET) shows improvement compared to other transistor technologies regarding energy efficiency and circuit speed. To the best of our knowledge, this is the first time that a ternary design has been applied inside the CPU of an SDN controller. Earlier studies focused on Ternary Content-Addressable Memory (TCAM) in SDN. This paper proposes a new 1-trit Ternary Full Adder (TFA) to decrease the propagation delay and the Power–Delay Product (PDP). The proposed design is compared to the latest 17 designs, including 15 designs that are 1-trit TFA CNTFET-based, 2-bit binary FA FinFET-based, and 2-bit binary FA CMOS-based, using the HSPICE simulator, to optimize the CPU utilization in SDN environments, thereby enhancing programmability. The results show the success of the proposed design in reducing the propagation delays by over 99% compared to the 2-bit binary FA CMOS-based design, over 78% compared to the 2-bit binary FA FinFET-based design, over 91% compared to the worst-case TFA, and over 49% compared to the best-case TFAs. Full article

As the traditional silicon-based CMOS technology advances into the nanoscale stage, approaching its physical limits, the Carbon Nanotube Field-effect Transistor (CNTFET) is considered to be the most significant transistor technology beyond Moore’s era. The CNTFET has a quasi-one-dimensional structure so that the carrier can realize ballistic transport and has very high mobility. At the same time, a single CNTFET can integrate hundreds of nanowires as the conductive channels, enabling significant current transport capabilities even in low supply voltage, thereby providing a foundational basis for achieving nanoscale ultra-large-scale analog/logic circuits. This paper summarizes the development status of the CNTFET compact model and digital/analog/RF integrated circuits. The challenges faced by SPICE modeling and circuit design are analyzed. Meanwhile, solutions to these challenges and development trends of carbon-based transistors are discussed. Finally, the future application prospects of carbon-based integrated circuits are presented. Full article

This paper investigates the performance of vacuum gate dielectric doping-free carbon nanotube/nanoribbon field-effect transistors (VGD-DL CNT/GNRFETs) via computational analysis employing a quantum simulation approach. The methodology integrates the self-consistent solution of the Poisson solver with the mode space non-equilibrium Green’s function (NEGF) in the ballistic limit. Adopting the vacuum gate dielectric (VGD) paradigm ensures radiation-hardened functionality while avoiding radiation-induced trapped charge mechanisms, while the doping-free paradigm facilitates fabrication flexibility by avoiding the realization of a sharp doping gradient in the nanoscale regime. Electrostatic doping of the nanodevices is achieved via source and drain doping gates. The simulations encompass MOSFET and tunnel FET (TFET) modes. The numerical investigation comprehensively examines potential distribution, transfer characteristics, subthreshold swing, leakage current, on-state current, current ratio, and scaling capability. Results demonstrate the robustness of vacuum nanodevices for high-performance, radiation-hardened switching applications. Furthermore, a proposal for extrinsic enhancement via doping gate voltage adjustment to optimize band diagrams and improve switching performance at ultra-scaled regimes is successfully presented. These findings underscore the potential of vacuum gate dielectric carbon-based nanotransistors for ultrascaled, high-performance, energy-efficient, and radiation-immune nanoelectronics. Full article

Carbon nanotubes have excellent electrical properties and can be used as a new generation of semiconductor materials. This paper presents a compact model for carbon nanotube field-effect transistors (CNTFETs). The model uses a semi-empirical approach to model the current–voltage properties of CNTFETs with gate lengths exceeding 100 nm. This study introduces an innovative approach by proposing physical parametric reference lengths ($L_{ref}$), which facilitate the integration of devices of varying sizes into a unified modeling framework. Furthermore, this paper develops models for the bipolar properties of carbon nanotube devices, employing two distinct sets of model parameters for enhanced accuracy. The model offers a comprehensive analysis of the different capacitances occurring between the electrodes within the device. The simulation of the model shows good agreement with the experimental measurements, confirming the model’s validity. The model is implemented in the Verilog-A hardware description language, with the circuit being subsequently constructed and subjected to simulations via the HSPICE tool. The CNTFET-based inverter exhibits a gain of 7.022 and a delay time of 16.23 ps when operated at a voltage of 1.2 V. Full article

Compared to single-gate CNTFET, dual-gate structures have better electrostatic control over nanowire conductive channels. However, currently, there is insufficient research on the back-gate effect in a compact model of dual-gate CNTFET. This paper presents an improved dual-gate carbon nanotube field effect transistor (CNTFET) compact model. The functional relationship between the back-gate voltage (V_bg) and threshold voltage (V_th) is derived. And a voltage reference regulation mechanism is adopted so that the back-gate effect can be accurately reflected in the DC transfer characteristics. The influence of gate voltage and drain voltage on transmission probability is analyzed. Meanwhile, the drain current is optimized by modifying the mobility equation. This compact model is built based on Verilog-A hardware language and supports the Hspice simulation tool. Within the supply voltage of 2 V, the simulation results of the proposed compact model are in good agreement with the measurement results. Finally, based on the compact model, an operational amplifier is designed to verify its correctness and feasibility in analog integrated circuits. When the power supply voltage is 1.8 V, and the load capacitance is 2 pF, the gain is 11.8 dB, and the unit-gain-bandwidth (UGB) is 214 kHz, which proves the efficiency of our compact model. Full article

As the semiconductor industry enters the post-Moore era, the carbon nanotube field-effect transistor (CNTFET) has become a powerful substitute for silicon-based transistors beyond 5 nm process nodes due to its high mobility, low power consumption, and ultra-thin-body electrical advantages. Carbon-based transistor technology has made significant progress in device manufacture and preparation, but carbon-based process design kits (PDKs) that meet the standards of commercial design tools are still an important bottleneck hindering the development of carbon-based integrated circuits. For the first time, a complete full-custom 90 nm CNTFET PDK is proposed in this paper, which includes Pcells for transistors, resistors, and capacitors; a compact model; DRC/LVS/PEX rules; and a standard cell and timing library. It can support the entire design flow of analog, digital, and mixed-signal carbon-based integrated circuits. To achieve an accurate compact model, the back-gate effect of CNTFETs and the influence of gate/drain voltage on transport probability are analyzed. Then the theoretical formulas for mobility and channel current are established. The comparison of the simulation and test results of CNTFET characteristics proves the accuracy of the compact model. Using this PDK, combined with standard IC design tools and design flow, the circuit and layout of an operational amplifier, SRAM, and 8-bit counter are completed. The simulation results verify the correctness and effectiveness of the PDK, laying a solid foundation for the large-scale industrialization of carbon-based integrated circuits. Full article

The preparation of semiconducting carbon nanotube (s-CNT) thin films by solution processing has become the mainstream approach nowadays. However, residual polymers are always inevitable during the sorting of s-CNTs in solution. These residual polymers will degrade the electrical properties of the CNTs. Although several post-treatment approaches have been reported to be effective in improving the performance of the device, there is no deep analysis and comprehensive comparison of these approaches, so there is no overall guidance on the optimum treatment of CNTs for performance improvement. In this work, we characterize CNT thin film with three post-treatment methods, including annealing (A), yttrium oxide coating and decoating (Y), and annealing combined with YOCD (A + Y), and evaluate and compare the performance of Field Effect Transistors (FETs) based on the above mentioned CNT thin film. The result shows that the CNT thin film treated by the A + Y method is the clearest and flattest; the average roughness determined from the overall AFM image is reduced by 28% (from 1.15–1.42 nm (O) to 0.826–1.03 nm (A + Y)), which is beneficial in improving the device contact quality, uniformity, and stability. The on-state current (I_on) of the FETs with CNTs treated by A, Y, and A + Y is improved by 1.2 times, 1.5 times, and 1.75 times, respectively, compared with that of FETs fabricated by untreated CNTs (O for original CNTs), indicating that the A + Y is the optimum post-treatment method for the A + Y and combines the effect of the other two methods. Accordingly, the contact and channel resistance (2R_c and R_ch) of the CNT FETs treated by different post-treatment methods including A, Y, and A + Y is reduced by 0.18/0.24 times, 0.37/0.32 times, and 0.48/0.41 times, respectively. The ratio of improvement in device performance is about 1:2 for the contact and channel sections for a transistor with a 500 nm channel length, and this ratio will go up further with the channel length scaling; together with the decay in the channel resistance optimization effect in the scaling device, it is necessary to adopt more methods to effectively reduce the contact resistance further. Full article