Search Results (28)

This paper introduces a novel control archetype designed to mitigate high-altitude electromagnetic pulse (HEMP) $E_3$ disturbances on the power grid, as well as information on performance and specifications of different control laws for the controller archetype. This method of protection has been overlooked in the literature until now. A controlled voltage supply is placed on the load-side of a transformer, diverting unwanted power from the transformer core to prevent saturation. The controlled voltage source is modeled using four control laws: an integral controller (capacitor), Linear Quadratic Regulator (LQR), an energy storage minimized feedforward control law, and a Hamiltonian feedback law. Results show that the Hamiltonian feedback law and the energy storage minimization feedforward control law both flat-line magnetic flux with similar actuator requirements. The LQR approach requires less energy storage than the other two laws, depending on control tuning, as it allows greater exogenous current flow through the neutral path to ground. This leads to further optimization opportunities based on acceptable exogenous current levels. A sweep of different LQR gains revealed a reduction of approximately $32\%$ in minimum control effort, $47\%$ in minimum power to maintain saturation bounds, $20\%$ in energy storage requirements, and $59\%$ in required controller bandwidth. Voltage and bandwidth requirements of the load-side controller are comparable to neutral blocking requirements with energy and power requirements being higher for the load-side controller. This, however, comes with the benefit of being able to use pre-existing assets—neutral blocking devices have not been deployed. Additionally, the load-side blocking capacitor degrades transformer performance compared to the unmitigated system. Full article

This paper explores the feasibility of implementing a flywheel energy storage system designed to generate voltage for the purpose of mitigating current flow through the transformer neutral path to ground, which is induced by a high-altitude electromagnetic pulse (HEMP) event. The active flywheel system presents the advantage of employing custom optimal control laws, in contrast to the conventional approach of utilizing passive blocking capacitors. A Hamiltonian-based optimal control law for energy storage is derived and integrated into models of both the transformer and the flywheel energy storage system. This Hamiltonian-based feedback control law is subsequently compared against an energy-optimal feedforward control law to validate its optimality. The analysis reveals that the required energy storage capacity is $13\mathrm{Wh}$, the necessary power output is less than $5\mathrm{kW}$ at any given time during the insult, and the required bandwidth for the controller is around $5\mathrm{Hz}$. These specifications can be met by commercially available flywheel devices. This methodology can be extended to other energy storage devices to ensure that their specifications adequately address the requirements for HEMP mitigation. Full article

Enhancing the resilience of renewable energy systems in ultra-weak grids is crucial for promoting sustainable energy adoption and ensuring a reliable power supply during disturbances. Ultra-weak grids characterized by a very low Short-Circuit Ratio, less than 2, and high grid impedance significantly impair voltage and frequency stability, imposing challenging conditions for Inverter-Based Resources. To address these challenges, this paper considers a 110 KVA, three-phase, two-level Voltage Source Converter, interfacing a 700 V DC link to a 415 V AC ultra-weak grid. X/R = 1 is controlled using Sinusoidal Pulse Width Modulation, where the Grid-Connected Converter operates in Grid-Forming Mode to maintain voltage and frequency stability under a steady state. During symmetrical and asymmetrical faults, the converter transitions to Grid-Following mode with current control to safely limit fault currents and protect the system integrity. After fault clearance, the system seamlessly reverts to Grid-Forming Mode to resume voltage regulation. This paper proposes an improved control strategy that integrates voltage feedforward reactive power support and virtual capacitor-based virtual inertia using Active Disturbance Rejection Control, a robust, model-independent controller, which rapidly rejects disturbances by regulating d and q-axes currents. To test the practicality of the proposed system, real-time implementation is carried out using the OPAL-RT OP4610 platform, and the results are experimentally validated. The results demonstrate improved fault current limitation and enhanced DC link voltage stability compared to a conventional PI controller, validating the system’s robust Fault Ride-Through performance under ultra-weak grid conditions. Full article

This paper proposes a three-stage op amp based on the SOI (silicon-on-insulator) process, which achieves a low offset voltage and temperature coefficient across a wide temperature range from −40 °C to 250 °C. It can be used in aerospace, oil and gas exploration, automotive electronics, nuclear industry, and in other fields where the ability of electronic devices to withstand high-temperature environments is strongly required. By utilizing a SC (Switched Capacitor) notch filter, the op amp achieves low input offset in a power-efficient manner. The circuit features a multi-path nested Miller compensation structure, consisting of a low-speed channel and a high-speed channel, which switch according to the input signal frequency. The input-stage operational amplifier is a fully differential, rail-to-rail design, utilizing tail current control to reduce the impact of common-mode voltage on the transconductance of the input stage. The two-stage operational amplifier uses both cascode and Miller compensation, minimizing the influence of the feedforward signal path and improving the amplifier’s response speed. The prototype op amp is fabricated in a 0.15 µm SOI process and draws 0.3 mA from a 5 V supply. The circuit occupies a chip area of 0.76 mm². The measured open-loop gain exceeds 140 dB, with a 3 dB bandwidth greater than 100 kHz. The amplifier demonstrates stable performance across a wide temperature range from −40 °C to 250 °C, and exhibits an excellent input offset of approximately 20 µV at room temperature and an offset voltage temperature coefficient of 0.7 μV/°C in the full temperature range. Full article

A low-noise amplifier (LNA) design with the operation of concurrent dual-band for Global Navigation Satellite System (GNSS) receivers with single channel is presented in this work. This LNA structure has an inductively degenerated cascode architecture and is pseudo-differential, operating at two frequencies simultaneously (1.2 GHz and 1.57 GHz). Two noise reduction/cancellation techniques, using load capacitor and feedforward path, respectively, are proposed resulting in an excellent improvement in the noise figure (NF). The input matching circuit uses both series and parallel resonant components to enable concurrency. The adopted pseudo-differential structure results in input balun elimination. Inductively degenerated cascode topology provides both input impedance and optimum noise impedance matching. The soundness of the proposed approach has been demonstrated in a 0.18-µm CMOS technology by TSMC. Simulation results show that at 1.2 GHz and 1.57 GHz the LNA achieves −13 dB and −11 dB of input matching, 24.6 dB and 24.7 dB of gain, 1.47 dB and 1.43 dB of NF, respectively. The input-referred 1-dB compression point (IP_1dB) is around −16 dBm, while the input-referred third-order intercept point (IIP₃) achieves −2.2 dBm at 1.2 GHz and −0.6 dBm at 1.57 GHz. The LNA draws about 13 mA from a 1.8-V supply voltage. Full article

This article presents a proportional–derivative (PD) type output voltage regulator without the current feedback, taking into account system parameter and load variations. The main advantages are given as follows: First, the first-order output voltage derivative observer is developed without the requirement of system parameter information, which makes it possible to stabilize the system without current sensing. Second, a simple self-tuner implements the feedback-loop adaptation by updating the desired dynamics accordingly. Third, the observer-based active damping injection for the PD-type controller results in the closed-loop system order reduction to 1 by the pole-zero cancellation, including the disturbance observer as a feed-forward term. The prototype uninterruptible power supply system comprised of a 3 kW three-phase inverter, inductors, and capacitors verifies the practical merits of the proposed technique for linear and nonlinear loads. Full article

A second-order delta-sigma modulator (DSM) is proposed for readout integrated circuits of sensor applications requiring a small area and low-power consumption. The proposed second-order CIFF DSM with the architecture of cascaded-of-integrator feedforward (CIFF) basically consists of two integrators, a 3-bit quantizer, data-weighted averaging (DWA) circuit, and clock generator. The use of the 3-bit quantizer instead of the single-bit quantizer reduces the size of the feedback capacitor in the first integrator. The 3-bit quantizer is designed based on a successive approximation register analog-to-digital converter for small area and low power implementation. Furthermore, the proposed second-order CIFF DSM has a single supply without an additional reference driver while having a wide analog input voltage range with rail to rail. The proposed second-order CIFF DSM, implemented using a 130 nm 1-poly 6-metal CMOS process with a supply of 1.5 V, has an area of 0.096 mm². It has a sampling frequency of 500 kHz for the implementation of an input bandwidth of 2 kHz and an oversampling ratio of 125. The measured peak signal-to-noise and distortion ratio is approximately 90 dB when the differential analog input signal has a frequency of 353 Hz and an amplitude of 1.2 Vpp. The measured dynamic range is approximately 96.3 dB. Full article

This paper presents a low-voltage low-power chopper-stabilized differential difference amplifier (DDA) realized using 40 nm CMOS technology. Operating with a supply voltage of 0.5 V, a three-stage DDA has been employed to achieve an open-loop gain of 89 dB, while consuming just 0.74 μW of power. The proposed DDA incorporates feed-forward frequency compensation and a Type II compensator to achieve pole-zero cancellation and damping factor control. The DDA has a unity-gain bandwidth (UGB) of 170 kHz, a phase margin (PM) of 63.98°, and a common-mode rejection ratio (CMRR) of up to 100 dB. This circuit can effectively drive a 50 pF capacitor in parallel with a 300 kΩ resistor. The use of the chopper stabilization technique effectively mitigates the offset and 1/f noise. The chopping frequency of the chopper modulator is 5 kHz. The input noise is 245 nV/sqrt (Hz) at 1 kHz, and the input-referred offset under Monte Carlo cases is only 0.26 mV. Such a low-voltage chopper-stabilized DDA will be very useful for analog signal processing applications. Compared to the reported chopper DDA counterparts, the proposed DDA is regarded as that with one of the lowest supply voltages. The proposed DDA has demonstrated its effectiveness in tradeoff design when dealing with multiple parameters pertaining to power consumption, noise, and bandwidth. Full article

In this paper, a solution is proposed to the problem of the unequal phase imbalance of output voltage caused by a three-phase, four-wire, split capacitor inverter when the load is unbalanced. First, the triple-loop control strategy was used to solve the unequal amplitude problem. This method used the feedforward + feedback composite control strategy on the inductor current inner-loop and voltage mid-loop to decrease the disturbance of the power and load. And the Root Mean Square (RMS) of voltage on the outer-loop completed the control of amplitude for the three-phase voltage. Second, to solve the imbalanced phase problem, the imbalance operation mechanism of the three-phase four-wire inverter was analyzed. It is known from the analysis that the phase imbalance is related to the DC-side splitting capacitance. The function relations between the DC-side capacitance and phase angle between each phase was simulated by MATLAB. But, it was too complicated to calculate the magnitude of the capacitance value through the functional relationship. In order to simplify the design of the DC-side splitting capacitor, the relations among the imbalanced current, the voltage fluctuations of the DC-side capacitor and the harmonics of load voltage were analyzed. In addition, by following the requirement of the national standard about the harmonics of load voltage, a DC-side capacitor design was mentioned to decrease the influence of imbalanced phase. Finally, simulation and experimental results show that the three-phase load voltage is stable, the THD value is less than 3%, and three-phase voltage unbalance is less than 2%, thus verifying the effectiveness of the proposed DC-side split capacitor design and control strategy. Full article

Bridge sensors are widely used in military and civilian fields, and their demand gradually increases each year. Digital sensors are widely used in the military and civilian fields. High-precision and low-power analog-to-digital converters (ADCs) as sensor read-out circuits are a research hotspot. Sigma-delta ADC circuits based on switched-capacitor topology have the advantages of high signal-to-noise ratio (SNR), good linearity, and better compatibility with CMOS processes. In this work, a fourth-order feed-forward sigma-delta modulator and a digital decimation filter are designed and implemented with a correlated double sampling technique (CDS) to suppress pre-integrator low-frequency noise. This work used an active pre-compensator circuit for deep phase compensation to improve the system’s stability in the sigma-delta modulator. The modulator’s local feedback factor is designed to be adjustable off-chip to eliminate the effect of process errors. A three-stage cascade structure was chosen for the post-stage digital filter, significantly reducing the number of operations and the required memory cells in the digital circuit. Finally, the layout design and engineering circuit were fabricated by a standard 0.35 μm CMOS process from Shanghai Hua Hong with a chip area of 9 mm². At a 5 V voltage supply and sampling frequency of 6.144 MHz, the modulator power consumption is 13 mW, the maximum input signal amplitude is −3 dBFs, the 1 Hz dynamic range is about 118 dB, the modulator signal-to-noise ratio can reach 110.5 dB when the signal bandwidth is 24 kHz, the practical bit is about 18.05 bits, and the harmonic distortion is about −113 dB, which meets the design requirements. The output bit stream is 24 bits. Full article

This paper explores a current distortion problem in totem-pole bridgeless power factor correction (PFC) converters with average current mode (ACM) control. With in-depth modeling for the current and voltage loops, it was found that the current distortion is caused by the limited current loop bandwidth and input filter capacitor. These factors lead to the presence of a susceptance component in the input admittance, which degrades the power factor (PF) and total harmonic distortion (THD) of the PFC converter. To solve this problem, this paper proposes virtual admittance feedforward compensation (VAFC) and phase correction methods to adjust the input admittance to pure conductance. The VAFC can generate virtual admittance that compensates for susceptance components in the input admittance, while phase correction can generate an equivalent current source that offsets the current in input capacitors. Furthermore, a phase lock loop (PLL) is introduced to realize the VAFC, which reduces the feedforward interference caused by input voltage sampling noise. Finally, an experimental prototype was built to verify the effectiveness of the proposed strategies. According to the test results, the proposed compensation strategy improves the PF by 1.23%, while reducing the THD by 2.52% and achieving a peak efficiency of 98.69%. Full article

This paper presents the design, analysis, and control of a dual transformer-based bidirectional DC/DC resonant converter featuring balanced voltage stress across all the resonant capacitors. Compared to existing topologies, the proposed converter has a dual-rectifier structure on the secondary side, which allows operation over a wide load range with balanced voltage stress across all resonant components. The transformer stress is greatly reduced by employing two small transformers, thus greatly lowering thermal as well electrical stresses on the transformers’ windings. Furthermore, by operating the primary-side interleaved converter at a fixed 50% duty, input current ripples are significantly reduced. The proposed controller consists of a feedforward control part for effective system uncertainty compensation and a feedback control part for the convergence of system error dynamics. Notably, state-plane trajectory theory is employed to derive accurate feedforward compensation terms. Additionally, the effect of resonant elements’ parameter mismatch is analyzed in detail. The designed controller was implemented using the TI TMS320F28377D DSP on a 3.3 kW prototype hardware board. Detailed experimental investigations under tough, practical operating conditions corroborate an effective bidirectional power transfer operation with a balanced voltage stress distribution in each resonant element. Full article

Modular multilevel converter (MMC) tends to cause resonance instability in interconnected systems. Current studies on the stability of MMC mainly focus on high-voltage and large-capacity power systems, while the impedance modeling process of MMC ignores the harmonics of the submodule (SM) capacitor voltages and the influence of voltage feedforward control. The applicability of the MMC impedance model with fewer submodules is doubtful. According to the circuit structure and control mode, the AC-side sequence impedance model of the MMC is established, which takes into account the capacitor voltage balance control of submodules and voltage feedforward control. Based on the RT-Lab control hardware-in-loop (CHIL) test platform, the MMC impedance frequency scanning was carried out to verify the accuracy of the impedance modeling method. The influence of control parameters in different frequency bands on the impedance characteristics of MMC was studied. The AC terminal voltage feedforward causes phase lag in the mid-/high-frequency range and increases the risk of resonance. In the low-frequency range, the dynamics and control of capacitor voltages reduce the impedance magnitude of MMC. Using the resonance phenomenon of an MMC connected to a weak grid as an example, the high-frequency resonance mechanism caused by control parameters is analyzed from the perspective of the negative damping effect. The simulation results show that the detailed wideband impedance model can improve the accuracy of the stability analysis results. Full article

A wideband cascaded receiver and a stacked receiver using an improved clock strategy are proposed to support the software-defined radio (SDR). The improved clock strategy reduces the number of mixer switches and the number of LO clock paths required to drive the mixer switches. This reduces the dynamic power consumption. The cascaded receiver includes an inverter-based low-noise transconductance amplifier (LNTA) using a feed-forward technique to enhance the noise performance; a passive mixer; and an inverter-based transimpedance amplifier (TIA). The stacked receiver architecture is used to reduce the power consumption by sharing the current between the LNTA and the TIA from a single supply. It utilizes a wideband LNTA with a capacitor cross-coupled (CCC) common-gate (CG) topology, a passive mixer to convert the RF current to an IF current, an active inductor (AI) and a $1/f$ noise-cancellation (NC) technique to improve the noise performance, and a TIA to convert the IF current to an IF voltage at the output. Both cascaded and stacked receivers are simulated in 22 $\mathrm{n}$$\mathrm{m}$ CMOS technology. The cascaded receiver achieves a conversion-gain from 26 $\mathrm{d}$$\mathrm{B}$ to 36 $\mathrm{d}$$\mathrm{B}$, a double-sideband noise-figure (NFDSB) from $1.4$ $\mathrm{d}$$\mathrm{B}$ to $3.9$ $\mathrm{d}$$\mathrm{B}$, ${\mathrm{S}}_{11}<$$-10$ $\mathrm{d}$$\mathrm{B}$ and an IIP3 from $-7.5$ $\mathrm{d}$$\mathrm{Bm}$ to $-10.5$ $\mathrm{d}$$\mathrm{Bm}$, over the RF operating band from $0.4$ $\mathrm{G}$$\mathrm{Hz}$ to 12 $\mathrm{G}$$\mathrm{Hz}$. The stacked receiver achieves a conversion-gain from $34.5$ $\mathrm{d}$$\mathrm{B}$ to 36 $\mathrm{d}$$\mathrm{B}$, a NFDSB from $4.6$ $\mathrm{d}$$\mathrm{B}$ to $6.2$ $\mathrm{d}$$\mathrm{B}$, ${\mathrm{S}}_{11}<$$-10$ $\mathrm{d}$$\mathrm{B}$, and an IIP3 from $-21$ $\mathrm{d}$$\mathrm{Bm}$ to $-17.5$ $\mathrm{d}$$\mathrm{Bm}$, over the RF operating band from $2.2$ $\mathrm{G}$$\mathrm{Hz}$ to $3.2$ $\mathrm{G}$$\mathrm{Hz}$. The cascaded receiver consumes 11 m from a 1 $\mathrm{V}$ supply voltage, while the stacked receiver consumes $2.4$ m from a $1.2$ $\mathrm{V}$ supply voltage. Full article

Rectifiers are required by the devices connected to the distribution end of the electrical power networks for AC/DC conversion. The line current becomes non-sinusoidal when a capacitor with a significant value is used to mitigate the output voltage ripple. This type of converter emulates a non-resistive impedance to the grid, due to which a bend occurs in the shape of the line current, which results in high total harmonic distortion and a low power factor. For perceiving sinusoidal current, power factor correction techniques are required. A digital controller for parallel-connected buck-boost power factor correctors is presented in this article to maintain a constant output voltage and to deal with circulating currents amongst parallel-connected converters. The proposed digital supervisory controller also regulates the input and line currents to keep them sinusoidal according to the input supply voltage to maintain the high power factor of the system. In this paper, using the differential equations of a buck-boost converter, the duty cycle calculations are performed for both Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM), which are responsible for providing a unity power factor. A supervisory controller encompasses a feed-forward control algorithm for tuning model parameters for eliminating the harmonics from the line current. The proposed scheme helps calculate duty cycles which provides a unity power factor and minimizes the circulating currents. The proposed method was simulated in MATLAB/Simulink and their digital-hardware validation testing was also performed using C2000 MCU Launchpad. Full article