Search Results (108)

Bias Temperature Instability (BTI)-induced aging of transistors is a serious concern in modern electronic circuits, yet its effects on the operation of mixed-signal circuits have not been extensively studied. In this work, initially we analyze how BTI-induced aging degradation influences the analog front end of Flash analog-to-digital converters (ADCs). BTI-induced aging leads to substantial increments in the offset voltage of the ADC comparators, which in turn affect their trip point voltage, leading to the alteration of the ADC’s performance characteristics, such as gain, full-scale error and integral nonlinearity. Thus, erroneous responses are generated. Next, we propose a low-cost BTI-induced aging mitigation technique based on a circuit reconfiguration method which periodically alters the average voltage stress on the ADC comparators’ transistors. The proposed method limits the comparators’ offset voltage development, restricting the shift in their trip point voltage. Consequently, the impact of aging on the performance characteristics of the ADC is drastically reduced, and its reliability is improved. According to our simulations, after two years of operation, the gain error is reduced by 95.43%, the full-scale error is reduced by 63.31% and the integral nonlinearity is reduced by 63.00%, with respect to operation without applying the proposed aging mitigation technique. Full article

This paper introduces a compact analog configuration that concurrently realizes a mixed-mode biquadratic filter and a dual-mode quadrature oscillator (QO) by employing a single differential differencing gain amplifier (DDGA) and all-grounded passive components. The proposed design supports four fundamental operation modes—voltage-mode (VM), current-mode (CM), trans-impedance-mode (TIM), and trans-admittance-mode (TAM)—utilizing the same circuit topology without structural modifications. In filter operation, it offers low-pass, high-pass, band-pass, band-stop, and all-pass responses with orthogonal and electronic pole frequency and quality factor. In oscillator operation, it delivers simultaneous voltage and current quadrature outputs with independent tuning of oscillator frequency and condition. The grounded-component configuration simplifies layout and enhances its suitability for monolithic integration. Numerical simulations in a 0.18-μm CMOS process with ±0.9 V supply confirm theoretical predictions, demonstrating precise gain-phase characteristics, low total harmonic distortion (<7%), modest sensitivity to 5% component variations, and stable operation from −40 °C to 120 °C. These results, combined with the circuit’s low component count and integration suitability, suggest strong potential for future development in low-power IoT devices, adaptive communication front-ends, and integrated biomedical systems. Full article

This paper proposes a dual-mode CMOS analog front-end (AFE) circuit for short-wave infrared (SWIR) image sensors, which integrates a hybrid readout circuit (ROIC) and a 12-bit two-step single-slope analog-to-digital converter (TS-SS ADC). The ROIC dynamically switches between buffered-direct-injection (BDI) and direct-injection (DI) modes, thus balancing injection efficiency against power consumption. While the DI structure offers simplicity and low power, it suffers from unstable biasing and reduced injection efficiency under high background currents. Conversely, the BDI structure enhances injection efficiency and bias stability via an input buffer but incurs higher power consumption. To address this trade-off, a dual-mode injection architecture with mode-switching transistors is implemented. Mode selection is executed in-pixel via a low-leakage transmission gate and coordinated by the column timing controller, enabling low-current pixels to operate in low-noise BDI mode, whereas high-current pixels revert to the low-power DI mode. The TS-SS ADC employs a four-terminal comparator and dynamic reference voltage compensation to mitigate charge leakage and offset, which improves signal-to-noise ratio (SNR) and linearity. The prototype occupies 2.1 mm × 2.88 mm in a 0.18 µm CMOS process and serves a 64 × 64 array. The AFE achieves a dynamic range of 75.58 dB, noise of 249.42 μV, and 81.04 mW power consumption. Full article

The inherent non-ideal characteristics of circuit components and inter-channel mismatch errors induce nonlinear amplitude and phase distortions in time-interleaved pipelined analog-to-digital converters (TI-pipelined ADCs), significantly degrading system performance. Limited by prior modeling, conventional digital calibration methods only correct partial errors, while machine learning (ML) approaches achieve comprehensive calibration at a high computational cost. This work proposes an ensemble calibration framework that combines polynomial modeling and ML techniques. The ensemble calibration framework employs a two-stage correction: a learned Volterra front-end performs forward mapping to compensate static baseline nonlinear distortions, while a lightweight neural network back-end implements inverse mapping to correct dynamic nonlinear distortions and inter-channel mismatch errors adaptively. Experiments conducted on TI-pipelined ADCs show improvements in both the spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR). It is noteworthy that in two ADCs fabricated using 40 nm CMOS technology, the 12-bit, 3000 MS/s silicon-validated four-channel TI-pipelined ADC exhibits SFDR and SNDR improvements from 35.47 dB and 35.35 dB to 79.70 dB and 55.63 dB, respectively, while the 16-bit, 1000 MS/s silicon-validated four-channel TI-pipelined ADC demonstrates an enhancement from 38.62 dB and 40.21 dB to 80.90 dB and 62.43 dB, respectively. Furthermore, a comparison with related studies reveals that our method achieves comprehensive calibration performance for wide-band inputs while substantially reducing computational complexity, requiring only 4.4 K parameters and 8.57 M floating-point operations per second (FLOPs). Full article

Edge-computing applications demand ultra-low-power architectures for both feature extraction and classification tasks. In this manuscript, a Keyword Spotting (KWS) system tailored for energy-constrained portable environments is proposed. A 16-channel analog filter bank is employed for audio feature extraction, followed by a digital Gated Recurrent Unit (GRU) classifier. The filter bank is behaviorally modeled, making use of second-order band-pass transfer functions, simulating the analog front-end (AFE) processing. To enable efficient deployment, the GRU classifier is trained using a Learned Step Size (LSQ) and Look-Up Table (LUT)-aware quantization method. The resulting quantized model, with 4-bit weights and 8-bit activation functions (W4A8), achieves 91.35% accuracy across 12 classes, including 10 keywords from the Google Speech Command Dataset v2 (GSCDv2), with less than 1% degradation compared to its full-precision counterpart. The model is estimated to require only 34.8 kB of memory and 62,400 multiply–accumulate (MAC) operations per inference in real-time settings. Furthermore, the robustness of the AFE against noise and analog impairments is evaluated by injecting Gaussian noise and perturbing the filter parameters (center frequency and quality factor) in the test data, respectively. The obtained results confirm a strong classification performance even under degraded circuit-level conditions, supporting the suitability of the proposed system for ultra-low-power, noise-resilient edge applications. Full article

Distortions of electrocardiograms (ECGs) caused by mandatory high-pass and low-pass analog RC filters in ECG devices are always present. The fidelity of the ECG waveform requires limiting the RC cutoff frequencies of the diagnostic (0.05–150 Hz) and monitoring systems (0.5–40 Hz). However, the use of fixed frequency bands is a compromise between enhanced noise immunity and ECG distortions. This study aims to propose active inverse high-pass and low-pass filters which are able to compensate for distortions in digital recordings of RC-filtered ECGs, thereby overcoming the limitations imposed by analog filtering. A new straightforward design of an inverse high-pass filter (IHPF) uses an integrator as the forward-path gain block, with a feedback loop containing an active digital filter equivalent to the analog RC high-pass filter. In contrast, the inverse low-pass filter (ILPF) employs a constant-gain block in the forward path to ensure stability and prevent phase delay, while its feedback path features an active digital counterpart of the RC low-pass filter. Second-order inverse filters are created by cascading two first-order stages. The proposed filters were validated according to essential performance requirements for electrocardiographs. The low-frequency (impulse) responses of IHPFs with cutoff frequencies of 0.05–5 Hz exhibit no overshoot and undershoot by magnitudes of 0.1–25 µV, well within the ±100 µV compliance limit defined for a test rectangular pulse (3 mV, 100 ms). The high-frequency responses of ILPFs with cutoff frequencies of 10–150 Hz present a relative amplitude drop of only 0.2–2.5%, far below the 10% limit for peak amplitude reduction of a triangular pulse (1.5 mV) with 20 ms vs. 200 ms widths. For any of the eight ECG leads (I, II, and V1–V6) available in the standard signal (ANE20000), the IHPF (0.05–5 Hz) presents ST-segment deviations <5 μV (within the ±25 μV limit) and R- and S-peak deviations <±3.5% (within the ±5% limit). The ILPF (10–150 Hz) preserves R- and S-peak amplitudes with deviations less than −1%. Diagnostic-level recovery of ECG waveforms distorted by first- and second-order analog RC filters in ECG devices is possible with the innovative and comprehensive inverse filter design presented in this study. This approach offers a significant advancement in ECG signal processing, effectively restoring essential waveform components even after aggressive, noise-robust analog filtering in ECG acquisition circuits. Although validated for ECG signals, the proposed inverse filters are also applicable to other biosignal front-end circuits employing RC coupling. Full article

Precision timing is a key requirement for emerging 4D particle tracking, Positron Emission Tomography (PET), beam and fusion plasma diagnostics, and other systems. Time-to-Digital Converters (TDCs) are commonly used to provide digital estimates of the relative timing between events, but the jitter performance of a TDC can be no better than the performance of the circuits that acquire the pulses and deliver them to the TDC. Several clock receiver and distribution circuits were evaluated, and a differential amplifier with resistive loads driving a pseudo-differential clock distribution network, developed using design guidelines for radiation tolerance and cryogenic compatibility, was fabricated as part of three prototypes: an analog front-end testbed chip for high-precision timing pixel readout, a dedicated TDC evaluation chip, and a Low-Gain Avalanche Detector (LGAD) readout circuit. Based on TDC measurements of the prototypes, we infer that the jitter added by the clock receiver and distribution circuits is less than 2.25 ps-rms. This performance meets the requirements of many future precision timing systems. The clock receiver and on-chip pseudo-differential driver were fabricated in commercial 28-nm CMOS technology and occupy 2288 µm². Full article

In-cell touch and display integrated panels, along with their integrated readout systems, are widely adopted in mobile devices for their cost-effectiveness and compact design. This paper proposes an analog Gaussian-shaped filter and a current mode compensation technique for dot-matrix Touch Screen Panel (TSP) readout systems. Specifically, this article presents a noise management strategy for both intrinsic and external noise, offering simulation guidelines for determining intrinsic circuit noise levels in relation to scan time and enhancing external noise immunity through the Gaussian-shaped filter response. The system achieved an intrinsic SNR of 66 dB with a 200 kHz TSP driving frequency and a 160 μs scan time, while the 4-bit quantized Gaussian coefficients filter provided 33 dB noise suppression for out-of-band noise. The compensation error in the dot-matrix capacitance compensation was measured at 1.24 pF, which corresponds to a 0.078% deviation. The simulated power consumption of the proposed readout system is 24 mW, with a layout area of 1.017 mm² for the 10-channel readout front-end. Full article

An innovative analog frontend for big data collection and intelligent compression as part of an instantaneous failure prediction platform is presented. Failure prediction in power management systems is crucial for increasing uptime and preventing massive failure. Accurate failure prediction, with real-time decision-making, requires data collection from many wide-bandwidth signals within a system, as low-bandwidth information such as DC output voltage is of limited value for decision-making and failure prediction. Analog compression, data profiling, and anomaly detection methods enabled by the unique analog frontend are presented. The system significantly reduces the demand for high computational power, fast communication, and large storage space required for the task. A real-time compression ratio exceeding 100:1 was achieved by the experimental analog frontend, digitizing the analog signal at a rate of 135 MS/s with a 10-bit resolution. The motivation, existing solutions, performance metrics, and advantages of the analog frontend are demonstrated, along with the details of the circuit operation principle. The process of data collection, its intelligent processing using the analog frontend, and anomaly detection are simulated to validate the theoretical hypotheses. For experimental validation, a laboratory setup that includes a dedicated analog frontend prototype and step-down DC-DC converter was built and evaluated to demonstrate the robust performance in sampling and monitoring wide-bandwidth signals and smart data processing using analog frontend for quick decision-making. Full article

Efficient filtering in biosignals acquisition is challenging. The resistance of the sources exhibits inter- and intra-subject variability or is unknown; thus, using passive filters before the first amplification stage is problematic. Conversely, filtering after amplification does not effectively eliminate the amplified electrical noise, main’s interference, and the artifacts. In this context, the design and utilization of filters in the analog front end of biosensors, in conjunction with the first amplification stage, is not common but offers substantial advantages. In this study, the design of a novel Multi-feedback Differential Filter Instrumentation Amplifier (MFDFIA) is proposed. The design and the equations governing the gain and bandwidth characteristics of the MFDFIA are presented, and relevant topologies are explored. Even though MFDFIA has two op-amps in its first stage, due to its symmetric topology, the analysis can be conducted separately for the differential- and common-mode input signal with a simplified one op-amp equivalent circuit. Notably, MFDFIA’s CMRR is equal and depends only on the CMRR of the second stage. An exemplary simulation for EEG signal acquisition is provided, with a flat band of 1db between 0.7 Hz and 25.4 Hz, a gain of 34.1 db, and an input noise of 70.66 nVrms in the range of 0.1–10 Hz. Full article

This paper presents a 35 nV/√Hz analog front-end (AFE) circuitdesigned in the UMC 40 nm CMOS technology for the acquisition of biopotential signal. The proposed AFE consists of a capacitive-coupled instrumentation amplifier (CCIA) and a combination of a programmable gain amplifier (PGA) and a low-pass filter (LPF). The CCIA includes a DC servo loop (DSL) to eliminate electrode DC offset (EDO) and a ripple rejection loop (RRL) with self-zeroing technology to suppress high-frequency ripples caused by the chopper. The PGA-LPF is realized using switched-capacitor circuits, enabling adjustable gain and bandwidth. Implemented in theUMC 40 nm CMOS process, the AFE achieves an input impedance of 368 MΩ at 50 Hz, a common-mode rejection ratio (CMRR) of 111 dB, an equivalent input noise of 1.04 μVrms over the 0.5–1 kHz range, and a maximum elimination of 50 mV electrode DC offset voltage. It occupies an area of only 0.39 × 0.47 mm² on the chip, with a power consumption of 8.96 μW. Full article

A battery-operated biomedical wearable device gradually assists in clinical tasks to monitor patients’ health states regarding early diagnosis and detection. This paper presents the development of a self-powered portable electronic module by integrating an onboard energy-harvesting facility for electrocardiogram (ECG) signal processing and personalized health monitoring. The developed electronic module provides a customizable approach to power the device using a lithium-ion battery, a series of silicon photodiode arrays, and a solar panel. The new architecture and techniques offered by the developed method include an analog front-end unit, a signal processing unit, and a battery management unit for the acquiring and processing of real-time ECG signals. The dynamic multi-level wavelet packet decomposition framework has been used and applied to an ECG signal to extract the desired features by removing overlapped and repeated samples from an ECG signal. Further, a random forest with deep decision tree (RFDDT) architecture has been designed for offline ECG signal classification, and experimental results provide the highest accuracy of 99.72%. One assesses the custom-developed sensor by comparing its data with those of conventional biosensors. The onboard energy-harvesting and battery management circuits are designed with a BQ25505 microprocessor with the support of silicon photodiodes and solar cells which detect the ambient light variations and provide a maximum of 4.2 V supply to enable the continuous operation of an entire module. The measurements conducted on each unit of the proposed method demonstrate that the proposed signal-processing method significantly reduces the overlapping samples from the raw ECG data and the timing requirement criteria for personalized and wearable health monitoring. Also, it improves temporal requirements for ECG data processing while achieving excellent classification performance at a low computing cost. Full article

Circuit noise is a critical factor that affects the performances of an MEMS gyroscope. Therefore, it is essential to analyze and suppress the noises in the key analog circuits, which are the main noise sources. This study presents an optimized front-end readout circuit and noise suppression methods. First, the noise analysis of the front-end readout circuit is carried out with theoretical derivation to clarify the main noise contributors. To suppress the output noise, an improved readout circuit based on the T-resistor networks is proposed, and the corresponding noise equation is derived in detail. In addition, the noise analysis of the critical circuits of the detection and control system, such as the inverting amplifiers, the first-order low-pass filters, and the first-order high-pass filters, is carried out, and the noise suppression strategy with the optimization of the resistances and is proposed. Taking the inverting amplifier as an example, the theoretical derivation is verified by measuring and comparing the output noises of different resistance schemes. In addition, the output noises of the gyroscope before and after circuit optimization are measured. Experimental results demonstrate that the output noise with the circuit optimization is reduced from 60 μV/Hz^1/2 to 30 μV/Hz^1/2 and the bias instability is reduced from 3.8 deg/h to 1.38 deg/h. In addition, the ARW is significantly improved from 0.035 deg/h^1/2 to 0.018 deg/h^1/2, which indicates that the proposed noise analysis and suppression methods are effective and feasible. Full article

Carbon nanotube field-effect transistors (CNT-FETs) have shown great promise in infrared image detection due to their high mobility, low cost, and compatibility with silicon-based technologies. This paper presents the design and simulation of a column-level analog front-end (AFE) circuit tailored for carbon-based short-wave infrared (SWIR) photodetectors. The AFE integrates a Capacitor Trans-impedance Amplifier (CTIA) for current-to-voltage conversion, coupled with Correlated Double Sampling (CDS) for noise reduction and operational amplifier offset suppression. A 10-bit/125 kHz Successive Approximation analog-to-digital converter (SAR ADC) completes the signal processing chain, achieving rail-to-rail input/output with minimized component count. Fabricated using 0.18 μm CMOS technology, the AFE demonstrates a high signal-to-noise ratio (SNR) of 59.27 dB and an Effective Number of Bits (ENOB) of 9.35, with a detectable current range from 500 pA to 100.5 nA and a total power consumption of 7.5 mW. These results confirm the suitability of the proposed AFE for high-precision, low-power SWIR detection systems, with potential applications in medical imaging, night vision, and autonomous driving systems. Full article

This paper introduces a fully differential asynchronous successive approximation register analog-to-digital converter (SAR ADC) designed for biomedical signal processing. By extending the tracking time and utilizing fully differential inputs in the analog front-end circuit, the signal-to-noise ratio is enhanced in the system. Using an asynchronous clock can reduce power consumption across a wider range of sampling frequencies. In comparison to conventional architecture in high-speed SAR ADC, using an internal clock generator can operate at lower frequencies. A fully differential input can eliminate the DC offset of the analog front-end circuit and reduce the adverse effects of process variation, voltage variation, and temperature variation. The chip is implemented by TSMC 0.18 $\mathsf{\mu }$m complementary metal-oxide-semiconductor (CMOS) technology, and the chip area is 0.680 mm² (including ESD I/O PAD). At a 1.2 V supply, the maximum sampling rate is 10 Kilo Samples per second (KSps). The implemented ADC has an 11-bit resolution, while the input voltage range is 300∼900 mV. The total power consumption is 1.7 $\mathsf{\mu }$W, with the core power consumption at 932 nW. Full article