Analog Gaussian-Shaped Filter Design and Current Mode Compensation for Dot-Matrix TSP Readout Systems

Abstract

In-cell touch and display integrated panels, along with their integrated readout systems, are widely adopted in mobile devices for their cost-effectiveness and compact design. This paper proposes an analog Gaussian-shaped filter and a current mode compensation technique for dot-matrix Touch Screen Panel (TSP) readout systems. Specifically, this article presents a noise management strategy for both intrinsic and external noise, offering simulation guidelines for determining intrinsic circuit noise levels in relation to scan time and enhancing external noise immunity through the Gaussian-shaped filter response. The system achieved an intrinsic SNR of 66 dB with a 200 kHz TSP driving frequency and a 160 μs scan time, while the 4-bit quantized Gaussian coefficients filter provided 33 dB noise suppression for out-of-band noise. The compensation error in the dot-matrix capacitance compensation was measured at 1.24 pF, which corresponds to a 0.078% deviation. The simulated power consumption of the proposed readout system is 24 mW, with a layout area of 1.017 mm² for the 10-channel readout front-end.

1. Introduction

With the rapid advancements in user interaction systems and display technologies, integrated touch and display circuits, referred to as Touch and Display Driver ICs (TDDIs) [1,2,3], have emerged as a highly popular solution. TDDIs provide both cost and area efficiency by integrating the touch panel and display into an in-cell structure, eliminating the need for separate touch modules and ICs.

Figure 1a illustrates the stack-up of an in-cell LCD display panel, where the TSP electrodes are integrated onto the color filter glass. These electrodes, made of transparent indium tin oxide (ITO), maintain optical transmittance while enabling capacitive sensing. They form either fringing field capacitance or self-capacitance (C_S) [4,5,6,7] with the LCD’s common electrode (V_COM) layer, which stabilizes the voltage across the liquid crystal (LC) layer during operation. When a finger touches the cover glass, an additional finger capacitance (C_F) is introduced, altering the total capacitance and enabling touch detection. The color filter layer, positioned beneath the TSP electrodes, selectively transmits RGB subpixel data for accurate color representation. Below the LC layer, the thin-film transistor (TFT) array, fabricated on the TFT glass, actively controls pixel switching by modulating the electric field across the liquid crystals. By embedding TSP electrodes within the display stack, this design reduces manufacturing complexity and cost while enabling thinner and lighter panels. Figure 1b shows the illustration of a dot-matrix type in-cell TSP panel, highlighting a disadvantage related to the uniformity of the capacitance (Cs). The dot-matrix channels, denoted as CH_Dot [N:1], consist of N individual sensing channels, each connected to a dot-matrix capacitance readout IC, where the capacitance values are measured and processed. Since the trace of each dot-matrix TSP electrode is routed within the panel, the width (W_U) of the dot-matrix electrodes in the upper area is wider than that (W_L) in the lower area. Consequently, the capacitance varies depending on the channel location. Additionally, the V_COM layer, serving as the reference potential, is connected through a unity-gain feedback buffer to stabilize the voltage level before being distributed via contact pins (V_COM1–V_COM4) at the four corners of the rectangular layer in mobile devices. This configuration introduces a loading effect caused by the network of series and parallel resistance (R_S) connections within the V_COM layer. As a result, the parasitic resistances are particularly pronounced at the center of the layer, leading to variations in the time constant and, consequently, nonuniformity in the measured C_S. These challenges in accurately measuring the Cs are exacerbated by the small variation introduced when a finger contacts the TSP electrode. The capacitance change caused by finger contact (C_F) is only 3–5% of the baseline Cs. This minimal variation is often masked by the significantly larger and nonuniform baseline Cs, emphasizing the necessity of a precise Cs compensation circuit.

Another major concern of the TSP readout system is its noise immunity to external disturbances, which is highly influenced by the choice of the TSP driving frequency. Most external noise sources, such as charger-induced noise, fluorescent lamp ramp noise, and electromagnetic interference (EMI) from surrounding components within the compact form factor of mobile devices, typically fall within the range of several tens to hundreds of kHz [8,9,10,11]. Consequently, a higher TSP driving frequency is generally required to effectively mitigate these noise effects. However, this frequency is constrained by the time constant determined by the TSP’s Cs and the TSP electrode’s series resistance, significantly limiting the available frequency range.

Recently, the introduction of Variable Refresh Rate (VRR) technology [12] in mobile display systems has added another layer of complexity. VRR dynamically adjusts the display update signals to optimize power consumption and visual performance, but it creates a non-static display noise environment, further complicating the design of touch sensing circuits. While frequency hopping based on three selective TSP driving frequencies was proposed [13], the uniformity of the capacitance (Cs) across the TSP channels varied depending on the selection of hopping frequency, making baseline calibration more challenging and necessitating advanced filtering and noise cancellation algorithms within the TDDI controller.

In this paper, we propose a reconfigurable selectivity Gaussian filter and a highly accurate Cs compensation circuit to effectively address the two aforementioned challenges. First, the 4-bit coefficient Gaussian filter is implemented using a discrete-time (DT) analog circuit within the analog front-end (AFE) of the TSP readout system. This approach eliminates the need for a complex and area-intensive multiplier logic typically required in digital implementations of Gaussian filters [13]. Second, the C_S compensation is achieved through a charge-boosting scheme with an Operational Transconductance Amplifier (OTA) and reference integrated capacitor. The paper is organized as follows: Section 2 presents the proposed system architecture with detailed circuit implementations. Simulation results are provided in Section 3. A comparison of the proposed design with existing TSP readout systems is discussed and the conclusion is presented in Section 4.

2. Proposed TSP Readout System

2.1. Whole System Architecture

The top of Figure 2 illustrates the proposed overall system architecture of the TSP sensing front-end. The sensing front-end is divided into two sections: TSP AFE Right (R), which handles dot-matrix TSP channels (CH_Dot [20:1]), and TSP AFE Left (L) for CH_Dot [40:21]. This division is essential due to the integration with the display driver IC (DDI) as a TDDI, centrally located within the system. Each front-end section comprises key functional blocks, including a 2-to-1 multiplexer, a second-generation current conveyor (CCII), a current-to-voltage converter (C2V), a sample-and-hold circuit (S/H), and an ADC. Additionally, a dot-matrix Cs-compensator is integrated and its output cells generate compensation charges of Q_CP,O [9:0] to each CCII input to effectively nullify the baseline Cs, ensuring accurate signal processing and minimizing capacitance nonuniformity.

First, the CCII converts the capacitance C_S into current and amplifies it. The CCII’s inherent low-pass characteristics suppress high-frequency coupled noise. Simultaneously, the baseline Cs is nullified before current conversion, ensuring that only the capacitive variations from finger touch (C_F) are transferred to the C2V for further processing. The subsequent C2V stage consists of an operational amplifier (op-amp) with a feedback integral capacitor (C_INT) and resistor (R_INT). The parallel combination of C_INT and R_INT converts the current from the CCII into a proportional voltage while introducing a high-pass pole at a low frequency. Consequently, the poles at the CCII input and the C2V output collectively form a band-pass filter centered at the TSP driving frequency (f_TSP). The S/H functions as a voltage sampling circuit for subsequent analog-to-digital (A/D) conversion while incorporating a reconfigurable Gaussian filtering effect. Operating as a discrete-time (DT) circuit, the S/H can implement Gaussian coefficients using a discrete-level sampling capacitor array, synchronized with a clock operating at twice the frequency of f_TSP.

The bottom of Figure 2 shows the frequency translation of the capacitance signal across each AFE stage, emphasizing the frequency range of the TSP signals and the dominant noise sources at each front-end stage. First, the capacitance-induced signal is up-modulated to f_TSP to shift its frequency spectrum away from low-frequency noise sources, such as DC offsets from the charger and hum noise from power lines (50–60 Hz). Then, band-pass filtering within the AFE removes out-of-band noise, while the dot-matrix C_S compensator isolates the capacitive change by finger (C_F), ensuring accurate touch detection. After discrete-time Gaussian filtering in the sample-and-hold (S/H) and A/D conversion stages, demodulation is performed in the digital domain through +1/−1 coefficient multiplication. Since the +1/−1 multiplication is synchronized to twice the frequency of f_TSP, intrinsic noise at the baseband, such as DC offset and 1/f noise, is up-modulated to f_TSP during this process. The resulting noise components are then removed through decimation filtering, ensuring that only the desired baseband signal components (C_S,Digital) are retained for further processing.

2.2. Sensing Front-End

Figure 3 illustrates the sensing front-end, consisting of a CCII and a C2V converter along with its timing diagram. The CCII, directly connected to the TSP electrode via SW_CHG, has its X node (V_X) referenced to the Y node voltage (V_Y). When V_Y is driven by an AC-modulated V_DRV, V_X achieves the same voltage level and drives C_S[n] with virtual V_DRV. The V_DRV signal is generated by a unity-gain buffer and a resistor string in the reference generator, where V_H and V_L are alternately selected by V_DRV,CTR to produce the AC-modulated V_DRV. Another key feature of the CCII is its ability to copy the input current (I_X) to the Z node (I_Z) with a multiplication factor of K. Since C_S[n] is driven by the virtual V_DRV, a proportional charge of V_DRV × C_S[n] is generated and transferred to the X node as a current. However, due to the large C_S[n] of the TSP electrode, the I_Z (=K × I_X) can saturate the subsequent front-end stage. To mitigate this, only the capacitive variation from C_S[n], approximately corresponding to the C_F of a finger, should be transferred to the next sensing stage. For this purpose, a dot-matrix C_S-compensator is designed, with its output connected to C_S[n]. Instead of fully transferring the charge of V_DRV × C_S[n], the static portion of C_S[n] is eliminated by Q_CP,O. Since the charge of V_DRV × C_S[n] is modulated by f_TSP, the proposed compensator alternately generates sinking (Q_SK,O) and sourcing (Q_SC,O) charges for effective compensation. Once the sampling switch (SW_CHG) is closed, only the differential charge of ∆Q (=V_DRV × C_S[n] − Q_CP,O) is transferred. The charge of Q_CP,REF is generated by a metal–insulator–metal (MIM) reference capacitor (C_REF) driven by virtual V_DRV, while a current amplifier at the output boosts that current to Q_CP,O through fine and coarse tuning. The tuning ratio (M) can be reconfigured depending on the measurable channel-dependent size of C_S[n].

To mitigate external noises, such as V_COM noise, the sensing front-end incorporates a bandpass filter (BPF). The charge conversion from C_S[n] to I_X at the CCII input generates a transfer function’s zero at DC. Conversely, the large parasitic capacitance combined with the input impedance of the CCII forms a high-frequency low-pass pole. The C2V converts this high-pass-filtered I_Z to a proportional voltage. Simultaneously, R_INT in parallel with C_INT introduces a low-frequency high-pass pole, collectively shaping the bandpass filter response. The passband gain (A_V) from V_DRV to V_C2V can be described by

$${\mathrm{A}}_{\mathrm{V}}={\displaystyle \frac{\mathrm{K}({\mathrm{C}}_{\mathrm{S}}\left[\mathrm{n}\right]-{\mathrm{M}\times \mathrm{C}}_{\mathrm{R}\mathrm{E}\mathrm{F}})}{{\mathrm{C}}_{\mathrm{I}\mathrm{N}\mathrm{T}}}}$$

(1)

where K is the current gain of CCII from the X node to the Z node, and M denotes the charge-boosting ratio of the dot-matrix C_S-compensator, which can be reconfigured based on the size of C_S[n]. The operation of C2V is synchronized with the switches SW_RST and SW_CHG as described in the timing diagram of Figure 3. When SW_CHG is closed, the proportional charge is integrated on C_INT, while SW_RST resets C_INT to prevent saturation of the front-end before the arrival of the next set of samples.

2.3. Dot-Matrix C_S-Compensator

There have been numerous studies on self-capacitance (C_S) sensing front-ends, with various compensation techniques proposed. The compensation using chip-integrated capacitors has been identified as one of the most accurate topologies, as demonstrated in [14]. However, this approach requires an increasing number and size of integrated capacitors proportional to the number of sensing channels, which significantly increases the chip area and makes it unsuitable for cost-sensitive applications. To address this, current-mode compensation schemes employing static sinking or sourcing currents have been utilized [15,16], offering an area-efficient solution for realizing the compensation charge. However, this method is highly susceptible to process and temperature variations. Temperature sensitivity presents a critical challenge in smartphone applications, where operational conditions are heavily affected by environmental factors, such as ambient weather variations.

The proposed C_S-sensing circuit achieves a balance between accuracy and area efficiency by utilizing both integrated capacitors and a current-mode scheme. As shown in Figure 4, the compensator incorporates three main blocks: an integral reference capacitor (C_REF), adjustable from 13 pF to 20 pF in 1 pF increments, connected to the negative input of the OTA (-)IN, an OTA configured as a unity-gain amplifier, which transfers charges from C_REF (Q_SC, Q_SK) to its output, and 10 current output cells, which amplify Q_SC and Q_SK to compensate the channel-dependent C_S. When the (+) input of the OTA, (+)IN is driven by the AC-modulated V_DRV at a frequency of f_TSP, C_REF is alternately charged to V_H or V_L, delivering equivalent charges of Q_SC and Q_SK to the OTA’s output. The absolute variation in these charges is equal to C_REF $\times$ (V_H − V_L), which modulates the gate voltages (V_GP and V_GN) of the PMOS/NMOS transistors (M_P2, M_N2) in the current sources. Since the current copying output cell shares the V_GN and V_GP with the output of the OTA, it generates and amplifies C_REF $\times$ (V_H − V_L) at its output (V_CS,O [9:0]) by ratio M to compensate for the baseline C_S. This cell includes both a 4b fine compensation unit (1/16Q_SC to 1/2Q_SC) with 1/16Q_SC steps and a 3b coarse compensation unit (Q_SC to 4Q_SC) with Q_SC steps controlled by GCTR<6:0>. For instance, with a C_REF of 20 pF, the compensation range for C_S spans from 1.25 pF to 160 pF with a 7b resolution.

Although the OTA has a single dominant pole (w_don) at its output formed by C_REF and PMOS/NMOS cascode resistors in parallel (R_op//R_on), its stability is degraded by parasitic capacitance from the 10 output cells connected to V_GN and V_GP in parallel. Since the size of each output current cell is approximately eight times that of OTA, the gate capacitance of each cell (C_G,OUT) is also eight times that of M_N2‘s gate capacitance (C_G,MN2). Consequently, the total parasitic capacitance at V_GN (C_P) can increase by approximately 80 times compared to a conventional OTA of the same device size without output current cells. The second pole is given by the product of the inverse of the transconductance of M_N1 (g_MN1) and C_P, as described in Figure 4. Thus, the maximum unity gain frequency of the C_S compensator is limited to g_MN1/C_P, degrading the response time of the compensator. Another key factor in degrading the compensation speed is the slew rate limitation of the OTA. With the voltage swing of V_DRV approaching 1 V (=V_H − V_L), a significant portion of the compensation time is dominated by the slewing condition. Thus, depending on the channel location and the resistance of its routing trace, the slew rate can be improved and adjusted through a 2b controlled bias current (I_bias) of the OTA’s input pairs (G_m,IN).

2.4. Proposed Second-Generation Current Conveyor (CCII)

The CCII at the sensing front-end serves two purposes in the readout system. First, it converts the capacitive variation at the TSP into proportional current. Second, it utilizes the parasitic capacitance of the TSP (C_S[n]) to create a high-frequency low-pass pole, mitigating external noises. At the same time, the large C_S[n], of the order of 100–200 pF should not limit the system’s bandwidth, aided by the small input resistance (R_IN) of the CCII. Previously, various methods have been proposed to implement the CCII [17,18,19,20]. However, in this design, a negative-feedback closed-loop configuration is employed to effectively reduce the R_IN of the CCII by the loop gain.

As shown in Figure 5, the OTA consists of two gain stages, with an additional resistor R_F in the first stage to further enhance the overall gain. Since R_F is significantly smaller compared to the channel resistances of the PMOS input pairs (M_P1, M_P2) and NMOS current source pairs (M_N1, M_N2), the gain of the first stage (A_V1) is determined by the product of the input transconductance of M_P1 and M_P2 (G_m,CC) and R_F [7]. The second gain stage (A_V2) is determined by the transconductance G_m,CC of M_N3 and the parallel combination of the PMOS and NMOS cascode resistances (R_op,CCII//R_on,CCII). When unity-gain feedback is applied, the effective cascode resistance is reduced by the product of A_V1 and A_V2. With R_F tunable between 20 kΩ to 37.5 kΩ using 3b control and G_m,CS designed to be 150 μS, the reduction factor in R_IN by the additional gain stage ranges from 3 to 5.625, depending on the actual panel loading. The current amplification ratio (from I_X to I_Z) is adjusted from 1/8 to 15/8 to prevent saturation of the subsequent C2V and Gaussian-shaped S/H circuit.

2.5. Sensing Back-End

Although a filtering effect is implemented in the sensing front-end using CCII and C2V, which performs bandpass filtering to mitigate external noise, the noise environment can be varied in modern commercial mobile devices. In particular, the VRR driving in the DDI necessitates a more systematic adaptive filtering approach in the TSP readout system. The sensing back-end comprises a Gaussian-shaped sample and hold (S/H) circuit, and a successive approximation register (SAR) ADC. The Gaussian-shaped S/H circuit features both a discrete-time (DT) finite impulse response filter (FIR) effect and voltage sampler for A–D conversion by successively sampling the output of C2V onto the reconfigurable sampling capacitor C_GS, as shown in Figure 6. The C_GS is composed of 15 unit capacitors C_GS,u [14:0] to enhance matching accuracy, with their values continuously increasing and decreasing in a Gaussian-shaped manner synchronized to twice the frequency of f_TSP. The operating timing diagram and the schematic of the Class AB op-amp are also presented in Figure 6. First, the control signal V_S and V_S,Pre are applied to input and feedback switches during the sampling phase. In this phase, the output (V_S/H,O) is maintained at half the supply voltage (=V_CM) due to the unity-gain feedback configuration, while V_C2V is sampled on the left-side plate of C_GS. After disabling V_S,Pre and then V_S to eliminate input-dependent charge injection, the sampled charge on C_GS is transferred to C_F, generating an output of V_C2V × (C_GS/C_F). Since C_GS varies in each S/H phase, the generated output level V_S/H,O is adjusted according to the Gaussian coefficients gains G_GCTR [14:0] applied to C_GS, effectively implementing a DT FIR filter of the digital signal processor (DSP) in the analog signal. Therefore, when G_GCTR [14:0] reaches its maximum value 0 × 7FFF, the S/H gain is maximized with all C_GS,U enabled, and subsequently decreases to its minimum within the scan-time. The scan time is determined by the product of twice the inverse of f_TSP and the number of Gaussian filter coefficients (N_Gauss).

The primary goal of implementing Gaussian filtering in the analog domain is to achieve an area- and power-efficient solution compared to its digital counterpart. However, as the number of Gaussian coefficient levels increases, the design complexity in the analog domain also rises. Therefore, a careful trade-off must be made to balance efficiency and complexity. Figure 7a illustrates the frequency response based on the Gaussian coefficient quantization levels, comparing the results from 4-bit (4b) and 7-bit (7b) discrete Gaussian levels with a continuous-time (CT) Gaussian waveform. In 4b quantization, the filter coefficients range from −7 to 7, while in 7b quantization, the range extends from −63 to 63, offering improved approximation of the continuous-time Gaussian waveform at the cost of increased implementation complexity. Here, the TSP driving frequency f_TSP is set to 200 kHz, with the number of filter taps set to 64, resulting in 160 μs scan-time. The bandwidth within the main lobe frequency is measured to 40 kHz, which remains consistent across all three cases. However, the external noise immunity at 1.4 times the main frequency (=200 kHz), or the sideband ripple in the 4b quantization, is degraded by 16.4 dB compared to the ideal CT Gaussian waveform. This issue can be mitigated using the previously mentioned analog BPF, which is implemented with a CCII and C2V, making the 4-bit design a practical trade-off between performance and complexity. Figure 7b also illustrates the bandwidth modification as a function of the number of filter taps. While the bandwidth can be adjusted based on external noise conditions, this comes at the cost of increased scan time, which must be considered depending on the operating environment.

3. Simulation Results

To define the sensitivity requirements for the sensing front-end, the intrinsic circuit noise and external noise are analyzed. Although this study primarily presents simulation results rather than measurement data, the proposed simulation methodology can be utilized to define system specifications and provide practical design guidelines. Moreover, this approach is not limited to the proposed system but can be adapted to other sensing front-end structures, enhancing its applicability.

Figure 8 shows the overall AFE architecture, incorporating both intrinsic and external noise power within the system. The output-referred noise voltages for the C_S-compensator, reference generator, op-amp in C2V, and Gaussian-shaped S/H circuits are represented as $\overline{{V_{NO,CP}}^2}$, $\overline{{V_{NO,REF}}^2}$, $\overline{{V_{NO,opamp}}^2}$, and $\overline{{V_{NO,S/H}}^2}$ while the input-referred noise voltage of the CCII is $\overline{{V_{NIN,CCII}}^2}$ and the noise current of the feedback resistor in the C2V is $\overline{{I_{RINT}}^2}$. Additionally, the external noise from the capacitive coupling is denoted as $\overline{{V_{ND}}^2}$. Thus, the overall noise at the AFE output or S/H output is expressed as $\overline{{V_{NO}}^2}$, as also depicted in Figure 8. However, its amount cannot be quantified due to its dependence on the environmental noise condition. Thus, we define two evaluation metrics: one to qualify the SNR over the intrinsic circuit noise, and the other to assess noise immunity against the external noise by measuring the system’s responsiveness to noise frequencies ranging from DC to a predefined high frequency. First, the intrinsic SNR can be described [21] in Equation (2)

$$\mathrm{S}\mathrm{N}\mathrm{R} (\mathrm{d}\mathrm{B})=20{\mathrm{l}\mathrm{o}\mathrm{g}}_{10}{\displaystyle \frac{\sqrt{{\mathrm{N}}_{\mathrm{F}\mathrm{i}\mathrm{l}\mathrm{t}\mathrm{e}\mathrm{r}}}\times {\mathrm{V}}_{S/H,\mathrm{O}\mathrm{M}\mathrm{a}\mathrm{x}}}{2\overline{V_{NO}}}}$$

(2)

where N_Filter is the number of filter taps, which is twice the number of TSP driving, and V_S/H,OMax and $\overline{V_{NO}}$ are the maximum output voltage level and the total output-referred noise observed at the Gaussian-shaped S/H circuit, respectively. Since the signal power from capacitive changes is proportional to N_Filter, and the noise power is proportional to the square root of N_Filter, the SNR becomes proportional to the square root of N_Filter, indicating that a higher SNR can be achieved with increased scan time. Moreover, the factor of 2 in the denominator of Equation (2) reflects the reduction in the total signal amplitude due to Gaussian shaping in the S/H circuit, compared to maintaining a constant V_S/H,OMax at the output. We target an intrinsic SNR exceeding 60 dB with a 1 pF capacitive variation from a finger (C_F), N_Filter = 64 Gaussian filter coefficients, and a 200 kHz TSP driving fre- quency. Figure 9 shows the simulated output (V_S/H,OMax) of the Gaussian S/H circuit. The output root mean square (RMS) integrated noise of the S/H circuit over the system bandwidth was also evaluated using the noise simulation function in Virtuoso. The V_S/H,OMax reaches up to 2.67 V at the center of the Gaussian-shaped output, achieving a signal voltage of 1.17 V for capacitive change (V_S/H,OMax-V_CM), while the simulated output RMS noise ($\overline{V_{NO,RMS}}$) is 2.31 mV, resulting in an intrinsic SNR of 54 dB in a single pulse. With N_Filter of 64 and a 200 kHz TSP driving frequency, the SNR is further enhanced to 66 dB within a scan time of 160 μs. As the TSP frame rate is typically synchronized with the display in TDDI, the reduced scan time enhances system efficiency by maximizing the time allocated to display driving. For instance, with a 120 Hz display refresh rate (8.33 ms per frame), apart from the 160 µs scan time, the remaining 8.17 ms can be fully utilized for display driving, allowing the TSP to remain in idle mode, thereby improving the overall power efficiency.

Secondly, as shown in Figure 10, external noise immunity was simulated by sweeping the external noise ($\overline{{V_{ND}}^2}$ in Figure 8) from DC to 400 kHz in 1 kHz steps and injecting through C_S[n]. To verify the discrete-time Gaussian filter response, the ADC output was demodulated using discrete signals of [1, −1] after A–D conversion and then decimated to DC to obtain the raw value at each display noise frequency. Compared to the FFT results obtained directly from the 64-tap Gaussian filter coefficients, the simulated noise performance under the noise sweep exhibits a high level of consistency, achieving −33 dB noise rejection at 278 kHz. To evaluate the impact of process variation on the filter response, the metal–insulator–metal (MIM) capacitor in the chip is assumed to vary by ±15% variation (∆Var) of its nominal value. Consequently, C_GS,u in the Gaussian S/H circuit experiences the same variation. Figure 11 compares the Gaussian filter responses obtained from ideal 4-bit quantized filter coefficients and those affected by ±15% random variations in C_GS,u. In the worst case, where C_GS,u exhibits a ±15% random mismatch across all nine samples, the attenuation capability degrades by 6.2 dB. However, since C_GS,u is placed in close proximity within the same location, the impact of its random mismatch will be further mitigated in practice.

Figure 12 shows the simulated results of the C_S compensator’s compensation linearity, where the reference capacitor C_REF is set to 20 pF, and the current gain (M), corresponding to the compensation capacitance, increases from 1/16 (1.25 pF) to 8 (160 pF) across a 7-bit range. The maximum capacitive error occurs at the midband of the compensation range, reaching 1.24 pF, which corresponds to a 0.078% error in the total 160 pF compensation range. To verify the impact of process variation on the compensation accuracy, the mismatch between source (Q_SC) and sink (Q_SK) compensation charges was analyzed using Monte Carlo simulations in the virtuoso tool, with C_REF ideally fixed, as shown in Figure 13. In the simulation, 500 deviation samples were obtained to evaluate the statistical distribution of compensation charge variations, while the results of Q_SK in (b) were scaled by the mean value of Q_SC to facilitate a direct comparison of their absolute value differences. The width and length of NMOS (M_N2, M_N4) and PMOS (M_P2, M_P4) cascode current sources are specified in Figure 4, with dimensions scaled in micrometers. With the aid of large channel length (=1.8 μm), the standard deviation was measured as 0.25% for Q_SC and 0.24% for Q_SK, while the difference between Q_SC and Q_SK is 1.2%, demonstrating high compensation accuracy.

Figure 14 shows the layout of the sensing front-end designed for 20 dot-matrix sensor electrodes, comprising 10 front-end blocks and 5 SAR ADCs. The C_S compensator is positioned at the top of the layout, with the adjacent area allocated for general analog blocks, such as the LDO, BGR, and OSC, which will be shared by the display driver IC. The total front-end area is double the 1.017 mm² for 40 dot-matrix sensors, CH_Dot [40:1].

Table 1. Performance summary and comparison with the state of the art.

	This Work	[5]	[15]	[22]	[23]
Process	350 nm CMOS	1.1 V/3.3 V/8 V/20 V 45 nm	130 nm/350 nm CMOS	1.2 V/6 V/32 V 80 nm	130 nm/350 nm CMOS
Capacitance	Dot-matrix self-capacitance	Dot-matrix self-capacitance	Dot-matrix self-capacitance	Dot-matrix self-capacitance	2-layered self- and mutual capacitance
Electrode	40 dots	N/A	16	576 dots	37
Sensor	40	216	16	96	37
AFE Area	1.017 mm2 × 2	27.7 mm2	0.128 mm2	5 mm2	2.81 mm2
AFE Area/Sensor	0.05 mm2	0.12 mm2	0.08 mm2	0.05 mm2	0.086 mm2
Power	24 mW	166 mW	1.04 mW	16 mW	22.4 mW
Supply	3.3 V	1.1 V/3.3 V/5 V/6.6 V	3.3 V	1.2 V/6 V/32 V	3.3 V
Scan Rate	3.125 kHz	120 Hz	330 Hz	120 Hz	1.05 kHz for CS
Noise-removing scheme	Discrete-time Gaussian filter + BPF	Noise antenna reference	Moving average + pseudo-random spreading of orthogonal driving	Moving average scheme	Noise-monitoring scheme
SNR	66 dB/1 pF (simulation) (1)	45.8 dB/500 fF	47.2 dB	$51 \mathrm{dB}/7\mathsf{\Phi }$	36.1 dB for 340 pF CS

⁽¹⁾ Since this study is based on simulation results, a direct and fair comparison with measurement-based results is not feasible.

summarizes the front-end performance compared to previous TDDI circuit designs. Compared to previous works, the proposed IC operates with a single supply voltage of 3.3 V, allowing the PMIC to power the controller IC using a single voltage rail. This design enhances both implementation and area efficiency, as it requires only a single bypass capacitor on the 3.3 V supply pin, thereby minimizing the PCB footprint in compact smartphone designs. It also achieves a high scan rate of 3.125 kHz for 40 TSP electrode sensing, which is advantageous in TDDI designs, as TSP and DDI operate sequentially in a time-division manner. The 40 TSP electrodes correspond to a display size of 1.91 inches, assuming a channel pitch of 4.5 mm, making it suitable for wearable device panels. With the aid of a channel-dependent C_S-compensator featuring independent fine and coarse tuning, the system can accommodate various TSP shapes that exhibit location-dependent C_S variations.

Although a fair comparison with previous studies presenting measurement results is not feasible, the proposed design demonstrates superior area efficiency with 0.05 mm² AFE area per sensor electrode and enhanced noise immunity using an analog Gaussian filter in the DT S/H circuit.

4. Conclusions

This work presents an analog Gaussian-shaped filter and a current mode compensation technique for dot-matrix TSP readout systems, addressing critical challenges in noise immunity and area efficiency for in-cell touch and display integrated panels. The proposed system achieves an intrinsic SNR of 66 dB with a 200 kHz TSP driving frequency and a scan time of 160 μs. Additionally, the 4-bit quantized Gaussian filter provides −33 dB noise suppression at 278 kHz, effectively mitigating out-of-band noise.

The C_S compensator demonstrates high linearity, with a maximum capacitive error of 1.24 pF, corresponding to a 0.078% deviation across a 7-bit range. The system achieves a simulated power consumption of 24 mW and an area efficiency of 0.05 mm² per sensor electrode, demonstrating feasibility for mass production.

While the evaluation is based on simulation results, the proposed methodology establishes a practical framework for system specification and design optimization. Furthermore, the methodology is versatile and can be extended to other circuit designs. The combination of an analog Gaussian filter and current mode compensation offers a scalable, area-efficient, and noise-immune solution for modern TSP readout systems, making it well suited for integration into cost-sensitive mobile devices.