Search Results (83)

As the resolution and conversion speed of time-to-digital conversion (TDC) chips continue to improve, the bit error rate also increases, leading to a decrease in the linearity of TDC and seriously affecting measurement accuracy. This paper presents a high-linearity, low-power-consumption, and wide dynamic range TDC that was achieved based on the SMIC 180 nm BCD process. Compared with previous research methods, the proposed phase arbiter structure can eliminate sampling errors and improve the linearity of TDC. The preprocessing circuit can eliminate fixed errors caused by START and STOP signal transmission delays. Post-simulation results show that the TDC has high linearity, with ranges of DNL and INL being −0.98 LSB < DNL < 0.93 LSB and −0.88 LSB < INL < 0.95 LSB, respectively. The highest resolution is 156 ps, the maximum measurement time range is 1.2 μs, and the power consumption is 1.625 mW. The overall system architecture of TDC is very simple, and it can be applied to dToF LIDAR to measure photon flight time, capable of measuring a range of up to hundreds of meters, with an accuracy of 2.25 cm, high linearity, and without any post-processing or time calibration. Full article

The signal-processing architecture of passive surface acoustic wave (SAW) sensors presents significant implementation challenges due to its radar-like operational principle and the inherent complexity of discrete component-based hardware design. While System-in-Package (SiP) has demonstrated remarkable success in miniaturizing electronic systems for smartphones, automotive electronics, and IoT applications, its potential for revolutionizing SAW sensor interrogator design remains underexplored. This paper presents a novel architecture that synergistically combines time-domain ADC design with SiP-based miniaturization to achieve unprecedented simplification of SAW sensor readout systems. The proposed time-domain ADC incorporates an innovative delay chain calibration methodology that integrates physical unclonable function (PUF) principles during time-to-digital converter (TDC) characterization, enabling the simultaneous generation of unique system IDs. The experimental results demonstrate that the integrated security mechanism provides variable-length bit entropy for device authentication, and has a reliability of 97.56 and uniqueness of 49.43, with 53.28 uniformity, effectively addressing vulnerability concerns in distributed sensor networks. The proposed SiP is especially suitable for space-constrained IoT applications requiring robust physical-layer security. This work advances the state-of-the-art wireless sensor interfaces by demonstrating how time-domain signal processing and advanced packaging technologies can be co-optimized to address performance and security challenges in next-generation sensor systems. Full article

In application domains where severe environmental conditions are unavoidable, including high-energy physics and nuclear power plants, accurate and dependable time-to-digital converters (TDCs) are essential components. Single-event upsets (SEUs) associated with the configuration memory of field-programmable gate array (FPGA)-based implementations are becoming common sources of performance degradation even in terrestrial areas. Hence, the need to test and mitigate the effects of SEUs on FPGA-based TDCs is crucial to ensure that the design achieves reliable performance under critical conditions. The TMR SEM IP provides real-time fault injection, and dynamic SEU monitoring and correction in safety critical conditions without intervening with the functionality of the system, unlike traditional fault injection methods. This paper presents a scalable and fast fault emulation framework that tests the effects of SEUs on the configuration memory of a 5.7 ps-resolution TDC implemented on ZedBoard. The experimental results demonstrate that the standard deviation in mean bin width is 2.4964 ps for the golden TDC, but a 0.8% degradation in the deviation is observed when 3 million SEUs are injected, which corresponds to a 0.02 ps increment. Moreover, as the number of SEUs increases, the degradation in the RMS integral non-linearity (INL) of the TDC also increases, which shows 0.04 LSB (6.8%) and 0.05 LSB (8.8%) increments for 1 million and 3 million SEUs injected, respectively. The RMS differential non-linearity (DNL) of the faulty TDC with 3 million SEUs injected shows a 0.035 LSB (0.8%) increase compared to the golden TDC. Full article

Time-to-Digital Converters (TDCs) implemented on Field-Programmable Gate Arrays (FPGAs) have become increasingly prevalent across a wide range of scientific and engineering disciplines, such as high-energy physics experiments, autonomous driving, robotic navigation, and medical imaging, owing to their cost-effectiveness, high precision, and rapid development cycles. This article presents a 3-tap heterogeneous tapped delay-line (TDL) architecture for a FPGA-based TDC that can be employed for multi-channel time-of-flight measurement. The TDC desgin is based on the open-source jTDC, featuring single-cycle dead time and multi-channel expansion capabilities, with an original precision of 30 ps. Combined with jTDC’s dynamic caching mechanism using dual-page memory, this work employs a dual-cycle encoding and calibration. The proposed architecture has been implemented on a Xilinx Artix-7 FPGA. According to the experimental results, an optimal 3-tap heterogeneous TDL architecture achieves a resolution of 23.220 ps and a typical precision of 17.520 ps, whereas an optimal 4-tap heterogeneous TDL architecture demonstrates a resolution of 17.530 ps and a typical precision of 17.213 ps. A comparison with recently published state-of-the-art FPGA-based TDCs is provided at the end of the article. Full article

This research presents a novel approach to 28 $\mathrm{GHz}$ impulse radio ultra-wideband (IR-UWB) transmission using pulse position modulation (PPM) over an analog radio-over-fiber (ARoF) link, investigating the impact of fiber-based fronthaul on the overall performance of the communication system. In this setup, an arbitrary waveform generator (AWG) is employed for PPM signal generation, while demodulation is performed with a commercial time-to-digital converter (TDC) based on an event timer. To enhance the reliability of transmitted reference PPM (TR-PPM) signals, the transmission system integrates Gray coding and Consultative Committee for Space Data Systems (CCSDS)-standard-compliant Reed-Solomon (RS) error correcting code (ECC). System performance was evaluated by transmitting pseudorandom binary sequences (PRBSs) and measuring the bit error ratio (BER) across a 5-m wireless link between two 20 $\mathrm{d}\mathrm{B}\mathrm{i}$ gain horn (Ka-band) antennas, with and without a 20 $\mathrm{k}\mathrm{m}$ single-mode optical fiber (SMF) link in transmitter side and ECC at the receiver side. The system achieved a BER of less than 8.17 × 10⁻⁷, using a time bin duration of 200 $\mathrm{p}\mathrm{s}$ and a pulse duration of 100 $\mathrm{p}\mathrm{s}$, demonstrating robust performance and significant potential for space-to-ground telecommunication applications. Full article

Precision timing is a key requirement for emerging 4D particle tracking, Positron Emission Tomography (PET), beam and fusion plasma diagnostics, and other systems. Time-to-Digital Converters (TDCs) are commonly used to provide digital estimates of the relative timing between events, but the jitter performance of a TDC can be no better than the performance of the circuits that acquire the pulses and deliver them to the TDC. Several clock receiver and distribution circuits were evaluated, and a differential amplifier with resistive loads driving a pseudo-differential clock distribution network, developed using design guidelines for radiation tolerance and cryogenic compatibility, was fabricated as part of three prototypes: an analog front-end testbed chip for high-precision timing pixel readout, a dedicated TDC evaluation chip, and a Low-Gain Avalanche Detector (LGAD) readout circuit. Based on TDC measurements of the prototypes, we infer that the jitter added by the clock receiver and distribution circuits is less than 2.25 ps-rms. This performance meets the requirements of many future precision timing systems. The clock receiver and on-chip pseudo-differential driver were fabricated in commercial 28-nm CMOS technology and occupy 2288 µm². Full article

Time-to-Digital Converters (TDCs) are increasingly vital in modern measurement systems, with Field-Programmable Gate Arrays (FPGAs) offering a cost-effective platform despite challenges in asynchronous circuit design. Among various solutions, Tapped Delay-Line (TDL)-TDCs stand out for balancing precision, speed, and resource efficiency. However, a primary concern in FPGA-based TDL-TDCs are the Bubble Errors (BEs), i.e., spurious zeros introduced in the information code in the TDL that put the measurement precision at severe risk. The main goal of this contribution is to investigate the distribution of BEs, utilizing the Clock Region Crossing (CRC) within the FPGA as a case study, in order to demonstrate theoretically and experimentally that if BEs are manipulated properly, they create an interpolation effect that reduces the quantization error of the TDL-TDC. The analysis is carried out on a 256-tap fully integrated TDL-TDC implemented in a 28 nm Xilinx Artix 100T FPGA. The outcome confirms the potential to use CRC-BEs instead of suppressing them with precision increasing up to 0.17 ps r.m.s., or by almost 2% while also supporting the correctness of the model. Full article

This paper reviews recent developments in highly integrated all-digital frequency synthesizers suitable to deploy in low-power internet-of-things (IoT) applications. This review sets low power consumption as a key criterion for exploring the all-digital frequency synthesizer implemented in CMOS fabrication technology. The alignment with mainstream CMOS technology offers high-density, comprehensive, robust signal processing capability, making it very suitable for all-digital phase-locked loops to harvest that capacity, and it becomes inevitable. This review includes various divider-less low-power frequency synthesizers, including all-digital phase-locked loops (ADPLL), all-digital frequency-locked loops (ADFLL), and hybrid PLLs. This paper also discusses the latest architectural developments for ADPLLs to lead to low-power implementation, such as DTC-assisted TDC, embedded TDC, and various levels of hybridization in ADPLLs. Full article

Pixellated scintillation detectors have the potential to overcome several limitations of conventional microchannel-plate-based detectors employed in time-of-flight mass spectrometry (ToF-MS), such as extending detector lifetime, reducing vacuum requirements, or increasing the ion throughput. We have developed a prototype comprising a fast organic scintillator (Exalite 404) coupled to an array of 16 silicon photomultipliers (SiPMs), with read-out electronics based on the FastIC application-specific integrated circuit (ASIC). Each SiPM signal processed by FastIC is fed into its own time-to-digital converter (TDC). The dead time of a single channel can be as short as ∼20 ns. As a result, our system have the potential to process ion rates above ${10}^9$ cm⁻² s⁻¹. We have evaluated the performance of our prototype using a velocity-map imaging ToF-MS instrument, recording the time-of-flight mass spectra of C₃H₆ and CF₃I samples. We achieved time resolutions of ($3.3\pm 0.1$) and ($2.5\pm 0.2$) ns FWHM for ions of mass-to-charge ratio ($m/z$) values of 196 and 18, respectively. This corresponds to a mass resolution of ∼1000 for $m/z<200$, which we found to be dominated by the spread in ion arrival times. Full article

This study investigated implementation strategies to optimize the precision of Tapped Delay Line (TDL) Time-to-Digital Converters (TDCs) designed for Xilinx 20 nm UltraScale Field-Programmable Gate Arrays (FPGAs). This optimization process aims to bridge the performance gap between FPGA-based TDCs, which are more flexible and suitable for fast prototyping, and the better-performing Application-Specific Integrated Circuit (ASIC) solutions, making FPGA-based TDCs viable for cutting-edge applications. Our key areas of focus included the optimal design of the decoder, the degree of sub-interpolation, and the placement of TDLs, with particular emphasis on the clocking distribution scheme within the Configurable Logic Block (CLB) to minimize the effects of Bubble Errors (BEs) and quantization error. The research led to the development and comparison of multiple TDL TDC solutions implemented on a Kintex UltraScale device (i.e., XCKU040-2FFVA1156E) housed on a KCU105 general-purpose Evaluation Board (EVB). From these, two main solutions emerged: one with high precision and one with low area. The first one was characterized by a Single-Shot Precision (SSP) of 2.64 ps r.m.s., and by Differential and Integral Non-Linearity (DNL/INL) Errors of 0.523 ps and 16.939 ps, respectively, occupying 883 CLBs and 126 kb of Block RAM (BRAM). The second one had an SSP of 3.75 ps r.m.s., a DNL of 0.599 ps, and an INL of 7.151 ps, and it occupies only 259 CLBs and 72 kb of BRAM. Full article

The Streak-Tube Imaging Lidar (STIL) has been widely used in high-precision measurement systems due to its ability to capture detailed spatial and temporal information. In this paper, we proposed a ranging measurement method that integrates a Time-to-Digital Converter (TDC) with a streak camera in a remote STIL system. In this method, the TDC accurately measures the trigger pulse time, while the streak camera captures high time-resolution images of the laser echo, thereby enhancing both measurement accuracy and range. A corresponding ranging model is developed for this method. To validate the system’s performance, an outdoor experiment covering a distance of up to 6 km was conducted. The results demonstrate that the system achieved a distance measurement accuracy of 0.1 m, highlighting its effectiveness in long-range applications. The experiment further confirms that the combination of STIL and TDC significantly enhances accuracy and range, making it suitable for various long-range, high-precision measurement tasks. Full article

This paper presents advancements in the performance of digital phase-locked loop (DPLL)s, with a special focus on addressing the issue of required gain calibration in the time-to-digital converter (TDC) within phase-domain DPLL structures. Phase-domain DPLLs are preferred for their simplicity in implementation and for eliminating the delta–sigma modulator (DSM) noise inherent in conventional fractional-N designs. However, this advantage is countered by the critical need to calibrate the gain of the TDC. The previously proposed dual-interpolated TDC(DI-TDC) was proposed as a solution to this problem, but strong spurs were still generated due to the TDC resolution, which easily became non-uniform due to PVT variation, degrading performance. To overcome these problems, this work proposes a DPLL with a new calibration system that ensures consistent TDC resolution matching the period of the digitally controlled oscillator (DCO) and operating in both the foreground and background, thereby maintaining consistent performance despite PVT variations. This study proposes a DPLL using a calibrated dual-interpolated TDC that effectively compensates for PVT variations and improves the stability and performance of the DPLL. The PLL was fabricated in a 28-nm CMOS process with an active area of only 0.019 mm², achieving an integrated phase noise (IPN) performance of −17.5 dBc, integrated from 10 kHz to 10 MHz at a PLL output of 570 MHz and −20.5 dBc at 1.1 GHz. This PLL operates within an output frequency range of 475 MHz to 1.1 GHz. Under typical operating conditions, it consumes only 930 µW with a 1.0 V supply. Full article

This paper proposes an adaptive acceleration lock compensation technology for phase-locked loops (PLLs) based on a novel dual-mode programmable ring voltage-controlled oscillator (ring-VCO). In addition, a time-to-digital converter (TDC) is designed to accurately quantify the phase difference from the phase frequency detector (PFD) in order to optimize the dead-zone effect while dynamically switching an auxiliary charge pump (CP) module to realize fast phase locking. Furthermore, a TDC-controlled three/five-stage dual-mode adaptively continuously switched VCO is proposed to optimize the phase noise (PN) and power efficiency, leading to an optimal performance tradeoff of the PLL. Based on the 180 nm/1.8 V standard CMOS technology, the complete PLL design and a corresponding simulation analysis are implemented. The results show that, with a 1 GHz reference signal as the input, the output frequency is 50–324 MHz, with a wide tuning range of 260 MHz and a low phase noise of −98.07 dBc/Hz@1 MHz. The key phase-locking time is reduced to 1.11 μs, and the power dissipation is lowered to 1.86 mW with a layout area of 66 μm × 128 μm. A significantly remarkable multiobjective performance tradeoff with topology optimization is realized, which is in contrast to several similar design cases of PLLs. Full article

A high resolution, acceptable accuracy and low power consumption time-domain temperature sensor is proposed and simulated in this paper based on a 180 nm standard CMOS technology. A diode stacking structure is introduced to enhance the accuracy of the temperature sensing core. To improve the resolution of the sensor, a dual-input capacitor multiplexing voltage-to-time converter (VTC) is implemented. Additionally, a low-temperature drift voltage-mode relaxation oscillator (ROSC) is proposed, effectively reducing the large oscillation frequency drift caused by significant temperature impacts on delay errors. The simulated results show that the resolution is as high as 0.0071 °C over 0∼120 °C with +0.43 °C/−0.38 °C inaccuracy and 1.9 pJ · K² resolution FoM, consuming only 1.48 $\mathsf{\mu }$W at a 1.2 V supply voltage. Full article

Digital histogram generation for time-resolved measurements with single-photon avalanche diode (SPAD) sensors requires the storage of many timestamp signals. This work presents a mixed-signal time-to-digital converter (TDC) that uses analog storage to achieve an area-efficient design that can be integrated in large SPAD arrays. Fabricated using a 150 nm CMOS process, the prototype occupies an area of only 18.3 µm × 36.5 µm, a notable size reduction compared to conventional designs. The experimental results demonstrated high performance, with an integral nonlinearity (INL) of 0.35/0.14 least significant bit (LSB) and a differential nonlinearity (DNL) of 0.14/−0.12 LSB. In addition, the proposed TDC can support the construction of histograms comprising up to 512 bins, making it an effective solution to accommodate a wide range of resolution requirements. Validated in a point-of-care (PoC) device for fluorescence lifetime measurements, it distinguished between lifetimes of approximately 4.1 ns, 3.6 ns and 80 ns with the Alexa Fluor (AF) 546 and 568 dyes and Quantum Dot (QD) 705, respectively. The analog storage design and area-efficient architecture offer a novel approach to integrating TDCs in SPAD-based systems, with potential applications in medical diagnostics and beyond. Full article