Search Results (25)

A vanadium dioxide (VO₂)-based layered metastructure is proposed that enables dynamic optical encoding in the range of 15.5 GHz to 16 GHz through synergistic temperature and magnetic field modulation. By utilizing sequential temperature control, an optical date flip-flop (DFF) functionality can be achieved. The VO₂ component of the metastructure exhibits an insulator-to-metal phase transition under thermal regulation, accompanied by significant changes in its optical properties. Furthermore, by optimizing the sequential temperature-control strategy, an optical DFF is successfully implemented whose output state can be dynamically controlled by the data input (D), timing control port (T), and state control port (B). A novel technical approach is provided for programmable photonic devices, dynamic optical information storage, and optical computing systems. Full article

Due to technological advancement, the advent of smart cities has facilitated the deployment of advanced urban management systems. This integration has been made possible through the Internet of Vehicles (IoV), a foundational technology. By connecting smart cities with vehicles, the IoV enhances the safety and efficiency of transportation. This interconnected system facilitates wireless communication among vehicles, enabling the exchange of crucial traffic information. However, this significant technological advancement also raises concerns regarding privacy for individual users. This paper presents an innovative privacy-preserving authentication scheme focusing on IoV using physical unclonable functions (PUFs). This scheme employs the k-nearest neighbor (KNN) encryption technique, which possesses a multi-multi searching property. The main objective of this scheme is to authenticate autonomous vehicles (AVs) within the IoV framework. An innovative PUF design is applied to generate random keys for our authentication scheme to enhance security. This two-layer security approach protects against various cyber-attacks, including fraudulent identities, man-in-the-middle attacks, and unauthorized access to individual user information. Due to the substantial amount of information that needs to be processed for authentication purposes, our scheme is implemented using hardware acceleration on an Nexys A7-100T FPGA board. Our analysis of privacy and security illustrates the effective accomplishment of specified design goals. Furthermore, the performance analysis reveals that our approach imposes a minimal communication and computational burden and optimally utilizes hardware resources to accomplish design objectives. The results show that the proposed authentication scheme exhibits a non-linear increase in encryption time with a growing AV ID size, starting at 5$\mathsf{\mu }$s for 100 bits and rising to 39 $\mathsf{\mu }$s for 800 bits. Also, the result demonstrates a more gradual, linear increase in the search time with a growing AV ID size, starting at less than 1 $\mathsf{\mu }$s for 100 bits and rising to less than 8 $\mathsf{\mu }$s for 800 bits. Additionally, for hardware utilization, our scheme uses only 25% from DSP slides and IO pins, 22.2% from BRAM, 5.6% from flip-flops, and 24.3% from LUTs. Full article

Design-for-test/debug (DfT/D) introduces scan chain testing to increase testability and fault coverage by inserting scan flip-flops. However, these scan chains are also known to be a liability for security primitives. In previous research, the dynamically obfuscated scan chain (DOSC) was introduced to protect logic-locking keys from scan-based attacks by obscuring test patterns and responses. In this paper, we present DOSCrack, an oracle-guided attack to de-obfuscate DOSC using symbolic execution and binary clustering, which significantly reduces the candidate seed space to a manageable quantity. Our symbolic execution engine employs scan mode simulation and satisfiability modulo theories (SMT) solvers to reduce the possible seed space, while obfuscation key clustering allows us to effectively rule out a group of seeds that share similarities. An integral component of our approach is the use of sequential equivalence checking (SEC), which aids in identifying distinct simulation patterns to differentiate between potential obfuscation keys. We experimentally applied our DOSCrack framework on four different sizes of DOSC benchmarks and compared their runtime and complexity. Finally, we propose a low-cost countermeasure to DOSCrack which incorporates a nonlinear feedback shift register (NLFSR) to increase the effort of symbolic execution modeling and serves as an effective defense against our DOSCrack framework. Our research effectively addresses a critical vulnerability in scan-chain obfuscation methodologies, offering insights into DfT/D and logic locking for both academic research and industrial applications. Our framework highlights the need to craft robust and adaptable defense mechanisms to counter evolving scan-based attacks. Full article

This paper proposes a unique configuration for an all-optical D Flip Flop (D-FF) utilizing a quasi-square ring resonator (RR) and T-Splitter, as well as NOT and OR logic gates within a 2-dimensional square lattice photonic crystal (PC) structure. The components realizing the all-optical D-FF comprise of optical waveguides in a 2D square lattice PC of 45 × 23 silicon (Si) rods in a silica (SiO₂) substrate. The utilization of these specific materials has facilitated the fabrication process of the design, diverging from alternative approaches that employ an air substrate, a method inherently unattainable in fabrication. The configuration underwent examination and simulation utilizing both plane-wave expansion (PWE) and finite-difference time-domain (FDTD) methodologies. The simulation outcomes demonstrate that the designed waveguides and RR effectively execute the operational principles of the D-FF by guiding light as intended. The suggested configuration holds promise as a logic block within all-optical arithmetic logic units (ALUs) designed for digital computing optical circuits. The design underwent optimization for operation within the C-band spectrum, particularly at 1550 nm. The outcomes reveal a distinct differentiation between logic states ‘1’ and ‘0’, enhancing robust decision-making on the receiver side and minimizing logic errors in the photonic decision circuit. The D-FF displays a contrast ratio (CR) of 4.77 dB, a stabilization time of 0.66 psec, and a footprint of 21 μm × 12 μm. Full article

The exponential emergence of Field-Programmable Gate Arrays (FPGAs) has accelerated research on hardware implementation of Deep Neural Networks (DNNs). Among all DNN processors, domain-specific architectures such as Google’s Tensor Processor Unit (TPU) have outperformed conventional GPUs (Graphics Processing Units) and CPUs (Central Processing Units). However, implementing low-power TPUs in reconfigurable hardware remains a challenge in this field. Voltage scaling, a popular approach for energy savings, can be challenging in FPGAs, as it may lead to timing failures if not implemented appropriately. This work presents an ultra-low-power FPGA implementation of a TPU for edge applications. We divide the systolic array of a TPU into different FPGA partitions based on the minimum slack value of different design paths of Multiplier Accumulators (MACs). Each partition uses different near-threshold (NTC) biasing voltages to run its FPGA cores. The biasing voltage for each partition is roughly calculated by the proposed static schemes. However, further calibration of biasing voltage is performed by the proposed runtime scheme. To overcome the timing failure caused by NTC, the MACs with higher minimum slack are placed in lower-voltage partitions, while the MACs with lower minimum slack paths are placed in higher-voltage partitions. The proposed architecture is implemented in a commercial platform, namely $Vivado$ with Xilinx $Artix\text{-}7$ FPGA and academic platform $VTR$ with 22 nm, 45 nm and 130 nm FPGAs. Any timing error caused by NTC can be caught by the Razor flipflop used in each MAC. The proposed voltage-scaled, partitioned systolic array can save 3.1% to 11.6% of dynamic power in $Vivado$ and $VTR$ tools, respectively, depending on the FPGA technology, partition size, number of partitions and biasing voltages. The normalized performance and accuracy of benchmark models running on our low-power TPU are very competitive compared to existing literature. Full article

Phase jitter is one of the crucial factors in modern digital electronics, determining the reliability of a design. This paper presents a novel approach to designing a jitter comparison system and methodology for FPGA chips using a Tapped Delay Line (TDL)—commonly used to implement a Time-to-Digital Converter (TDC). The design and its revision utilizing latches replacing some of the flip-flops are presented and discussed, with potential further improvements. A minimal temperature influence is verified and presented. The methodology of automated relative jitter measurements is discussed. Multiple different FPGA clock signal path configurations are measured, and the results are presented. The influence of clock routing is identified as critical when MMCM or PLL modules are omitted. It is demonstrated that with careful resource and routing allocation, the clock signal’s jitter performance does not have to be deteriorated by the absence of jitter filtering blocks. The proposed technique was implemented and verified and relative jitter performance was measured in the AMD/Xilinx Artix 7 35T FPGA platform. Full article

This article presents the design and optimization of a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider. The VCO is designed for the low-power and low-phase-noise applications of 2.4 GHz IoT/BLE receivers and wireless sensor devices. The proposed design comprises the proper stacking of an LC VCO and a DFF frequency divider and is simulated using a TSMC 65 nm CMOS technology, and it has a tuning range of 4.4 to 5.7 GHz. The voltage headroom is preserved using a high-impedance on-chip passive inductor at the tail for filtering and enabling true differential operation. The VCO and frequency divider consume as low as 2.02 mW altogether, with the VCO section consuming only 0.47 mW. The active area of the chip including the pads is only 0.47 mm². The designed VCO achieved a much better phase noise of −118.36 dBc/Hz at a 1 MHz offset frequency with 1.2 V supply voltages. The design produced a much better FoM of −196.44 dBc/Hz compared to other related research. Full article

This paper presents a design and implementation proposal for a real-time frequency measurement system for high-precision, multi-channel quartz crystal microbalance (QCM) sensors using a field programmable gate array (FPGA). The key contribution of this work lies in the integration of a frequency measurement and mass resolution computation based on Global Positioning System (GPS) signals within a single FPGA chip, utilizing Input/Output Blocks to incorporate logic QCM oscillator circuits. The FPGA design enables parallel processing, ensuring accurate measurements, faster calculations, and reduced hardware complexity by minimizing the need for external components. As a result, a cost-effective and accurate multi-channel sensor system is developed, serving as a reconfigurable standalone measurement platform with communication capabilities. The system is implemented and tested using the FPGA Xilinx Virtex-6, along with multiple QCM sensors. The implementation on a Xilinx XC6VLX240T FPGA achieves a maximum frequency of 324 MHz and consumes a dynamic power of 120 mW. Notably, the design utilizes a modest number of resources, requiring only 188 slices, 733 flip-flops, and 13 IOBs to perform a double-channel sensor microbalance. The proposed system meets the precision measurement requirements for QCM sensor applications, exhibiting low measurement error when monitoring QCM frequencies ranging from 1 to 50 MHz, with an accuracy of 0.2 ppm and less than 0.1 Hz. Full article

The aim of this study was to evaluate in vitro skin permeation and deposition, in vivo toxicokinetics, percutaneous absorption and tissue distribution of benzophenone-3 (BP-3) in rats. Four transdermal formulations containing BP-3 were prepared and evaluated for in vitro skin permeation and deposition of BP-3 using Franz diffusion cells. A gel formulation was used in subsequent in vivo percutaneous absorption due to its high in vitro skin permeation and deposition. Compared to intravenous (i.v.) injection, the prolonged terminal t_1/2 (3.1 ± 1.6 h for i.v. injection and 18.3 ± 5.8 h for topical application) was observed indicating occurrence of flip-flop kinetics after topical application. The bioavailability of BP-3 after topical application was 6.9 ± 1.8%. The tissue-to-plasma partition coefficient (kp) for testis, considered a toxic target for BP-3, was less than 1. Overall, findings of this study may be useful for risk assessment of BP-3. Full article

EPR spin labeling has been used extensively to study lipids in model membranes to understand their structures and dynamics in biological membranes. The lipid multilamellar liposomes, which are the most commonly used biological membrane model, were prepared using film deposition methods and investigated with the continuous wave EPR technique (T₂-sensitive spin-labeling methods). These investigations provided knowledge about the orientation of lipids, their rotational and lateral diffusion, and their rate of flip-flop between bilayer leaflets, as well as profiles of membrane hydrophobicity, and are reviewed in many papers and book chapters. In the early 1980s, the saturation recovery EPR technique was introduced to membrane studies. Numerous T₁-sensitive spin-label methods were developed to obtain detailed information about the three-dimensional dynamic membrane structure. T₁-sensitive methods are advantageous over T₂-sensitive methods because the T₁ of spin labels (1–10 μs) is 10 to 1000 times longer than the T₂, which allows for studies of membrane dynamics in a longer time–space scale. These investigations used multilamellar liposomes also prepared using the rapid solvent exchange method. Here, we review works in which saturation recovery EPR spin-labeling methods were applied to investigate the properties of multilamellar lipid liposomes, and we discuss their relationships to the properties of lipids in biological membranes. Full article

Transport Layer Security (TLS) provides a secure channel for end-to-end communications in computer networks. The ChaCha20–Poly1305 cipher suite is introduced in TLS 1.3, mitigating the sidechannel attacks in the cipher suites based on the Advanced Encryption Standard (AES). However, the few implementations cannot provide sufficient speed compared to other encryption standards with Authenticated Encryption with Associated Data (AEAD). This paper shows ChaCha20 and Poly1305 primitives. In addition, a compatible ChaCha20–Poly1305 AEAD with TLS 1.3 is implemented with a fault detector to reduce the problems in fragmented blocks. The AEAD implementation reaches 1.4-cycles-per-byte in a standalone core. Additionally, the system implementation presents 11.56-cycles-per-byte in an RISC-V environment using a TileLink bus. The implementation in Xilinx Virtex-7 XC7VX485T Field-Programmable Gate-Array (FPGA) denotes 10,808 Look-Up Tables (LUT) and 3731 Flip-Flops (FFs), represented in 23% and 48% of ChaCha20 and Poly1305, respectively. Finally, the hardware implementation of ChaCha20–Poly1305 AEAD demonstrates the viability of using a different option from the conventional cipher suite based on AES for TLS 1.3. Full article

Quantum-dot cellular automata is a novel nanotechnology that has the advantages of low energy dissipation, easy integration, and high computing speed. It is regarded as one of the powerful alternative technologies for the next generation of integrated circuits because of its unique implementation concept. In this paper, two XOR/XNOR gates are proposed. Level-sensitive T flip-flops, negative edge-trigger T flip-flops, two-to-one multiplexers, reversible gates, and (8, 4) polar encoders are implemented based on these two proposed logic gates. Simulation results show that, compared with the existing level-sensitive T flip-flops, the second proposed level-sensitive T flip-flop has fewer cells and lower energy dissipation; compared with the best (8, 4) polar encoder, the cell count and area of the second proposed (8, 4) polar encoder are decreased by 13.67% and 12.05%, respectively. The two XOR/XNOR gates have a stable output and low energy dissipation, which can be flexibly designed into complex quantum-dot cellular automata circuits. Full article

In this paper, a flip-flop (FF) that minimizes the transition of internal nodes by using a dual change-sensing scheme is discussed. Further, in order to reduce power consumption, a new technique to eliminate short-circuit currents is described. The proposed dual change-sensing FF (DCSFF) composed of 24T (T: number of transistors) has the lowest dynamic power consumption among conventional FFs, independent of the data activity ratio. According to the measured results with a 65 nm CMOS process, the power consumption of DCSFF is reduced by 98% and 32%, when the data activity is close to 0% and 100%, respectively, compared to that of conventional transmission gate FF. Further, compared to that of change-sensing FF, the power consumption of DCSFF is reduced by 26% when the data activity is close to 100%. Full article

We have simulated a monolithic three-dimensional inverter (M3DINV) structure by considering the interfacial trap charges generated thermally during the monolithic three-dimensional integration process. We extracted the SPICE model parameters from M3DINV structures with two types of inter-layer dielectric thickness T_ILD (=10,100 nm) using the extracted interface trap charge distribution of the previous study. Logic circuits, such as inverters (INVs), ring oscillators (ROs), a 2 to 1 multiplexer (MUX), and D flip-flop and 6-transistor static random-access memory (6T SRAM) containing M3DINVs, were simulated using the extracted model parameters, and simulation results both with and without interface trap charges were compared. The extracted model parameters reflected current reduction, threshold voltage increase, and subthreshold swing (SS) degradation due to the interface trap charge. HSPICE simulation results of the fanout-3 (FO3) ring oscillator considering the interface trap charges showed a 20% reduction in frequency and a 30% increase in propagation delay compared to those without the interface trap charges. The propagation delays of the 2 × 1 MUX and D flip-flop with the interface trap charges were approximately 78.2 and 39.6% greater, respectively, than those without the interface trap charges. The retention static noise margin (SNM) of the SRAM increased by 16 mV (6.4%) and the read static noise margin (SNM) of SRAM decreased by 43 mV (35.8%) owing to the interface trap charge. The circuit simulation results revealed that the propagation delay increases owing to the interface trap charges. Therefore, it is necessary to fully consider the propagation delay of the logic circuit due to the generated interface trap charges when designing monolithic 3D integrated circuits. Full article

Digital cores that are currently incorporated into advanced Systems on Chip (SoC) frequently include Logic Built-In Self-Test (LBIST) modules with the Self-Test Using MISR/Parallel Shift Register Sequence Generator (STUMPS) architecture. Such a solution always comprises a Pseudo-Random Pattern Generator (PRPG), usually designed as a Linear Feedback Shift Register (LFSR) with a phase shifter attached to the register and arranged as a network of XOR gates. This study discloses an original and innovative structure of such a PRPG unit referred to as the DT-LFSR-TPG module that needs no phase shifter. The module is designed as a set of identical linear registers of the DT-LFSR type with the same primitive polynomial. Each register has a form of a ring made up exclusively of D and T flip-flops. This study is focused on the investigation of those parameters of DT-LFSR registers that are essential to use these registers as components of PRPG modules. The investigated parameters include phase shifts and the correlation between sequences of bits appearing at outputs of T flip-flops, implementation cost, and the maximum frequency of the register operation. It is demonstrated that PRPG modules of the DT-LFSR-TPG type enable much higher phase shifts and substantially higher operation frequencies as compared to competitive solutions. Such modules can also drive significantly more scan paths than other PRPGs described in reference studies and based on phase shifters. However, the cost of the foregoing advantages of DT-LFSR-TPG modules is the larger hardware overhead associated with the implementation of the solution proposed. Full article