Search Results (84)

This paper presents the growth and in situ optical characterization of silicon nanowires (Si NWs) on Al₂O₃(0001) substrates that are thermally faceted using the atomic low angle shadowing technique (ATLAS) method. Annealing Al₂O₃ substrates in air before surface faceting was used for the first time, as identified by atomic force microscopy (AFM). Planar Si NW arrays were subsequently deposited and characterized in real-time by reflectance anisotropy spectroscopy (RAS). RAS measurements detected irreversible spectral changes during growth, e.g., red-shift in peak energy for marking amorphous Si NW formation. Blue-shifts in RAS spectra following annealing post-growth at varied temperatures were found to be associated with structural nanowire development. AFM analysis following annealing detected dramatic changes in morphology, e.g., quantifiable differences in NW height and thickness and complete disappearance of nanowire structures at high temperatures. These results confirm the validity of in situ RAS as a monitoring tool for nanowire growth and illustrate Si NW morphology’s sensitivity to thermal processing. Full article

The crystal structure of kuliokite-(Y), Y₄Al(SiO₄)₂(OH)₂F₅, has been re-investigated using the material from the type locality the Ploskaya Mt, Kola peninsula, Russian Arctic. It has been shown that in contrast to previous studies, the mineral is monoclinic, Im, with a = 4.3213(1), b = 14.8123(6), c = 8.6857(3) Å, β = 102.872(4)°, and V = 541.99(3) ų. The crystal structure was solved and refined to R₁ = 0.030 on the basis of 3202 unique observed reflections. The average chemical composition determined by electron microprobe analysis is (Y_2.96Yb_0.49Er_0.27Dy_0.13Tm_0.07Lu_0.05Ho_0.05Gd_0.01Ca_0.01)_Σ4.04Al_0.92Si_2.04O₈-[(OH)_2.61F_4.42]_Σ7.03; the idealized formula is (Y,Yb,Er)₄Al[SiO₄]₂(OH)_2.5F_4.5. The crystal structure of kuliokite-(Y) contains two symmetrically independent Y sites, Y1 and Y2, coordinated by eight and seven X anions, respectively (X = O, F). The coordination polyhedra can be described as a distorted square antiprism and a distorted pentagonal bipyramid, respectively. The refinement of site occupancies indicated that the mineral represents a rare case of HREE fractionation among two cation sites driven by their coordination numbers and geometry. In agreement with the lanthanide contraction, HREEs are selectively incorporated into the Y2 site with a smaller coordination number and tighter coordination environment. The strongest building unit of the structure is the [AlX₂(SiO₄)₂] chain of corner-sharing AlX₆ octahedra and SiO₄ tetrahedra running along the a axis. The chains have their planes oriented parallel to (001). The Y atoms are located in between the chains, along with the F⁻ and (OH)⁻ anions, providing the three-dimensional integrity of the crystal structure. Each F⁻ anion is coordinated by three Y³⁺ cations to form planar (FY₃)⁸⁺ triangles parallel to the (010) plane. The triangles share common edges to form [F₂Y₂]⁴⁺ chains parallel to the a axis. The analysis of second-neighbor coordination of Y sites allowed us to identify the structural topology of kuliokite-(Y) as the only case of the skd network in inorganic compounds, previously known in molecular structures only. The variety of anionic content in the mineral allows us to identify the potential existence of two other mineral species that can tentatively be named ‘fluorokuliokite-(Y)’ and ‘hydroxykuliokite-(Y)’. Full article

Growing demand for high-performance system semiconductors has highlighted the importance of hybrid bonding, where precise control of copper dishing is essential. This requirement reinforces the role of chemical mechanical planarization (CMP). Many studies have sought to control dishing by modifying slurry chemistry or adjusting mechanical parameters, but these approaches have not been sufficient. This study addresses the overlooked effect of process temperature and demonstrates its role in integrating both chemical and mechanical behaviors in CMP. Removal rates of Cu, Ta, and SiO₂ films were evaluated through blanket wafer experiments, and all exhibited Arrhenius-type behavior as a function of temperature and activation energy. The results showed that maintaining the process temperature at 30 °C balanced selectivity and minimized dishing on patterned wafers. To enable precise temperature control, a vortex-tube-based pad cooling system was developed. Without temperature control, dishing increased by 12 nm in the 100 µm pattern and 16 nm in the 50 µm pattern. With temperature control, dishing was reduced to 4 nm and below 1 nm, respectively. These results demonstrate that process temperature is a key parameter for controlling selectivity and ensuring precise dishing control, which is critical to meeting the requirements of hybrid bonding. Full article

This paper presents the design of an ultrabroadband solar absorber, developed using a metamaterial stack composed of only two materials, consisting of alternating layers of Cr and SiO₂. Starting with a Cr layer as the substrate, multiple pairs of Cr and SiO₂ were stacked sequentially, where one Cr layer and one SiO₂ layer constitute a single pair. To further enhance performance, a cylindrical Cr structure was added to the top. A key innovation of this work lay in its material simplicity and cost efficiency, relying solely on two inexpensive materials, Cr and SiO₂. Additionally, the inclusion of the top Cr cylinder was found to significantly enhance absorptivity. Simulations demonstrate that removing this feature led to a noticeable reduction in absorptivity of approximately 10% across the 500–2000 nm wavelength range. Another important finding is the effect of the number of Cr–SiO₂ pairs on absorption behavior. When the number of pairs increases from four to five, the average absorptivity decreases slightly, but the absorption bandwidth is notably broadened. Further increasing six pairs resulted in a marginal increase in bandwidth, while maintaining the average absorptivity. Moreover, a low-absorptivity dip at 360 nm was slightly mitigated, rising to approximately 0.900. Based on these insights, a six-pair metamaterial structure was chosen for further optimization. Utilizing COMSOL Multiphysics^® simulation software (version 6.0), the absorber was successfully engineered to achieve high performance across an exceptionally broad spectral range, from 200 nm to 2160 nm. Under optimal design parameters, it exhibited an average absorptivity of 0.950, with absorptivity consistently exceeding 0.900 throughout this range. This demonstrates the absorber’s strong potential for efficient solar energy harvesting using a structurally simple and cost-effective design. Full article

This study presents a reconfigurable planar photonic device capable of dynamically switching between optical filter and absorber functionalities by exploiting the phase transition properties of GeTe, a chalcogenide phase-change material. The device adopts a Metal–Dielectric–PCM architecture composed of silver (Ag), silicon dioxide (SiO₂), and GeTe layers, each playing a distinct role: the silver layer governs the transmission and absorption efficiency, the SiO₂ layer controls the resonance conditions, and the GeTe layer determines the device’s scattering behavior via its tunable optical losses. Numerical simulations revealed that the structure enables high RGB transmission in the amorphous state and broadband absorption in the crystalline state. By adjusting geometric parameters—especially the metallic thickness—the device exhibits finely tunable spectral responses under varying polarizations and incidence angles. These findings highlight the synergistic interplay between material functionality and layer configuration, positioning this platform as a compact and energy-efficient solution for applications in tunable photonics, optical sensing, and programmable metasurfaces. Full article

To satisfy the superior surface quality requirements in the fabrication of HBM (High-Bandwidth Memory) and 3D NAND Flash Memory, high-efficiency Si chemical mechanical planarization (CMP) is essential. In this study, a colloidal silica abrasive-based Si-wafer CMP slurry was developed to simultaneously achieve a high polishing rate (≥10 nm/min) and low surface roughness (≤0.2 nm) without inducing CMP-induced scratches. The proposed Si-wafer CMP slurry incorporates two functional components: triammonium phosphate (TAP) as a hydrolysis reaction accelerator and hydroxyethyl cellulose (HEC) as an abrasive drag force accelerator. The polishing rate enhancement mechanism of TAP was analyzed by monitoring the OH⁻ mol concentration, surface adsorption behavior, and XPS spectra. The results showed that increasing the TAP concentration raised the OH⁻ mol concentration and converted Si–Si and Si–O–Si bonds to Si–OH via a hydrolysis reaction, thereby increasing the polishing rate. However, excessive hydrolysis also led to increased surface roughness. On the other hand, HEC influenced slurry viscosity, abrasive dispersibility, and drag force. At low HEC concentrations, increased abrasive drag force improved the polishing rate. At high concentrations, however, HEC formed a hindrance layer on the Si surface via hydrogen bonding and condensation reactions, reducing the effective contact area of abrasives and thus decreasing the polishing rate. By optimizing the concentrations of TAP (0.0037 wt%) and HEC (≤0.0024 wt%), the proposed slurry formulation achieved high-performance Si-wafer CMP, satisfying both surface roughness and polishing rate targets required for advanced memory packaging applications. Full article

Photothermal conversion is a pivotal energy transformation mechanism in solar energy systems. Achieving high-efficiency and broadband photothermal conversion within the solar radiation spectrum holds strategic significance in driving the innovative development of renewable energy technologies. In this study, a transmission matrix method was employed to design an interference-type solar selective absorber based on multilayer Cr-SiO₂ planar films, successfully achieving an average absorption of 94% throughout the entire solar spectral range. Further analysis indicates that this newly designed absorber shows excellent absorption performance even at a relatively large incident angle (up to 60°). Additionally, the newly designed absorber demonstrates lower polarization sensitivity, enabling efficient operation under complicated incident conditions. With its simple fabrication process and ease of preparation, the proposed absorber holds substantial potential for applications in photothermal conversion fields such as solar thermal collectors. Full article

The atomic level polishing of a material surface affects the accuracy of devices and the application of materials. Silica slurries play an important role in chemical mechanical polishing (CMP) by polishing the material surface. In this study, an efficient and controllable Stöber approach was developed to synthesize uniform monodisperse silica spheres with different cationic surfactants. The obtained silica spheres exhibited a regular shape with a particle size of 50–150 nm and were distributed evenly and narrowly. The highest surface specific area of the silica spheres was approximately 1155.9 m²/g, which was conducive to the polish process. The monodisperse SiO₂ spheres were applied as abrasives in chemical mechanical polishing. The surface micrographs of silicon wafers during the CMP process were studied using atomic force microscopy (AFM). The results demonstrated that the surface roughness Ra values reduced from 1.07 nm to 0.979 nm and from 1.05 nm to 0.933 nm when using a CTAB-SiO₂ microsphere as an abrasive. These results demonstrate the advantages of monodisperse SiO₂ spheres as abrasive materials in chemical mechanical planarization processes. Full article

The transition of SiC MOSFET structure from planar to trench-based architectures requires the optimization of gate dielectric layers to improve device performance. This study utilizes a range of characterization techniques to explore the interfacial properties of ZrO₂ and SiO₂/ZrO₂ gate dielectric films, grown via atomic layer deposition (ALD) in SiC epitaxial trench structures to assess their performance and suitability for device applications. Scanning electron microscopy (SEM) and atomic force microscopy (AFM) measurements showed the deposition of smooth film morphologies with roughness below 1 nm for both ZrO₂ and SiO₂/ZrO₂ gate dielectrics, while SE measurements revealed comparable physical thicknesses of 40.73 nm for ZrO₂ and 41.55 nm for SiO₂/ZrO₂. X-ray photoelectron spectroscopy (XPS) shows that in SiO₂/ZrO₂ thin films, the binding energies of Zr 3d_5/2 and Zr 3d_3/2 peaks shift upward compared to pure ZrO₂. Electrical characterization showed an enhancement of E_BR (3.76 to 5.78 MV·cm⁻¹) and a decrease of I_{ON_EBR} (1.94 to 2.09 × 10⁻³ A·cm⁻²) for the SiO₂/ZrO₂ stacks. Conduction mechanism analysis identified suppressed Schottky emission in the stacked film. This indicates that the incorporation of a thin SiO₂ layer effectively mitigates the small bandgap offset, enhances the breakdown electric field, reduces leakage current, and improves device performance. Full article

This study proposed a novel perovskite/silicon heterojunction (SHJ) tandem device structure without an interlayer, represented as ITO/NiO/perovskite/SnO₂/MoO_X/i-a-Si:H/n-c-Si/i-a-Si:H/n-a-Si:H/Ag, which was investigated by Silvaco TCAD software. The recombination layer in this structure comprises the carrier transport layers of SnO₂ and MoO_X, where MoO_X serves dual functions, acting as the emitter for the SHJ bottom cell and as part of the recombination layer in the tandem cell. First, the effects of different recombination layers are analyzed, and the SnO₂/MoO_X layer demonstrates the best performance. Then, we systematically investigated the impact of the carrier concentration, interface defect density, thicknesses of the SnO₂/MoO_X layer, different hole transport layers (HTLs) for the top cell, absorption layer thicknesses, and perovskite defect density on device performance. The optimal carrier concentration in the recombination layer should exceed 5 × 10¹⁹ cm⁻³, the interface defect density should be below 1 × 10¹⁶ cm⁻², and the thicknesses of SnO₂/MoO_X should be kept at 20 nm/20 nm. CuSCN has been found to be the optimal HTL for the top cell. When the silicon absorption layer is 200 μm, the perovskite layer thickness is 470 nm, and the defect density of the perovskite layer is 10¹¹ cm⁻³, the planar structure can achieve the best performance of 32.56%. Finally, we studied the effect of surface texturing on the SHJ bottom cell, achieving a power conversion efficiency of 35.31% for the tandem cell. Our simulation results suggest that the simplified perovskite/SHJ tandem solar cell with a dual-functional MoO_X layer has the potential to provide a viable pathway for developing high-efficiency tandem devices. Full article

The heterogeneous integration of ferroelectric thin films on silicon- or silicon nitride-based platforms for photonic integrated circuits plays a crucial role in the development of nanophotonic thin film modulators. For this purpose, an ultrathin seed film was recently introduced as an integration method for ferroelectric thin films such as BaTiO₃ and Pb(Zr,Ti)O₃. One issue with this self-orienting seed film is that for non-planarized circuits, it fails to act as a template film for the thin films. To circumvent this problem, we propose a method of planarization without the need for wafer-scale chemical mechanical polishing by using hydrogen silsesquioxane as a precursor to forming amorphous silica, in order to create an oxide cladding similar to the thermal oxide often present on silicon-based platforms. Additionally, this oxide cladding is compatible with the high annealing temperatures usually required for the deposition of these novel ferroelectric thin films (600–800 °C). The thickness of this silica film can be controlled through a dry etch process, giving rise to a versatile platform for integrating nanophotonic thin film modulators on a wider variety of substrates. Using this method, we successfully demonstrate a hybrid BaTiO₃-Si ring modulator with a high Pockels coefficient of $r_{wg}=155.57\pm 10.91$ pm V⁻¹ and a half-wave voltage-length product of $V_{\pi }L=2.638\pm 0.084$ V cm, confirming the integration of ferroelectric thin films on an initially non-planar substrate. Full article

The progression of SiC MOSFET technology from planar to trench structures requires optimized gate oxide layers within the trench to enhance device performance. In this study, we investigated the interface characteristics of HfO₂ and SiO₂/HfO₂ gate dielectrics grown by atomic layer deposition (ALD) on SiC trench structures. The trench structure morphology was revealed using scanning electron microscopy (SEM). Atomic force microscopy (AFM) measurements showed that the roughness of both films was below 1nm. Spectroscopic ellipsometry (SE) indicated that the physical thicknesses of HfO₂ and SiO₂/HfO₂ were 38.275 nm and 40.51 nm, respectively, demonstrating their comparable thicknesses. X-ray photoelectron spectroscopy (XPS) analysis of the gate dielectrics revealed almost identical Hf 4f core levels for both HfO₂ and the SiO₂/HfO₂ composite dielectrics, suggesting that the SiO₂ interlayer and the SiC substrate had minimal impact on the electronic structure of the HfO₂ film. The breakdown electric field of the HfO₂ film was recorded as 4.1 MV/cm, with a leakage current at breakdown of 1.1 × 10⁻³A/cm². The SiO₂/HfO₂ stacked film exhibited significantly better performance, with a breakdown electric field of 6.5 MV/cm and a marked reduction in leakage current to 3.7 × 10⁻⁴ A/cm². A detailed extraction and analysis of the leakage current mechanisms were proposed, and the data suggested that the introduction of thin SiO₂ interfacial layers effectively mitigated small bandgap offset issues, significantly reducing leakage current and improving device performance. Full article

OH* generated through plasma catalysis offers several advantages, including a long survival time, high modification efficiency, and environmental friendliness. Consequently, a plasma-assisted polishing technology has rapidly developed. Previous studies exploring the interaction mechanism between OH* and 4H-SiC have often assumed flat surfaces. However, in the surface modification experiments on 4H-SiC, the actual surface morphology was not flat but contained numerous scratches. Therefore, this study investigated the interaction mechanism of OH* on an uneven surface using reactive force field molecular dynamics (ReaxFF MD) simulations. The results show that in the low-speed OH* modification process, the adsorption effect leads to a thicker modified layer at higher locations than at lower locations. The resulting modified layer can be removed by soft abrasive mechanical polishing to achieve surface flatness, but there will be a modified layer on the surface, which needs to be modified and polished several times. In contrast, during high-speed OH* modification, high-speed particle bombardment causes more Si-O bonds to diffuse into the scratches, resulting in the formation of a flat bonding layer with surface planarization achieved after a single polishing step. The interaction mechanism of OH* with the uneven surface at different speeds, as obtained through ReaxFF MD, provides a theoretical foundation for subsequent polishing experiments. Full article

This study utilized semiconductor processing techniques to fabricate patterned silicon (Si) substrates with arrays of inverted pyramid-shaped micro-pits by etching. Molybdenum trioxide (MoO₃) was then deposited on these patterned Si substrates using a thermal evaporation system, followed by two-stage sulfurization in a high-temperature furnace to grow MoS₂ thin films consisting of only a few atomic layers. During the dropwise titration of Rhodamine 6G (R6G) solution, a longitudinal electric field was applied using a Keithley 2400 (Cleveland, OH, USA) source meter. Raman mapping revealed that under a 100 mV condition, the analyte R6G molecules were effectively confined within the pits. Due to its two-dimensional structure, MoS₂ provides a high surface area and supports a surface-enhanced Raman scattering (SERS) charge transfer mechanism. The SERS results demonstrated that the intensity in the pits of the few-layer MoS₂/patterned Si SERS substrate was approximately 274 times greater compared to planar Si, with a limit of detection reaching 10⁻⁵ M. The experimental results confirm that this method effectively resolves the issue of random distribution of analyte molecules during droplet evaporation, thereby enhancing detection sensitivity and stability. Full article

This work investigates the gate oxide reliability of commercial 1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The performance of threshold voltage $\left({\mathrm{V}}_{\mathrm{t}\mathrm{h}}\right)$ and gate leakage current $\left({\mathrm{I}}_{\mathrm{g}\mathrm{s}\mathrm{s}}\right)$ in SiC MOSFETs is evaluated under positive and negative gate voltage stress. The oxide lifetimes of SiC planar and trench MOSFETs at 150 °C are measured using constant voltage Time-Dependent Dielectric Breakdown (TDDB) testing. From the test results, it is found that electron trapping and hole trapping in ${\mathrm{S}\mathrm{i}\mathrm{O}}_2$ caused by oxide electric field $\left({\mathrm{E}}_{\mathrm{o}\mathrm{x}}\right)$ stress affect the ${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$ of SiC MOSFETs. The saturation and turnaround behavior of the ${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$ shift during positive and negative gate voltage stresses indicates that the influence of charge trapping in the gate oxide varies with stress time. The ${\mathrm{I}}_{\mathrm{g}\mathrm{s}\mathrm{s}}$ under positive and negative gate voltages depends on the tunneling barrier height for electrons and holes, respectively, which can be calculated using the Fowler–Nordheim (FN) tunneling mechanism. Moreover, the presence of near-interface traps (NITs) affects the barrier height for holes under negative gate voltages. The behavior of ${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$ shift and ${\mathrm{I}}_{\mathrm{g}\mathrm{s}\mathrm{s}}$ under high-temperature gate bias reflects the charge trapping occurring in different regions of the gate oxide. In addition, compared to SiC planar MOSFETs, SiC trench MOSFETs with thicker gate oxide tend to exhibit higher lifetimes in TDDB tests. Full article