Search Results (82)

Existing databases supporting Online Transaction Processing (OLTP) workloads based on non-volatile memory (NVM) almost all use Multi-Version Concurrency Control (MVCC) protocol to ensure data consistency. MVCC allows multiple transactions to execute concurrently without lock conflicts, reducing the wait time between read and write operations, and thereby significantly increasing the throughput of NVM OLTP engines. However, it requires garbage collection (GC) to clean up the obsolete tuple versions to prevent storage overflow, which consumes additional system resources. Furthermore, existing GC approaches in NVM OLTP engines are inefficient because they are based on methods designed for dynamic random access memory (DRAM) OLTP engines, without considering the significant differences in read/write bandwidth and cache line size between NVM and DRAM. These approaches either involve excessive random NVM access (traversing tuple versions) or lead to too many additional NVM write operations, both of which degrade the performance and durability of NVM. In this paper, we propose TB-Collect, a high-performance GC approach specifically designed for NVM OLTP engines. On the one hand, TB-Collect separates tuple headers and contents, storing data in an append-only manner, which greatly reduces NVM writes. On the other hand, TB-Collect performs GC at the block level, eliminating the need to traverse tuple versions and improving the utilization of reclaimed space. We have implemented TB-Collect on DBx1000 and MySQL. Experimental results show that TB-Collect achieves 1.15 to 1.58 times the throughput of existing methods when running TPCC and YCSB workloads. Full article

Modern computer applications have become highly data-intensive, giving rise to an increase in data traffic between the processor and memory units. Computing-in-Memory (CiM) has shown great promise as a solution to this aptly named von Neumann bottleneck problem by enabling computation within the memory unit and thus reducing data traffic. Many simulation tools in the literature have been proposed to enable the design space exploration (DSE) of these novel computer architectures as researchers are in need of these tools to test their designs prior to fabrication. This paper presents a collection of classical nonvolatile memory (NVM) and CiM simulation tools to showcase their capabilities, as presented in their respective analyses. We provide an in-depth overview of DSE, emerging NVM device technologies, and popular CiM architectures. We organize the simulation tools by design-level scopes with respect to their focus on the devices, circuits, architectures, systems/algorithms, and applications they support. We conclude this work by identifying the gaps within the simulation space. Full article

Summer green tea often suffers from an inferior flavor, attributed to its bitterness and astringency. In this study, an integrated shaking and piling process was performed to improve the flavor of summer green tea. The results demonstrated a significant improvement in the sweet and kokumi flavors, accompanied by a reduction in umami, astringency, and bitterness following the treatment. Additionally, the yellowness and color saturation were also enhanced by the treatment. A total of 146 non-volatile metabolites (NVMs) were identified during the study. The elevated levels of sweet-tasting amino acids (L-proline, L-glutamine, and L-threonine), soluble sugars, and peptides (such as gamma-Glu-Gln and glutathione) contributed to the enhanced sweetness and kokumi. Conversely, the decreased levels of ester-catechins, flavonoid glycosides, and procyanidins resulted in a reduction in umami, astringency, and bitterness. Furthermore, the decreased levels of certain NVMs, particularly ascorbic acid and saponarin, played a crucial role in enhancing the yellowness and color saturation of the summer green tea. Our findings offered a novel theoretical framework and practical guidelines for producing high-quality summer green tea. Full article

With the increasing challenges facing silicon complementary metal oxide semiconductor (CMOS) technology, emerging non-volatile memory (NVM) has received extensive attention in overcoming the bottleneck. NVM and computing-in-memory (CiM) architecture are promising in reducing energy and time consumption in data-intensive computation. The HfO2-doped ferroelectric field-effect transistor (FeFET) is one of NVM and has been used in CiM digital circuit design. However, in the implementation of logical functions, different input forms, such as FeFET state and gate voltage, limit the logic cascade and restrict the rapid development of CiM digital circuits. To address this problem, this paper proposes a Vin–Vout CiM unit circuit with the built-in state of FeFET as a bridge. The proposed unit circuit unifies the form of logic inputs and describes the basic structure of FeFET to realize logic functions under the application of gate-source voltage. Based on the proposed unit circuit, basic logic gates are designed and used to realize CiM Full Adder (FA). The simulation results verify the feasibility of FeFET as the core of logic operations and prove the scalability of FeFET-based unit circuit, which is expected to develop more efficient CiM circuits. Full article

Existing databases supporting Online Transaction Processing (OLTP) workloads based on non-volatile memory (NVM) have not fully leveraged hardware characteristics, resulting in an imbalance between throughput and recovery performance. In this paper, we conclude with the reason why existing designs fail to achieve both: placing indexes on NVM results in numerous random writes and write amplification for index updates, leading to a decrease in system performance. Placing indexes on dynamic random access memory (DRAM) results in much time consumption for rebuilding indexes during recovery. To address this issue, we propose FIR, an NVM OLTP Engine with the fast rebuilding of the DRAM indexes, achieving instant system recovery while maintaining high throughput. Firstly, we design an index checkpoint strategy. During recovery, the indexes are quickly rebuilt by the bottom-up algorithm with index checkpoints. Then, to achieve instant recovery of the entire engine after rebuilding indexes, we optimize the existing log-free design by leveraging time-ordered storage, which significantly reduces the number of NVM writes. We also implement garbage collection based on data redistribution, enhancing system availability. The experimental results demonstrate that FIR achieves 98% of the performance of state-of-the-art OLTP Engine when running TPCC and YCSB. And the recovery speed of FIR is 43.6×–54.5× faster, achieving near-instantaneous recovery. Full article

Huangjinya has recently seen widespread adoption in key tea-producing areas of China, celebrated for its unique varietal traits. Its leaves are also used to produce black tea with distinctive sensory characteristics. The fragrance-enhancing (EF) process is essential in crafting Huangjinya black tea (HJYBT) and is significant in flavor development. However, the impact of EF on non-volatile metabolites (NVMs), volatile metabolites (VMs), and their interactions remains poorly understood. This study aims to investigate how EF temperatures (60 °C, 70 °C, 80 °C, 90 °C, and 110 °C) influence HJYBT flavor transformation. Quantitative descriptive analysis revealed that EF improved the color, aroma, and appearance of tea leaves. Moreover, after an EF temperature of 80 °C, the HJYBT exhibited lower bitterness and astringency, whereas floral, sweet, and fruity aromas became stronger. However, when EF temperatures exceeded 90 °C, a pronounced burnt aroma developed, with HJYBT at 100 °C exhibiting caramel and roasted notes. Partial least squares discriminant analysis indicated that geraniol and linalool contribute to floral and fruity aromas, while 2-ethyl-6-methyl-pyrazine, furfural, and myrcene are key volatiles for caramel and roast aromas. Heptanal, methyl salicylate, α-citral, 1-hexanol, and (E)-3-hexen-1-ol were found to modify the green and grassy odor. Overall, HJYBT treated at 80 °C EF exhibited the highest umami, sweetness, floral and fruity aromas, and overall taste, exhibiting the least astringency, bitterness, and green and grassy notes. These results provide a significant theoretical basis for enhancing HJYBT quality and selecting the optimal EF method. Full article

The rapid advancement of artificial intelligence (AI) technology, combined with the widespread proliferation of Internet of Things (IoT) devices, has significantly expanded the scope of AI applications, from data centers to edge devices. Running AI applications on edge devices requires a careful balance between data processing performance and energy efficiency. This challenge becomes even more critical when the computational load of applications dynamically changes over time, making it difficult to maintain optimal performance and energy efficiency simultaneously. To address these challenges, we propose a novel processing-in-memory (PIM) technology that dynamically optimizes performance and power consumption in response to real-time workload variations in AI applications. Our proposed solution consists of a new PIM architecture and an operational algorithm designed to maximize its effectiveness. The PIM architecture follows a well-established structure known for effectively handling data-centric tasks in AI applications. However, unlike conventional designs, it features a heterogeneous configuration of high-performance PIM (HP-PIM) modules and low-power PIM (LP-PIM) modules. This enables the system to dynamically adjust data processing based on varying computational load, optimizing energy efficiency according to the application’s workload demands. In addition, we present a data placement optimization algorithm to fully leverage the potential of the heterogeneous PIM architecture. This algorithm predicts changes in application workloads and optimally allocates data to the HP-PIM and LP-PIM modules, improving energy efficiency. To validate and evaluate the proposed technology, we implemented the PIM architecture and developed an embedded processor that integrates this architecture. We performed FPGA prototyping of the processor, and functional verification was successfully completed. Experimental results from running applications with varying workload demands on the prototype PIM processor demonstrate that the proposed technology achieves up to 29.54% energy savings. Full article

Quality of service (QoS) has evolved to ensure performance across various computing environments, focusing on data bandwidth, response time, throughput, and stability. Traditional QoS schemes primarily target DRAM-based homogeneous memory systems, exposing limitations when applied to diverse memory configurations. Moreover, the emergence of nonvolatile memories (NVMs) has made achieving QoS even more challenging due to their differing characteristics. While QoS schemes have been proposed for DRAM-based memory systems or hybrid memory systems combining DRAM and a single NVM type, there is a lack of research on QoS techniques for memory systems that incorporate multiple types of NVM simultaneously. Ensuring QoS in these heterogeneous memory environments is challenging due to significant differences in memory characteristics. In this paper, we propose a novel technique, dynamic affinity-based resource pairing (DARP), designed to enhance QoS in multicore heterogeneous memory systems. The proposed approach dynamically monitors the memory access patterns of applications and leverages the specific read/write characteristics of NVM devices. Detailed information from monitoring is used to optimally allocate memory data to the most suitable memory devices, ensuring stable memory response times and mitigating bottlenecks. Extensive experiments validate the efficiency and scalability of DARP across various workloads and heterogeneous memory configurations, including memory systems with multiple types of NVM. The results show that our technique significantly outperforms state-of-the-art QoS methods in terms of memory response time consistency and overall QoS in heterogeneous memory environments. DARP achieved a memory response time variability of 74.4% in six different memory configurations compared to the baseline on average, demonstrating its high scalability and effectiveness in enhancing QoS across various heterogeneous memory systems. Full article

The present research emphasizes fabrication alongside the assessment of an innovative nano-vesicular membranous system known as invasomes (NVMs) laden with Mirtazapine for rectal administration. This system could circumvent the confines of orally administered counterparts regarding dose schedules and bioavailability. Mirtazapine invasomes were tailored by amalgamating phospholipid, cineole, and ethanol through a thin-film hydration approach rooted in the Box–Behnken layout. Optimization of composition parameters used to fabricate desired NVMs’ physicochemical attributes was undertaken using the Design-Expert^® program. The optimal MRZ-NVMs were subsequently transformed to a pH-triggered in situ rectal gel followed by animal pharmacodynamic and pharmacokinetic investigations relative to rectal plain gel and oral suspension. The optimized NVMs revealed a diameter size of 201.3 nm, a z potential of −28.8 mV, an entrapment efficiency of 81.45%, a cumulative release within 12 h of 67.29%, and a cumulative daily permeated quantity of 468.68 µg/cm². Compared to the oral suspension, pharmacokinetic studies revealed a 2.85- and 4.45-fold increase in calculated rectal bioavailability in circulation and brain, respectively. Pharmacodynamic and immunohistopathology evaluations exposed superior MRZ-NVMs attributed to the orally administered drug. Consequently, rectal MRZ-NVMs can potentially be regarded as a prospective nanoplatform with valuable pharmacokinetics and tolerability assets. Full article

We explore security aspects of a new computing paradigm that combines novel memristors and traditional Complimentary Metal Oxide Semiconductor (CMOS) to construct a highly efficient analog and/or digital fabric that is especially well-suited to Machine Learning (ML) inference processors for Radio Frequency (RF) signals. Analog and/or hybrid hardware designed for such application areas follows different constraints from that of traditional CMOS. This paradigm shift allows for enhanced capabilities but also introduces novel attack surfaces. Memristors have different properties than traditional CMOS which can potentially be exploited by attackers. In addition, the mixed signal approximate computing model has different vulnerabilities than traditional digital implementations. However both the memristor and the ML computation can be leveraged to create security mechanisms and countermeasures ranging from lightweight cryptography, identifiers (e.g., Physically Unclonable Functions (PUFs), fingerprints, and watermarks), entropy sources, hardware obfuscation and leakage/attack detection methods. Three different threat models are proposed: (1) Supply Chain, (2) Physical Attacks, and (3) Remote Attacks. For each threat model, potential vulnerabilities and defenses are identified. This survey reviews a variety of recent work from the hardware and ML security literature and proposes open problems for both attack and defense. The survey emphasizes the growing area of RF signal analysis and identification in terms of commercial space, as well as military applications and threat models. We differ from other recent surveys that target ML, in general, neglecting RF applications. Full article

The rapid advancement of technology, alongside state-of-the-art techniques is at an all-time high. However, this unprecedented growth of technological prowess also brings forth potential threats, as oftentimes the security encompassing these technologies is imperfect. Particularly within the automobile industry, the recent strides in technology have brought about increased complexity. A notable flaw lies in the CAN-FD protocol, which lacks robust security measures, making it vulnerable to data theft, injection, replay, and flood data attacks. With the rising complexity of in-vehicular networks and the widespread adoption of CAN-FD, the imperative to safeguard the protocol has never been more crucial. This paper aims to provide a comprehensive review of the existing in-vehicle communication protocol, CAN-FD. It explores existing security approaches designed to fortify CAN-FD, demonstrating multiple multi-layer solutions that leverage modern techniques including Physical Unclonable Function (PUF), Elliptical Curve Cryptography (ECC), Ethereum Blockchain, and Smart contracts. The paper highlights existing multi-layer security measures that offer minimal overhead, optimal performance, and robust security. Moreover, it identifies areas where these security measures fall short and discusses ongoing research along with suggestions for implementing software and hardware-level modifications. These proposed changes aim to streamline complexity, reduce overhead while ensuring forward compatibility. In essence, the methods outlined in this study are poised to excel in real-world applications, offering robust protection for the evolving landscape of in-vehicular communication systems. Full article

Non-volatile memory based on thin-film transistor is crucial for system-on-panel and flexible electronic systems. Achieving high-performance and reliable thin-film transistor (TFT) memory still remains challenging. Here, for the first time, we present a ZnO TFT memory utilizing self-assembled Au nanocrystals with a low thermal budget, exhibiting excellent memory performance, including a program/erase window of 9.8 V, 29% charge loss extrapolated to 10 years, and remarkable endurance characteristics. Moreover, the memory exhibits favorable on-state characteristics with mobility, subthreshold swing, and current on–off ratio of 17.6 cm²V⁻¹s⁻¹, 0.71 V/dec, and 10⁷, respectively. Our study shows that the fabricated TFT memory has great potential for practical applications. Full article

In the era of widespread edge computing, energy conservation modes like complete power shutdown are crucial for battery-powered devices, but they risk data loss in volatile memory. Energy autonomous systems, relying on ambient energy, face operational challenges due to power losses. Recent advancements in emerging nonvolatile memories (NVMs) like FRAM, RRAM, MRAM, and PCM offer mature solutions to sustain work progress with minimal energy overhead during outages. This paper thoroughly reviews utilizing emerging NVMs in microcontroller units (MCUs), comparing their key attributes to describe unique benefits and potential applications. Furthermore, we discuss the intricate details of NVM circuit design and NVM-driven compute-in-memory (CIM) architectures. In summary, integrating emerging NVMs into MCUs showcases promising prospects for next-generation applications such as Internet of Things and neural networks. Full article

To analyze the induced electric field characteristics generated by the rotation and shaking of underwater metal vehicles, a mathematical model of the induced electric field generated by the underwater metal vehicles was derived using Faraday’s electromagnetic induction law. A mathematical model of the induced electric field on the electrode pairs of metal vehicles shaking in different coordinate system planes was established through in-depth analysis. Based on this, a three-component output model of the induced electric field output by the three-axis sensor was obtained when the measurement system was shaking at all three angles. At a constant speed, the induced electric field interference output by the measurement system is a static signal. The value of the static electric field is proportional to the vehicle’s speed and the value of the geomagnetic field, and the value of each component is related to the direction of movement and the value of the geomagnetic field component. The simulation results show that when the navigation body is moving at a constant speed, the induced electric field is a static electric field with a magnitude of mV/m. In a stable state, the induced electric field noise generated by changes in pitch, roll, and heading sway is at the nV/m level and does not have a significant impact on detection. The correctness of the theoretical model has been verified through experiments on offshore speedboat platforms, and it is feasible to use metal navigation bodies for ship electric field detection. Full article

Neuromorphic computing offers a promising solution to overcome the von Neumann bottleneck, where the separation between the memory and the processor poses increasing limitations of latency and power consumption. For this purpose, a device with analog switching for weight update is necessary to implement neuromorphic applications. In the diversity of emerging devices postulated as synaptic elements in neural networks, RRAM emerges as a standout candidate for its ability to tune its resistance. The learning accuracy of a neural network is directly related to the linearity and symmetry of the weight update behavior of the synaptic element. However, it is challenging to obtain such a linear and symmetrical behavior with RRAM devices. Thus, extensive research is currently devoted at different levels, from material to device engineering, to improve the linearity and symmetry of the conductance update of RRAM devices. In this work, the experimental results based on different programming pulse conditions of RRAM devices are presented, considering both voltage and current pulses. Their suitability for application as analog RRAM-based synaptic devices for neuromorphic computing is analyzed by computing an asymmetric nonlinearity factor. Full article