Search Results (37)

We present an analytic compact model for p-type cylindrical gate-all-around (GAA) MOSFETs in the quasi-ballistic/ballistic regime, incorporating drain-induced barrier lowering (DIBL). To describe the potential profile, an undetermined parameter is used to represent the channel potential, which is derived from the Laplace equation in the subthreshold region and from Gauss’s law combined with quantum statistics in the inversion region. A smoothing function is applied to this parameter to ensure a continuous source—drain current across all operating regions. The current model is based on the Landauer approach and captures both quasi-ballistic/ballistic transport and quantum-confinement effects. It is validated against non-equilibrium Green’s function (NEGF) simulation results and implemented in Verilog-A for SPICE circuit-level simulation of a CMOS inverter, demonstrating its applicability for nanoscale design. Full article

This paper presents a low-power CMOS voltage reference with low supply sensitivity, designed and verified in a 180 nm standard CMOS technology. A DIBL-based line-sensitivity (LS) compensation path is incorporated into the conventional PTAT generation circuit to simultaneously provide a reference voltage and a bias current with improved LS. The proposed circuit achieves LS values of 0.01%/V for the voltage reference and 0.07%/V for the bias current reference over a supply voltage range of 1.4 V to 2 V. It generates a reference voltage of 538 mV and a PTAT current of 38 nA, consuming 68 nW. The simulated temperature coefficient is 58 ppm/$℃$ from −40 °C to 130 °C, and the power supply rejection ratio is −59 dB at 100 Hz. Full article

This study conducts a comprehensive examination of a GaN channel-based nanobiosensor featuring a dielectrically modulated trigate FinFET structure, incorporating both uniform and Gaussian channel doping. The proposed device incorporates a nanocavity structure situated beneath the gate region, intended for the analysis of diverse biomolecules in biosensing applications. The proposed biosensor employs HfO₂ as the gate dielectric, characterized by a dielectric constant of 25, leading to an enhanced switching ratio for the device. This study examines the electrical properties relevant to biomolecule identification, including the switching ratio, DIBL, threshold swing, threshold voltage, and transconductance. The sensitivity of these properties concerning the drain current is subsequently assessed. Enhanced sensitivity increases the likelihood of detecting biomolecules. The electrical property of a biomolecule is examined in the absence of another biomolecule within the cavity. The apparatus is designed to detect neutral biomolecules. Simultaneously, further investigational research has been undertaken regarding the linearity behavior of GAA FET, nanobiosensors, and dielectrically modulated TGFinFET. This study’s results have been compared with those of GaN-based FinFET and GaN SOI FinFET technologies. The data indicates approximately ∼103% and ∼42% improvements in I_OFF and Switching ratio, respectively, when compared to IRDS 2025. The nanobiosensor (GAA FET) demonstrates enhanced linear performance concerning higher-order voltage and current intercept points, including VIP2, VIP3, IIP3, and P1dB. Full article

This study examines the performance of a GaN HEMT with a 150 nm gate length, fabricated on silicon carbide, across various operational modes, including direct current (DC), radio frequency (RF), and small-signal parameters. The evaluation of DC, RF, and small-signal performance under diverse bias conditions remains a relatively unexplored area of study for this specific technology. The DC characteristics revealed relatively little I_ds at zero gate and drain voltages, and the current grew as V_gs increased. Essential measurements include I_dss at 109 mA and I_dssm at 26 mA, while the peak g_m was 62 mS. Because transconductance is sensitive to variations in V_gs and V_ds, it shows “Vth _roll-off,” where Vth decreases as V_ds increases. The transfer characteristics corroborated this trend, illustrating the impact of drain-induced barrier lowering (DIBL) on threshold voltage (Vth) values, which spanned from −5.06 V to −5.71 V across varying drain-source voltages (V_ds). The equivalent-circuit technique revealed substantial non-linear behaviors in capacitances such as C_gs and C_gd concerning V_gs and V_ds, while also identifying extrinsic factors including parasitic capacitances and resistances. Series resistances (R_gs and R_gd) decreased as V_gs increased, thereby enhancing device conductivity. As V_gs approached neutrality, particularly at elevated V_ds levels, the intrinsic transconductance (g_mo) and time constants (τ_gm, τ_gs, and τ_gd) exhibited enhanced performance. f_t and f_max, which are essential for high-frequency applications, rose with decreasing V_gs and increasing V_ds. When V_gs approached −3 V, the S₂₁ and Y₂₁ readings demonstrated improved signal transmission, with peak S₂₁ values of approximately 11.2 dB. The stability factor (K), which increased with V_ds, highlighted the device’s operational limits. The robust correlation between simulation and experimental data validated the equivalent-circuit model, which is essential for enhancing design and creating RF circuits. Further examination of bias conditions would enhance understanding of the device’s performance. Full article

As transistor dimensions continue to scale below 10 nm, traditional MOSFET architectures face increasing limitations from short-channel effects, gate leakage, and variability. FinFETs, especially junctionless FinFETs on silicon-on-insulator (SOI) substrates, offer improved electrostatic control and simplified fabrication, making them attractive for deeply scaled nodes. In this work, we propose a novel Stepped-Spacer Structured FinFET (S³-FinFET) that incorporates a three-layer HfO₂/Si₃N₄/HfO₂ spacer configuration designed to enhance electrostatics and suppress parasitic effects. Using 2D TCAD simulations, the S³-FinFET is evaluated in terms of key performance metrics, including transfer/output characteristics, ON/OFF current ratio, subthreshold swing (SS), drain-induced barrier lowering (DIBL), gate capacitance, and cut-off frequency. The results show significant improvements in leakage control and high-frequency behavior. These enhancements make the S³-FinFET particularly well-suited for Field-Programmable Gate Arrays (FPGAs), where power efficiency, speed, and signal integrity are critical to performance in reconfigurable logic environments. Full article

In the context of increasing digitalization and the emergence of applications such as smart cities, embedded devices are becoming ever more pervasive, mobile, and ubiquitous. Due to increasing concerns around energy efficiency, gate density, and scalability in the semiconductor industry, there has been much interest recently in the fabrication of viable low-power energy-efficient devices. The Hetero-Dielectric Gate-All-Around (HD-GAA) MOSFET represents a cutting-edge transistor architecture designed for superior sustainability and energy efficiency, improving the overall efficiency of the system by reducing leakage and enhancing gate control; therefore, as part of the transition to a sustainable future, several semiconductor industries, including Intel, Samsung, Texas Instruments, and IBM, are using this technology. In this study, Hetero-Dielectric Single-Metal Gate-All-Around MOSFET (HD-SM-GAA MOSFET) devices and circuits were designed using Schottky source/drain contacts and tunable high-k dielectric Hf_xTi_1−xO₂ in the TCAD simulator using the following specifications: N-Channel HD-SM-GAA MOSFET (‘Device-I’) with a 5 nm radius and a 21 nm channel length alongside two P-Channel HD-SM-GAA MOSFETs (‘Device-II’ and ‘Device-III’) with radii of 5 nm and 8 nm, respectively, maintaining the same channel length. Thereafter, the inverters were implemented using these devices in the COGENDA TCAD simulator. The results demonstrated significant reductions in short-channel effects: subthreshold swing (SS) (‘Device-I’ = 61.5 mV/dec, ‘Device-II’ = 61.8 mV/dec) and drain-induced barrier lowering (DIBL) (‘Device-I’ = 8.2 mV/V, ‘Device-II’ = 8.0 mV/V) in comparison to the existing literature. Furthermore, the optimized inverters demonstrated significant improvements in noise margin values such as Noise Margin High (NM_H) and Noise Margin Low (NM_L), with Inverter-1 showing 38% and 44% enhancements and Inverter-2 showing 40% and 37% enhancements, respectively, compared to the existing literature. The results achieved illustrate the potential of using this technology (e.g., for power inverters) in embedded power control applications where energy efficiency and scalability are important, such as sustainable smart cities. Full article

In this work, a cylindrical gate-all-around junctionless field effect transistor (JLFET) was investigated. Junctions and doping concentration gradients are unavailable in JLFET. According to the results, the suggested device has a novel architecture that significantly enhances transistor performance while exhibiting a decreased vulnerability to short-channel effects (SCEs). The Atlas 3D device simulator has been used to analyze the proposed JLFET’s performance, especially for low-power applications for different channel lengths ranging from 10 nm to 60 nm with Al_0.30Ga_0.60As as III-V materials. The comparative simulated study has been based on various performance parameters, including subthreshold slope (SS), drain-induced barrier lowering (DIBL), transconductance, threshold voltage, and I_ON to I_OFF ratio. The results of the simulations demonstrated that the III-V JLFET exhibited a favorable SS and decreased DIBL compared to other circuit topologies. In the suggested study, gallium arsenide (GaAs) and its compound materials have demonstrated a strong correlation between the SS and DIBL values. The SS is approximately 63 mV/dec, extremely near the ideal 60 mV/dec value. Gallium arsenide (GaAs) and aluminum gallium arsenide (AlGaAs) exhibit DIBL of approximately 30 mV/V and an SS value of around 64 mV/dec. Full article

In this article, a novel double-trench SiC MOSFET with an integrated MOS-channel diode (MCD) is proposed and analyzed through TCAD simulations. The MCD incorporates a short channel, where the channel length can be adjusted by modifying the recess depth. Owing to the drain-induced barrier-lowering (DIBL) effect, a low potential barrier is created for electrons flowing from the JFET region to the N+ source region. This effectively eliminates the bipolar degradation of the parasitic body p-i-n diode and reduces the cut-in voltage $V_{\mathrm{on}}$ by 69.2%. Additionally, the breakdown voltage (BV) remains nearly unchanged. The reduction in the p-well region alleviates the JFET effect, successfully lowering the specific on-resistance $R_{\mathrm{on},\mathrm{sp}}$, making the channel easier to turn on, and reducing the threshold voltage ($V_{\mathrm{th}}$). However, the increase in the gate charge $Q_{\mathrm{g}}$ results in a slight rise in the switching loss. Full article

The continuous scaling down of MOSFETs is one of the present trends in semiconductor devices to increase device performance. Nevertheless, with scaling down beyond 22 nm technology, the performance of even the newer nanodevices with multi-gate architecture declines with an increase in short channel effects (SCEs). Consequently, to facilitate further increases in the drain current, the use of strained silicon technology provides a better solution. Thus, the development of a novel Gate-All-Around Field-Effect Transistor (GAAFET) incorporating a strained silicon channel with a 10 nm gate length is initiated and discussed. In this device, strain is incorporated in the channel, where a strained silicon germanium layer is wedged between two strained silicon layers. The GAAFET device has four gates that surround the channel to provide improved control of the gate over the strained channel region and also reduce the short channel effects in the devices. The electrical properties, such as the on current, off current, threshold voltage (V_TH), subthreshold slope, drain-induced barrier lowering (DIBL), and I_on/I_off current ratio, of the 10 nm channel length GAAFET are compared with the 22 nm strained silicon channel GAAFET, the existing SOI FinFET device on 10 nm gate length, and IRDS 2022 specifications device. The developed 10 nm channel length GAAFET, having an ultrathin strained silicon channel, delivers enriched device performance, being augmented in contrast to the IRDS 2022 specifications device, showing improved characteristics along with amended SCEs. Full article

In robotic arm controllers, the ability to shift signal levels is crucial for interfacing between different voltage domains in a processor. The level shifter (LS) has been used to convert signals operating near threshold voltage to signals operating well above the threshold voltage. Researchers have developed current mirror-based LSs to employ current mirrors, which duplicate the current from one transistor and accurately replicate it in another, ensuring precise current matching. In this research, a dynamic inverter-based level shifter (DIBLS) with an error correction circuit is implemented. One of the main issues addressed by DIBLS is the problem of current disagreement. Current disagreement arises when multiple circuit components attempt to draw current from a common source, which leads to operational problems. Furthermore, DIBLS includes a feedback inverter controlled by the output node; this feedback inverter likely plays a pivotal role in controlling and stabilizing the output voltage of operation of the LS. The results demonstrate that DIBLS offers notable advantages on increased operational speed. This speed improvement has been achieved by circumventing the threshold voltage drop associated with the feedback of the inverter and by ensuring complete output swing, addressing stability issues. Voltage shifting between 0.3 V and 1.2 V at 1 MHz having power consumption is 16.57 nW, delay 0.22 ns, and energy per transition 32.25 fJ. The entire process is executed in 45 nm in CMOS technology. Full article

In this work, we present the novel application of SiN_x stress-engineering techniques for the suppression of short-channel effects in AlGaN/GaN high-electron-mobility transistors (HEMTs), accompanied by a comprehensive analysis of the underlying mechanisms. The compressive stress SiN_x passivation significantly enhances the barrier height at the heterojunction beneath the gate, maintaining it above the quasi-Fermi level even as V_ds rises to 20 V. As a result, in GaN devices with a gate length of 160 nm, the devices with compressive stress SiN_x passivation exhibit significantly lower drain-induced barrier lowering (DIBL) factors of 2.25 mV/V, 2.56 mV/V, 4.71 mV/V, and 3.84 mV/V corresponding to drain bias voltages of 5 V, 10 V, 15 V, and 20 V, respectively. Furthermore, as V_ds increases, there is an insignificant degradation in transconductance, subthreshold swing, leakage current, or output conductance. In contrast, the devices with stress-free passivation show relatively higher DIBL factors (greater than 20 mV/V) and substantial degradation in pinch-off performance and output characteristics. These results demonstrate that the SiN_x stress-engineering technique is an attractive technique to facilitate high-performance and high-reliability GaN-based HEMTs for radio frequency (RF) electronics applications. Full article

The scaling of bulk Si-based transistors has reached its limits, while novel architectures such as FinFETs and GAAFETs face challenges in sub-10 nm nodes due to complex fabrication processes and severe drain-induced barrier lowering (DIBL) effects. An effective strategy to avoid short-channel effects (SCEs) is the integration of low-dimensional materials into novel device architectures, leveraging the coupling between multiple gates to achieve efficient electrostatic control of the channel. We employed TCAD simulations to model multi-gate FETs based on various dimensional systems and comprehensively investigated electric fields, potentials, current densities, and electron densities within the devices. Through continuous parameter scaling and extracting the sub-threshold swing (SS) and DIBL from the electrical outputs, we offered optimal MoS₂ layer numbers and single-walled carbon nanotube (SWCNT) diameters, as well as designed structures for multi-gate FETs based on monolayer MoS₂, identifying dual-gate transistors as suitable for high-speed switching applications. Comparing the switching performance of two device types at the same node revealed CNT’s advantages as a channel material in mitigating SCEs at sub-3 nm nodes. We validated the performance enhancement of 2D materials in the novel device architecture and reduced the complexity of the related experimental processes. Consequently, our research provides crucial insights for designing next-generation high-performance transistors based on low-dimensional materials at the scaling limit. Full article

This paper introduces an MOS-based intelligent temperature sensor with a linear readout. Compared with similar designs, the proposed sensor utilizes the DIBL effect to reduce the precision requirement for the voltage reference source and compensate for the temperature measurement range. A compact voltage reference circuit is introduced, which generates two reference voltage bases using only three transistors. In addition, the proposed digital readout circuit does not require a subtractor or a divider, further saving area. Fabricated in a 55 nm CMOS process, the proposed sensor occupies a compact area of 3216 $\mathsf{\mu }{\mathrm{m}}^2$. Post-simulation results show it has a maximum error of −0.52/+0.28 °C within the temperature range of −20 °C to 120 °C after two-point calibration. The power supply voltage range of the sensor is 0.8 to 1.8 V. It has a maximum voltage sensitivity of 5.7 °C/V and its power consumption is only 166 nW, with a power supply voltage of 0.8 V. Full article

Leakage diodes cause deviations in the thermal drift of ultra-low-power two-transistor (2T) reference circuits, resulting in either convex or concave output voltages against temperature, depending on the reference transistor types (n-type/p-type). This paper investigates the combined application of the convexity and concavity properties exhibited by the output voltage of complementary 2T references, one n-type and one p-type. By exploiting the body bias effect, this approach mitigates variations in the output reference voltage caused by temperature fluctuations. Software optimization is also used to obtain the required aspect ratios after formulating the required criteria for drain-induced barrier lowering (DIBL) elimination in the first stage. The performance of the proposed reference is evaluated by post-layout Monte Carlo simulations. In the range of 0 °C to 100 °C, the output reference voltage has an average temperature coefficient (TC) of 26.7 ppm/°C without any temperature trim. The output reference voltage is 195.5 mV with a standard deviation of 13.6 mV. The line sensitivity (LS) is 17.1 ppm/V in the supply voltage range of 0.5 V to 2.1 V at 25 °C. At 25 °C and 0.5 V, the power consumption is 28.8 pW, increasing to a maximum of 1.3 nW at 100 °C and 2.1 V. Full article

To study the morphological differences between and the evolutionary mechanisms driving the differentiation of geographically distinct populations of Gymnodiptychus dybowskii, 158 fish were collected from the Turks River and the Manas River in Xinjiang from 2020 to 2021 with the approval of the Academic Ethics Committee. The morphological characteristics of the fish were assessed using classical fish ecology methods such as traditional morphometric measurements and the framework approach. The results showed that the morphological characteristics of the populations in the Turks River and Manas River were significantly different; a one-way ANOVA revealed 22 highly significant differences (p < 0.01) and 1 significant difference (p < 0.05) among the 33 morphological traits of the observed populations, and a principal component analysis revealed that there was no overlap between the two populations of G. dybowskii. The main characteristics associated with principle component 1 were the terminus of the dorsal fin to the ventral origin of the caudal fin (D—F), the dorsal origin of the caudal fin to the origin of the anal fin (E—H), and the insertion of the pectoral fin to the terminus of the pectoral fin (J—K); the main factors associated with principal component 2 were the body height (BD), the terminus of the dorsal fin to the insertion of the pelvic fin (D—I), the caudal peduncle height (CPH), and the tip of the snout to the last end of the frontal maxilla (A—B); and the main traits associated with principle component 3 were the terminus of the anal fin to the origin of the anal fin (G—H), the body width (BW), the insertion of the pelvic fin to the terminus of the pelvic (I—L), the insertion of the pectoral fin to the terminus of the pectoral fin (J—K), and the insertion of the pelvic fin to the insertion of the pectoral fin (I—J). An OPLS-DA revealed that the two populations could be wholly separated and that the intergroup growth traits of the Manas River population were different and significantly greater than those of the Turks River population. The discriminant functions of the Turks River and Manas River populations of G. dybowskii were as follows: Y_T = −432.033 + 1787.748X₁ + 826.517X₂ + 249.002X₃ + 1183.050X₄ + 554.934X₅ + 999.296X₆ + 627.428X₇; Y_M = −569.819 + 2041.044X₁ + 344.942X₂ + 333.737X₃ + 940.512X₄ + 348.222X₅ + 1167.770X₆ + 1015.904X₇. According to a coefficient of variation analysis, a total of nine traits, namely, EI/BL, C-D/BL, E-F/BL, F-H/BL, H-I/BL, C-J/BL, D-I/BL, D-H/BL, and D-F/BL, had a CD > 1.28, indicating that the differences in these nine traits had reached the subspecies level. The results showed that G. dybowskii significantly differed between the two geographically distinct populations in the Turks River and the Manas River and have differentiated to the subspecies level. This study provides a basis for a better investigation of the population structure of highland endemic fishes and the mechanisms by which they diverged and lays a foundation for developing and utilizing germplasm resources from endemic fishes in Xinjiang. Full article