Search Results (54)

This article presents a low-noise amplifier (LNA) with high image rejection ratio (IRR) operating in the 5G millimeter-wave band using a 65 nm CMOS process. The circuit adopts an inter-stage notch filtering structure composed of a transformer and a switched capacitor array to achieve image suppression and impedance matching with no die area overhead. By adjusting the values of the switch capacitor array, the transmission zeros are positioned in the stopband while the poles are placed in the passband, thereby realizing image rejection. Furthermore, the number and distribution of poles under the both real and complex impedance conditions are analyzed. Moreover, the quality factor (Q) of the zero is derived to establish the relationship between Q and the image rejection ratio, guiding the optimization of both gain and IRR of the circuit design. Measurement results demonstrate that the LNA exhibits a gain of 18 dB and a noise figure (NF) of 4.4 dB at 40 GHz, with a corresponding IRR of 53.4 dB when the intermediate frequency (IF) is 6 GHz. The circuit demonstrates a 3 dB bandwidth from 36.3 to 40.7 GHz, with an IRR greater than 42 dB across this frequency range. The power consumption is 25.4 mW from a 1 V supply, and the pad-excluded core area of the entire chip is 0.13 mm². Full article

The global allocation of over 5 GHz of spectral bandwidth around the 60 GHz frequency band offers significant potential for ultra-high data rate wireless communication over short distances and enables the implementation of high-resolution frequency-modulated continuous-wave (FMCW) radar applications. In this study, a Front-End Receiver covering frequencies from 57 to 64 GHz was designed and characterized in a 40 nm CMOS process. The proposed architecture includes a Low-Noise Amplifier (LNA), a novel double-balanced mixer offering variable conversion gain, and a low-power class-C Voltage-Controlled Oscillator (VCO). From post-layout simulation results, the LNA presents a noise figure (NF) less than 4.8 dB and a gain more than 19 dB, while the input compression point (P1dB) reaches −15.6 dBm. The double-balanced mixer delivers a noise figure of less than 11 dB, a conversion gain of 14 dB, and an input-referred compression point of −13 dBm. The VCO achieves a phase noise of approximately −93 dBc/Hz at 1 MHz offset from 60 GHz and a tuning range of about 8 GHz, dissipating only 6.6 mW. Overall, the receiver demonstrates a maximum conversion gain of more than 39 dB, a noise figure of less than 9.2 dB, an input- referred compression point of −37 dBm, and a power dissipation of 56 mW. Full article

This paper presents a fully integrated bandpass filter (BPF) with high tunability based on a novel differential active inductor (DAI), designed for sensor interface circuits operating in the ultra-high frequency (UHF) band. The design of the proposed DAI is based on a symmetrical configuration, utilizing a differential amplifier for the feedforward transconductance and a common-source (CS) transistor for the feedback transconductance. By integrating a cascode scheme with a feedback resistor, the quality factor of the active inductor is significantly improved, leading to enhanced mid-band gain for the bandpass filter. To facilitate independent tuning of the BPF‘s center frequency and mid-band gain, an active resistor adjustment and bias voltage control are employed, providing precise control over the filter’s operational parameters. Post-layout simulations and process corner results are conducted with 0.13 µm CMOS technology at 1.2 V supply voltage. The proposed second order BPF achieves a broad tuning range of 280 MHz to 2.426 GHz, with a passband gain between 8.9 dB and 16.54 dB. The design demonstrates a maximum noise figure of 16.54 dB at 280 MHz, an input-referred 1 dB compression point of −3.78 dBm, and a third-order input intercept point (IIP3) of −0.897 dBm. Additionally, the BPF occupies an active area of only 68.2×30 µm², including impedance-matching part, and consumes a DC power of 14–20 mW. The compact size and low power consumption of the design make it highly suitable for integration into modern wireless sensor interfaces where performance and area efficiency are critical. Full article

Neural signal recording demands compact, low-power, high-performance amplifiers, to enable large-scale, multi-channel electrode arrays. This work presents a bioamplifier optimized for action potential detection, designed using TSMC 28 nm HPC CMOS technology. The amplifier integrates an active low-pass filter, eliminating bulky DC-blocking capacitors and significantly reducing the size and power consumption. It achieved a high input impedance of 105.5 GΩ, ensuring minimal signal attenuation. Simulation and measurement results demonstrated a mid-band gain of 58 dB, a −3 dB bandwidth of 7 kHz, and an input-referred noise of 11.1 μ${\mathrm{V}}_{\mathrm{rms}}$, corresponding to a noise efficiency factor (NEF) of 8.4. The design occupies a compact area of 2500 μ$m^2$, making it smaller than previous implementations for similar applications. Additionally, it operates with an ultra-low power consumption of 3.4 μW from a 1.2 V supply, yielding a power efficiency factor (PEF) of 85 and an area efficiency factor of 0.21. These features make the proposed amplifier well suited for multi-site in-skull neural recording systems, addressing critical constraints regarding miniaturization and power efficiency. Full article

In this paper, a novel multiple-input operational transconductance amplifier (MI-OTA) is proposed. The MI-OTA can be obtained by using the multiple-input bulk-driven MOS transistor (MIBD MOST) technique. The circuit structure is simple, can operate with a supply voltage of 0.5 V, and consumes 937 pW at a current setting of 625 pA. The proposed MI-OTA was used to implement a high-order multiple-input voltage-mode universal filter. The proposed filter can provide non-inverting and inverting low-pass, high-pass, band-pass, band-stop, and all-pass transfer functions to the same topology. In addition, it has a high input impedance and does not need any inverted input signals, so there is no additional buffering circuit. The proposed filter can be used for biological signal processing. The proposed MI-OTA and the second-order universal filter were simulated in Cadence using CMOS process parameters of 0.18 μm from TSMC to verify the functionality and performance of the new structures. Full article

This paper presents a multiple-input single-output (MISO) shadow filter implemented using multiple-input differential difference transconductance amplifiers (MI-DDTAs). The MI-DDTA’s multiple inputs are realized through the multiple-input bulk-driven MOS transistor (MI-BD MOST) technique. Leveraging the multiple-input capability of the DDTA, various filter responses—low-pass filter (LPF), high-pass filter (HPF), band-pass filter (BPF), band-stop filter (BSF), and all-pass filter (APF)—can be efficiently achieved by appropriately configuring the input signals. The natural frequency and quality factor of the shadow filter can be independently tuned using external amplifiers. Unlike conventional shadow filters, where adjusting the quality factor or natural frequency impacts the passband gain, this design ensures a constant unity passband gain. The MI-DDTA operates at a supply voltage of 0.5 V and consumes 385.8 nW of power for setting current I_set = 14 nA. The proposed MI-DDTA and shadow filter are designed and validated through simulations in the Cadence design environment, using a 0.18 µm CMOS process provided by TSMC (Taiwan Semiconductor Manufacturing Company Limited). Full article

This paper presents a low-voltage, low-power current differencing transconductance amplifier (CDTA) utilizing the bulk-driven MOS transistor technique in the subthreshold region for reduced voltage and power consumption. The proposed CDTA includes a z-copy terminal, which enhances its functionality in current-mode circuit applications. Designed in the Cadence Virtuoso environment using 0.18 µm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC), the amplifier operates with a supply voltage of 0.45 V and consumes 328 nW of power, with a bias current set to 10 nA. The current bandwidth and offset of the CDTA are 35 kHz and 0.3 nA, respectively. To demonstrate its performance, the CDTA is applied in a current-mode universal filter, which can realize low-pass, band-pass, high-pass, band-stop, and all-pass responses within a single topology. This design eliminates issues related to inverting input signals, input signal matching, or the need for multiple input signals. Additionally, the natural frequency of these filtering functions can be electronically controlled. The low-pass filter achieves a dynamic range of 61 dB, with a total harmonic distortion of 0.8%. Full article

This paper introduces a Ku-band fully differential low-power high-input 1 dB compression point (P1dB) low-noise amplifier (LNA). A fully differential structure is employed to enhance the input P1dB, common-mode noise rejection, and second harmonic cancellation. The first stage adopts large transistors and is optimized for power consumption and noise figure (NF). The output stage is designed with class AB bias, resulting in improved P1dB, power consumption, and linearity. The proposed two-stage fully differential common-source (CS) LNA was implemented using 65 nm bulk complementary metal oxide semiconductor (CMOS) technology. The fabricated LNA achieved a minimum NF of 2.7 dB at 13.6 GHz. Furthermore, it achieved a maximum gain of 19.92 dB at 12.2 GHz. Additionally, the LNA has an input P1dB of −7.45 dBm and an output power 1 dB compression point (OP1dB) of 10.09 dBm, both measured at 15.6 GHz. The LNA operates with a power consumption of 11 mW at a 1 V supply, and occupies a core size of 0.75 mm × 0.35 mm. Full article

This paper presents a novel low-power low-voltage current differencing transconductance amplifier (CDTA). To achieve a low-voltage low-power CDTA, the BD-MOST (bulk-driven MOS transistor) technique operating in a subthreshold region is used. The proposed CDTA is designed in 0.18 µm CMOS technology, can operate with a supply voltage of 0.5 V, and consumes 1.05 μW of power. The proposed CDTA is used to realize a current-mode universal filter. The filter can realize five standard transfer functions of low-pass, band-pass, high-pass and band-stop, and all-pass from the same circuit. Neither component-matching conditions nor input signals of the inverse type are required to realize these filter functions. The current-mode filter offers low-input and high-output impedance and uses grounded capacitors. The natural frequency and quality factor of the filters can be orthogonally controlled. The proposed CDTA and its applications are simulated using SPICE to confirm the feasibility and functionality of the new circuits. Full article

This paper presents a mixed-mode universal filter using differential difference current conveyor transconductance amplifiers (DDCCTA). Despite using a minimum number of MOS differential pairs, the proposed DDCCTA is a multiple-input, multiple-output device, that was achieved using the multiple-input bulk-driven MOS transistor (MIBD-MOST) technique, multiple-output current followers and transconductance gains. A subthreshold technique is used to achieve minimum power consumption of the DDCCTA. Thanks to the multiple-input and multiple-output of DDCCTA, the mixed-mode universal filter based on the proposed element can realize five standard filter responses, i.e., low-pass, high-pass, band-pass, band-stop, and all-pass responses, of four modes, i.e., voltage-mode, current-mode, transadmittance-mode, and transimpedance-mode, thus providing 194 filter responses from a single circuit. The natural frequency and quality factor of the filter response can be controlled electronically and orthogonally. The proposed DDCCTA and mixed-mode universal filter are simulated and designed using 0.18 μm CMOS technology to confirm the functionality of the new circuit. The mixed-mode universal filter uses ±0.5 V of supply voltage and consumes 0.374 mW of power when operating at a natural frequency of 10 kHz. Full article

This paper presents a single-input multiple-output (SIMO) cascode low-noise amplifier with inductive degeneration for inter- and intra-band carrier aggregation. The proposed low-noise amplifier has two output ports for flexible operation in carrier aggregation combinations for band 30 and band 7. However, during inter- and intra-band operation, gain variation occurs depending on the output mode. To compensate for this, a switching circuit is proposed to adjust the degeneration inductor, optimizing gain performance for both modes. The switching operation can minimize the control for the dynamic range in the receiver system to support carrier aggregation. The designed low-noise amplifier was fabricated using a 65 nm CMOS process, occupying an area of 2.1 mm². In inter-band operation, the small-signal gain was measured by 18.9 dB for band 30 and 18.6 dB for band 7, with the noise figures of 1.03 dB and 1.07 dB, respectively. For intra-band operation, the small-signal gain was 17.3 dB and 17.2 dB, with the noise figures of 1.3 dB and 1.41 dB. The IIP₃ values were measured by −7.6 dBm and −6.7 dBm for inter-band, and −6.3 dBm and −6.2 dBm for intra-band. Power consumption was 8.04 mW and 7.68 mW in inter-band, and 17.04 mW and 17.64 mW in intra-band depending on the output configuration. Full article

This paper presents a compact V-band low-noise amplifier (LNA) featuring temperature compensation, implemented in a 130 nm SiGe BiCMOS process. A negative temperature coefficient bias circuit generates an adaptive current for temperature compensation, enhancing the LNA’s temperature robustness. A T-type inductive network is employed to establish two dominant poles at different frequencies, significantly broadening the amplifier’s bandwidth. Over the wide temperature range of −55 °C to 85 °C, the LNA prototype exhibits a gain variation of less than 1.5 dB at test frequencies from 40 GHz to 65 GHz, corresponding to a temperature coefficient of 0.01 dB/°C. At −55 °C, 25 °C, and 85 °C, the measured peak gains are 25.5 dB, 25 dB, and 24.4 dB, respectively, with minimum noise figures (NF) of 3.0 dB, 3.5 dB, and 4.2 dB, and DC power consumptions of 22.3 mW, 27.6 mW, and 34.4 mW. Moreover, the total silicon area of the LNA chip is 0.37 mm², including all test pads, while the core area is only 0.09 mm². Full article

In this paper, a signal conditioner intended for use in variable impedance sensors is presented. First, an inductive linear displacement sensor design is described, and the signal conditioner discrete realization is presented. Second, based on this system’s requirements, the integrated conditioner is proposed. The conditioner comprises an amplifier, a tunable band-pass filter, and a precision high-frequency AC-DC converter. It is designed in a low-cost AMS 0.35 µm CMOS process. The presented conditioner measures the sensor’s impedance magnitude by using a simplified variation of the sensor voltage and current vector measurement. It can be used for the real-time measurement of fast sensors, having small output impedance. The post-layout simulation results show that the integrated conditioner has an inductance measurement range from 10 nH to 550 nH with a nonlinearity of 1.2%. The operating frequency in this case was 8 MHz, but the circuit can be easily adjusted to different operating frequencies (due to the tunable filter). The designed IC area is 500 × 330 μm², and the total power consumption is 93.8 mW. Full article

This paper presents a new multiple-input single-output voltage-mode universal filter employing four multiple-input operational transconductance amplifiers (MI-OTAs) and three grounded capacitors suitable for low-voltage low-frequency applications. The quality factor (Q) of the filter functions can be tuned by both the capacitance ratio and the transconductance ratio. The multiple inputs of the OTA are realized using the bulk-driven multiple-input MOS transistor technique. The MI-OTA-based filter can also offer many filtering functions without additional circuitry requirements, such as an inverting amplifier to generate an inverted input signal. The proposed filter can simultaneously realize low-pass, high-pass, band-pass, band-stop, and all-pass responses, covering both non-inverting and inverting transfer functions in a single topology. The natural frequency and the quality factors of all the filtering functions can be controlled independently. The natural frequency can also be electronically controlled by tuning the transconductances of the OTAs. The proposed filter uses a 1 V supply voltage, consumes 120 μW of power for a 5 μA setting current, offers 40 dB of dynamic range and has a third intermodulation distortion of −43.6 dB. The performances of the proposed circuit were simulated using a 0.18 μm TSMC CMOS process in the Cadence Virtuoso System Design Platform to confirm the performance of the topology. Full article

This paper presents a broadband millimeter-wave (mm-Wave) low noise amplifier (LNA) designed in a 22 nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Electromagnetic (EM) simulations suggest that the LNA has a 3-dB bandwidth (BW) from 17.8 to 42.4 GHz and a fractional bandwidth (FBW) of 81.7%, covering the key frequency bands within the mm-Wave 5G FR2 band, with its noise figure (NF) ranging from 2.9 to 4.9 dB, and its input-referred 1-dB compression point (IP1dB) of −17.9 dBm and input-referred third-order intercept point (IIP3) of −8.5 dBm at 28 GHz with 15.8 mW DC power consumption (P_DC). Using the FOM (figure-of-merit) developed for broadband LNAs (FOM = 20 × log((Gain[V/V] × S₂₁-3 dB-BW [GHz])/(P_DC [mW] × (F-1)))), this LNA achieves a competitive FOM (FOM = 18.9) among reported state-of-the-art mm-Wave LNAs in the literature. Full article