Hardware Design Systems at Chip and Board Level

Dear Colleagues,

We invite contributions for a Special Issue on hardware design methodologies, specification languages, and standards for on-chip and inter-chip interconnect. Designers are increasingly looking for turn-key tool flows when assembling components at the ASIC, MCM, PCB or rack level. Automated flows validate functional requirements, estimate metrics for performance, area and energy, and generate documentation and software stubs for hardware/software co-design and hierarchical modular assembly.

Although recent hardware description languages incorporate features to assist component interconnection, the EDA industry remains fragmented in its approach. The need for a rapid assembly of complex electronics systems is ever-growing, especially with FPGA-in-the-cloud and ever-decreasing consumer product lifetime. Die stacking and the multi-chip module have introduced a new level of design hierarchy. Cache-consistent interconnect and new generations of bus protocol are getting more and more complex, but they are increasingly designed for automatic discovery and configuration, both at design and boot time. Standards for component and interface description are lacking, with most machine-readable component meta-data existing only in silos and without inter-vendor compatibility.

High-performance serial interconnect is increasingly used at the physical layer with channel bonding, channel sharing, and protocol adaption implemented in hardware at the end points. Automatic deployment of such channels is especially important for portable hardware accelerators that must be projected onto different numbers of FPGAs on various blades. Equally, memory bank aggregation and sharing must also be managed with something akin to link editing required to allocate address maps in both DRAM and register spaces.

Automatic connection of debug infrastructure is also required. Debug components are increasingly self-describing for boot-time discovery at the board level, but high performance and secured access ports and bus mechanisms must be manually deployed for debug access. Again, inter-vendor tool flows should preferably manage the nuts-and-bolts of debug access and facilitate multi-chip composition.

Dr. David J Greaves
Guest Editor

Manuscript Submission Information

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• electronic data sheet
• IP-XACT
• interconnect synthesis
• AXI
• compatibility checking
• chisel
• RTL
• Bluespec
• PCIe
• SystemC
• TLM
• interconnect modeling
• device packaging
• multi-chip modules (MCMs)
• SMP2