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Electronics
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Program Analysis and Optimizing Compilers for High-Performance Computing
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Program Analysis and Optimizing Compilers for High-Performance Computing

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (31 December 2021) | Viewed by 5629

Special Issue Editor

Dr. Seyong Lee

E-Mail Website
Guest Editor
Programming Systems Group, Oak Ridge National Laboratory, Oak Ridge, TN 37831, USA
Interests: programming models; compilers; program analysis and optimizations; heterogeneous computing; high-performance computing
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

The recent technical trend toward extreme heterogeneity in processors, accelerators, memory hierarchies, on-chip interconnect networks, storage, etc., makes current and future computing systems more complex and diverse. This technical trend exposes significant challenges in programming and optimizing applications onto heterogeneous systems. The purpose of this Special Issue is to bring together application developers, compilers and other tool developers, and researchers working on various program analysis and performance optimization techniques for an exchange of experiences and new approaches to achieve performance portability in the era of extremely heterogeneous computing.   

The topics of interest include but are not limited to:

  • Program analysis tools and methodologies to understand program behavior and resource requirements;
  • Efficient profiling and instrumentation techniques to characterize applications and target systems;
  • Code generation, translation, transformation, and optimization techniques to achieve performance portability;
  • Optimizing compiler design, practice, and experience;
  • Methodologies for performance engineering

Dr. Seyong Lee
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Program analysis
  • Optimizing compilers
  • Code generation and optimization
  • Performance portability
  • Heterogeneous computing
  • High-performance computing

Published Papers (2 papers)

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Research

22 pages, 605 KiB  
Article
Automatic and Interactive Program Parallelization Using the Cetus Source to Source Compiler Infrastructure v2.0
by Akshay Bhosale, Parinaz Barakhshan, Miguel Romero Rosas and Rudolf Eigenmann
Electronics 2022, 11(5), 809; https://doi.org/10.3390/electronics11050809 - 4 Mar 2022
Cited by 5 | Viewed by 2602
Abstract
This paper presents an overview and evaluation of the existing and newly added analysis and transformation techniques in the Cetus source-to-source compiler infrastructure. Cetus is used for research on compiler optimizations for multi-cores with an emphasis on automatic parallelization. The compiler has gone [...] Read more.
This paper presents an overview and evaluation of the existing and newly added analysis and transformation techniques in the Cetus source-to-source compiler infrastructure. Cetus is used for research on compiler optimizations for multi-cores with an emphasis on automatic parallelization. The compiler has gone through several iterations of benchmark studies and implementations of those techniques that could improve the parallel performance of these programs. This work seeks to measure the impact of the existing Cetus techniques on the newer versions of some of these benchmarks. In addition, we describe and evaluate the recent advances made in Cetus, which are the capability of analyzing subscripted subscripts and a feature for interactive parallelization. Cetus started as a class project in the 1990s and grew with support from Purdue University and from the National Science Foundation (NSF), as well as through countless volunteer projects by enthusiastic students. While many Version-1 releases were distributed via the Purdue download site, Version 2 is being readied for release from the University of Delaware. Full article
(This article belongs to the Special Issue Program Analysis and Optimizing Compilers for High-Performance Computing)
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22 pages, 619 KiB  
Article
Space-Time Loop Tiling for Dynamic Programming Codes
by Wlodzimierz Bielecki and Marek Palkowski
Electronics 2021, 10(18), 2233; https://doi.org/10.3390/electronics10182233 - 12 Sep 2021
Cited by 1 | Viewed by 1974
Abstract
We present a new space-time loop tiling approach and demonstrate its application for the generation of parallel tiled code of enhanced locality for three dynamic programming algorithms. The technique envisages that, for each loop nest statement, sub-spaces are first generated so that the [...] Read more.
We present a new space-time loop tiling approach and demonstrate its application for the generation of parallel tiled code of enhanced locality for three dynamic programming algorithms. The technique envisages that, for each loop nest statement, sub-spaces are first generated so that the intersection of them results in space tiles. Space tiles can be enumerated in lexicographical order or in parallel by using the wave-front technique. Then, within each space tile, time slices are formed, which are enumerated in lexicographical order. Target tiles are represented with multiple time slices within each space tile. We explain the basic idea of space-time loop tiling and then illustrate it by means of an example. Then, we present a formal algorithm and prove its correctness. The algorithm is implemented in the publicly available TRACO compiler. Experimental results demonstrate that parallel codes generated by means of the presented approach outperform closely related manually generated ones or those generated by using affine transformations. The main advantage of code generated by means of the presented approach is its enhanced locality due to splitting each larger space tile into multiple smaller tiles represented with time slices. Full article
(This article belongs to the Special Issue Program Analysis and Optimizing Compilers for High-Performance Computing)
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