Highly Efficient Synapse-Device-Based Neuromorphic Systems

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Semiconductor Devices".

Deadline for manuscript submissions: closed (28 February 2021) | Viewed by 2955

Special Issue Editor


E-Mail Website
Guest Editor
Advanced Semiconductor Device Laboratory, Department of Electronic Materials Engineering, Kwangwoon University, Seoul, Korea
Interests: semiconductor device and fabrication; neuromorphic system; device characterization

Special Issue Information

Recently, artificial intelligence (AI) has been significantly improved through brain-inspired neural networks and deep learning. In particular, in various tasks such as large-scale visual and auditory recognition/classification, the accuracy of the AI has surpassed human-level accuracy. However, to apply the AI on various user-based applications, hardware resources are still limited despite the various available approaches, such as hardware accelerators and CMOS ASICs. Therefore, as an alternative hardware platform, a synapse-device-based neuromorphic system including parallel matrix–vector multiplication has been proposed. Based on multilevel states and parallel connection of the synapse devices, weight storage and fast parallel matrix–vector multiplication can be realized. Therefore, various requirements, such as multilevel state and low power consumption of the synapse device, operation interference in array scale, circuital demonstration of learning rule/algorithm, etc. need to be satisfied. This Special Issue of Electronics aims to call for recent research on the synapse-device-based neuromorphic system from material to system scale.

Topic of Interests

Prospective authors are invited to submit original works and extended works based on the topics from a wide range of synapse-device-based neuromorphic systems. The synapse devices include (but are not limited to) the following devices: RRAM, CBRAM, FTJ (or other ferroelectric devices), STT-MRAM (or other spintronic devices), PCM, Flash (or other floating-gate/charge trap devices), etc. From material to circuitry, the following topics are solicited:

  • Materials/devices for synapses and neurons;
  • Brain-inspired neural networks with synapse/neuron devices;
  • Selector materials/devices for crossbar array for neuromorphic systems;
  • Array scale demonstration for neuromorphic systems;
  • Architectural design/circuitry for neuromorphic systems;
  • Learning algorithms and architecture/circuitry for neuromorphic systems.

Prof. Dr. Daeseok Lee
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (1 paper)

Order results
Result details
Select all
Export citation of selected articles as:

Research

13 pages, 2528 KiB  
Article
An On-Chip Learning Method for Neuromorphic Systems Based on Non-Ideal Synapse Devices
by Jae-Eun Lee, Chuljun Lee, Dong-Wook Kim, Daeseok Lee and Young-Ho Seo
Electronics 2020, 9(11), 1946; https://doi.org/10.3390/electronics9111946 - 18 Nov 2020
Cited by 3 | Viewed by 2548
Abstract
In this paper, we propose an on-chip learning method that can overcome the poor characteristics of pre-developed practical synaptic devices, thereby increasing the accuracy of the neural network based on the neuromorphic system. The fabricated synaptic devices, based on Pr1x [...] Read more.
In this paper, we propose an on-chip learning method that can overcome the poor characteristics of pre-developed practical synaptic devices, thereby increasing the accuracy of the neural network based on the neuromorphic system. The fabricated synaptic devices, based on Pr1xCaxMnO3, LiCoO2, and TiOx, inherently suffer from undesirable characteristics, such as nonlinearity, discontinuities, and asymmetric conductance responses, which degrade the neuromorphic system performance. To address these limitations, we have proposed a conductance-based linear weighted quantization method, which controls conductance changes, and trained a neural network to predict the handwritten digits from the standard database MNIST. Furthermore, we quantitatively considered the non-ideal case, to ensure reliability by limiting the conductance level to that which synaptic devices can practically accept. Based on this proposed learning method, we significantly improved the neuromorphic system, without any hardware modifications to the synaptic devices or neuromorphic systems. Thus, the results emphatically show that, even for devices with poor synaptic characteristics, the neuromorphic system performance can be improved. Full article
(This article belongs to the Special Issue Highly Efficient Synapse-Device-Based Neuromorphic Systems)
Show Figures

Figure 1

Back to TopTop