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Special Issue "Deep Learning-Based Routing for Network-on-a-Chip (NoC): Opportunities, Challenges, and Solutions"
Deadline for manuscript submissions: 31 May 2020.
Interests: resource management; wireless networks; mobile networks; performance evaluation; embedded systems; machine learning
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Dear Colleagues,System-on-a-chip (SoC) technology incorporates all the required electronic circuits of numerous computer components onto a single integrated chip. An SoC usually contains various components such as an operating system, utility software applications, power management circuits, timing sources or oscillators, microprocessors, microcontrollers or digital signal processors, external interfaces (that is, USB, Ethernet, etc.), and RAM/ROM. However, SoC is facing scalability issues due to the increase in the number of on-chip resources as well as various communication requirements among these processing elements (PEs). Hence, the concept of network-on-a-chip (NoC) comes into play to overcome the scalability and latency issues of SoC. NoC is a concept in which a single silicon chip is used to implement the communication features of a large scale to a very large-scale integrated system. Its architecture comprises interconnected hybrid elements of SoC. NoC modeling and design has several tradeoff choices, like appropriate routing algorithm selection, topology design, application mapping to underlying network architecture, communication infrastructure, and router design.
An appropriate routing algorithm selection is very critical for the power requirements, as well as area and latency of the network. Routing algorithms that follow a predetermined path to reach the destination are classified as deterministic routing algorithms. Adaptive routing algorithms are capable to handle irregularities in path availability. A major problem in NoC is the reliability of the routers due to increased physical defects raised after the post-manufacturing process. This challenge of dealing with fault tolerance has become very important. These faults may be permanent in nature that will stay for a long time or they may be transient in nature because of radiations and external electrical fluctuations. The presence of faulty routs can lead to an unreliable NoC architecture. Therefore, fault-tolerant routing schemes are required to deal with such permanent or transient faults. The current state-of-the-art fault-tolerant routing algorithms have issues such as greater latency, lesser throughput, congestion/busy unawareness, hotspot unawareness, and less consideration on the simplex links in the bidirectional channels. They consider either faulty nodes or faulty duplex channels as a route metric. Therefore, to address such problems and challenges, this area requires more attention from researchers.
The ability of NoC to communicate effectively and reliably depends profoundly on the underlying NoC network topology. NoC network topology eventually affects the network throughput, latency, covered area, power requirement, and fault tolerance. Moreover, topology selection also plays a vital role in the routing algorithm design and implementation. However, there is still no theoretical solution to determine and implement an optimal NoC network topology for a given application. Hence, efficient topologies that trade off optimally between the implementation at the hardware level and the system performance require profound attention from researchers. In NoC architectures, a list of concurrent tasks is scheduled and mapped to a set of selected IP addresses. It is very important for the application mapping to find out how to topologically map the selected IP addresses on the NoC network such that certain metrics of interests can be satisfied.
Recently, artificial intelligence, thriving thanks to the advancements in deep learning (DL), has proven to be very valuable in a wide range of diverse applications. One of the key applications of future NoC architectures is the design and implementation of intelligent routing protocols for NoC networks. As mentioned earlier, the challenges and issues faced by the design and implementation of routing protocols in NoC architectures lead many researchers and practitioners to explore the application of DL techniques to make routing in the NoC architectures intelligent, reliable, and optimally performing.
Therefore, in this Special Issue (SI), we aim to bring together leading as well as academic and industrial researchers to explore the opportunities of DL for routing in NoC and to focus its impact on the solutions of the aforementioned challenges and propose feasible solutions. We encourage papers covering various topics of interest that include but are not limited to the following list:
- DL-based architectures/frameworks for NoC systems;
- DL-based technologies (routers/PEs) for routing protocols in NoC systems;
- DL-based routing services for specific applications of NoC systems (Multicast, unicast, etc.);
- DL-based network topology design for NoC architectures;
- DL-based routing protocols for NoC systems;
- DL-based energy efficient routing protocols for NoC systems;
- DL-based mapping algorithms for NoC systems;
- DL-based network floorplanning algorithms for NoC systems;
- DL-based wireless NoC (WNoC) architectures/frameworks (partially/fully wireless network);
- DL-based errors of fault handling/correction mechanisms in NoC
Papers must be tailored to the problems related to NoC systems and explicitly consider DL-based routing for NoC technologies. The scope of the SI is not limited to the abovementioned topics. However, the editors maintain the right to reject papers they deem to be out of the scope of this SI. Only original, unpublished contributions and invited articles will be considered for the issue. The papers should be formatted according to the Electronics guidelines (https://www.mdpi.com/journal/electronics/instructions). Authors should submit according to the submission guidelines (https://susy.mdpi.com/).
Prof. Dr. Sung Won Kim
Dr. Rashid Ali
Manuscript Submission Information
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Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access monthly journal published by MDPI.
Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.
- network on a chip
- deep learning
- complex networks
- network routing