Emerging Developments in Cybersecurity: Addressing Systemic Weaknesses in a Connected World

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (15 December 2024) | Viewed by 1286

Special Issue Editors


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Guest Editor
Department of Electrical and Computer Engineering, Kansas State University, Manhattan, KS 66506, USA
Interests: hardware security; third-party IP protection; formal verification and program analysis; language-based security

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Guest Editor
Department of Electrical and Computer Engineering, University of New Hampshire, Durham, NH 03824, USA
Interests: architectural security

Special Issue Information

Dear Colleagues,

Recently, there has been an explosion of attacks targeting common systems. Secure solutions are often recommended to combat these threats. However, a secure system, whether it be an IoT device or an HPC cluster, is only as secure as its weakest component. Furthermore, new and emerging threats consistently reveal that these “secure-by-design” solutions are lacking. Rather than seeking to combat piecemeal threats with ad hoc solutions, research should instead be focused on incorporating vulnerability discovery into the design life-cycle. Therefore, the purpose of this Special Issue is to seek contributions that not only investigate new hardware, microarchitectural, or software attacks but also automate exploit discovery against these computing systems. Topics of interest include, but are not limited to, the following areas:

  • Side-channel and fault attack, and resilience/countermeasures;
  • Intrusion and anomaly detection;
  • CPS security;
  • Smart grid security;
  • Cloud security;
  • Hardware security and privacy;
  • Formal method-based security verification, program analysis, and fuzzing;
  • Security tool development;
  • Security-oriented hardware design, or hardware and software co-design;
  • IoT devices and protocol security;
  • Machine learning and artificial intelligence for vulnerability discovery;
  • Empowering security with large language models;
  • Security and resilience in autonomous vehicle systems.

Dr. Xiaolong Guo
Dr. Dean Sullivan
Guest Editors

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Keywords

  • side-channel and fault attack, and resilience/countermeasures
  • intrusion and anomaly detection
  • CPS security
  • smart grid security
  • cloud security
  • hardware security and privacy
  • formal method-based security verification, program analysis, and fuzzing
  • security tool development
  • security-oriented hardware design, or hardware and software co-design
  • IoT devices and protocol security
  • machine learning and artificial intelligence for vulnerability discovery
  • empowering security with large language models
  • security and resilience in autonomous vehicle systems

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Published Papers (1 paper)

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Research

25 pages, 976 KiB  
Article
HT-PGFV: Security-Aware Hardware Trojan Security Property Generation and Formal Security Verification Scheme
by Maoyuan Qin, Jiale Li, Jiaqi Yan, Zishuai Hao, Wei Hu and Baolong Liu
Electronics 2024, 13(21), 4286; https://doi.org/10.3390/electronics13214286 - 31 Oct 2024
Viewed by 1016
Abstract
Property-driven hardware verification provides a promising way to uncover design vulnerabilities. However, developing security properties that check for highly concealed security vulnerabilities remains a significant challenge. In this paper, we propose a scheme, called HT-PGFV, to implement hardware Trojan security property assertion automatic [...] Read more.
Property-driven hardware verification provides a promising way to uncover design vulnerabilities. However, developing security properties that check for highly concealed security vulnerabilities remains a significant challenge. In this paper, we propose a scheme, called HT-PGFV, to implement hardware Trojan security property assertion automatic generation and formal security verification for Trojan-infected designs. In our scheme, we develop a hardware Trojan security property assertion generation method for automated hardware which can extract hardware Trojan security properties from Trojan-infected designs by performing the three main steps of Trojan-infected signal identification based on feature matching, influence-cone-analysis-based Trojan path identification, and information flow trace mining, and formulate them as SystemVerilog assertions. In addition, we develop a formal security verification method based on information flow analysis which can formally verify hardware Trojan security properties and detect hardware Trojans violating information flow security policies by checking the security of information flows via our developed RT-level hardware information flow security models. The proposed method is demonstrated on several Trojan benchmarks from Trust-Hub. Experimental results show that our scheme can generate hardware Trojan security property assertions for Trojan-infected designs and detect information leakage and functionality change hardware Trojans activated by external inputs or internal conditions. Full article
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