Machine Learning in Network-on-Chip Architectures

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Networks".

Deadline for manuscript submissions: closed (16 February 2025) | Viewed by 6321

Special Issue Editors


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Guest Editor
Electrical and Computer Engineering Department, University of Victoria, Victoria, BC V8W 3P6, Canada
Interests: computer architecture; network on chip; silicon photonics; machine learning
Special Issues, Collections and Topics in MDPI journals

E-Mail Website
Guest Editor
Electrical and Computer Engineering Department, University of Victoria, Victoria, BC V8W 3P6, Canada
Interests: network-on-chips, wireless communications, high performance architectures

Special Issue Information

Dear Colleagues,

We cordially invite you to submit your papers for the MDPI Electronics (IF=2.9) special issue on "Machine Learning in Network-on-Chip (NoC) Architectures". The goal of this special issue is to explore the intersection of machine learning and NoC architectures and present the latest advancements, applications, and challenges as they relate to this exciting area.

Network-on-Chip architectures have emerged as a promising solution for efficient communication in complex system-on-chip designs. Artificial intelligence and machine learning have grown rapidly in recent years, and their integration into NoC architectures is becoming increasingly important. NoC designs can benefit from machine learning techniques in many ways, including performance optimization, energy efficiency, fault tolerance, and resource allocation.

The scope includes, but is not limited to, the following:

  1. Machine learning-based routing algorithms for NoCs
  2. Deep learning techniques for congestion and deadlock avoidance
  3. Neural network models for adaptive flow control in NoCs
  4. Reinforcement learning approaches for fault-tolerant NoC designs
  5. Dependable system design in Nocs with machine learning techniques
  6. Machine learning-based power optimization in NoC architectures
  7. Data-driven approaches for NoC design exploration and optimization
  8. AI-driven resource allocation and management in NoCs
  9. Case studies and applications of machine learning in different NoC architectures such as electrical, optical and wireless.

Dr. Meisam Abdollahi
Dr. Amir Baharloo
Guest Editors

Manuscript Submission Information

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Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • machine learning
  • artificial intelligence
  • network-on-chip
  • multi/many-core systems
  • high performance
  • power efficiency
  • reliable on-chip communication

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Published Papers (2 papers)

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Research

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13 pages, 5484 KiB  
Article
A 14-Bit Digital to Analog Converter for a Topmetal-CEE Pixel Readout Chip
by Yunqi Deng, Ping Yang, Guangming Huang, Jun Liu, Zhongguang Ren, Yan Fan and Zixuan Song
Electronics 2024, 13(15), 3074; https://doi.org/10.3390/electronics13153074 - 3 Aug 2024
Viewed by 1167
Abstract
The Lanzhou Heavy Ion Research Facility (LIRF) is the largest heavy ion research facility in China, providing a substantial volume of experimental data for fundamental research in nuclear physics. The Topmetal-CEE is a pixel readout chip specifically designed for tracking detectors. Within the [...] Read more.
The Lanzhou Heavy Ion Research Facility (LIRF) is the largest heavy ion research facility in China, providing a substantial volume of experimental data for fundamental research in nuclear physics. The Topmetal-CEE is a pixel readout chip specifically designed for tracking detectors. Within the Topmetal-CEE framework, the front-end amplifier and comparator necessitate precisely adjustable bias voltages. Hence, in this paper, a 14-bit resolution DAC with an R-2R resistor network structure is designed, along with an amplifier featuring high driving capabilities as the DAC driver, thus preventing potential impedance issues when driving large pixel arrays. Test results demonstrate that the DAC module, operating under a 3.3 V supply voltage, can consistently output voltages ranging from 0 to 1.8 V. Furthermore, the differential non-linearity error is less than 1.07 LSB, and the integral non-linearity error is less than 1.57 LSB. Full article
(This article belongs to the Special Issue Machine Learning in Network-on-Chip Architectures)
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Review

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73 pages, 3621 KiB  
Review
Hardware Design and Verification with Large Language Models: A Scoping Review, Challenges, and Open Issues
by Meisam Abdollahi, Seyedeh Faegheh Yeganli, Mohammad (Amir) Baharloo and Amirali Baniasadi
Electronics 2025, 14(1), 120; https://doi.org/10.3390/electronics14010120 - 30 Dec 2024
Viewed by 4619
Abstract
Background: Large Language Models (LLMs) are emerging as promising tools in hardware design and verification, with recent advancements suggesting they could fundamentally reshape conventional practices. Objective: This study examines the significance of LLMs in shaping the future of hardware design and verification. It [...] Read more.
Background: Large Language Models (LLMs) are emerging as promising tools in hardware design and verification, with recent advancements suggesting they could fundamentally reshape conventional practices. Objective: This study examines the significance of LLMs in shaping the future of hardware design and verification. It offers an extensive literature review, addresses key challenges, and highlights open research questions in this field. Design: in this scoping review, we survey over 360 papers most of the published between 2022 and 2024, including 71 directly relevant ones to the topic, to evaluate the current role of LLMs in advancing automation, optimization, and innovation in hardware design and verification workflows. Results: Our review highlights LLM applications across synthesis, simulation, and formal verification, emphasizing their potential to streamline development processes while upholding high standards of accuracy and performance. We identify critical challenges, such as scalability, model interpretability, and the alignment of LLMs with domain-specific languages and methodologies. Furthermore, we discuss open issues, including the necessity for tailored model fine-tuning, integration with existing Electronic Design Automation (EDA) tools, and effective handling of complex data structures typical of hardware projects. Conclusions: this survey not only consolidates existing knowledge but also outlines prospective research directions, underscoring the transformative role LLMs could play in the future of hardware design and verification. Full article
(This article belongs to the Special Issue Machine Learning in Network-on-Chip Architectures)
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