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Elbow Joint Angle Estimation Using a Low-Cost and Low-Power Single Inertial Device for Daily Home-Based Self-Rehabilitation
A Comprehensive Analysis of Losses and Efficiency in a Buck ZCS Quasi-Resonant DC/DC Converter
A 0.8 V Low-Power Wide-Tuning-Range CMOS VCO for 802.11ac and IoT C-Band Applications

Journal Description

Journal of Low Power Electronics and Applications

Journal of Low Power Electronics and Applications is an international, peer-reviewed, open access journal on low power electronics published quarterly online by MDPI.

Open Access— free for readers, with article processing charges (APC) paid by authors or their institutions.
High Visibility: indexed within Scopus, ESCI (Web of Science), Inspec, and other databases.
Rapid Publication: manuscripts are peer-reviewed and a first decision is provided to authors approximately 23.4 days after submission; acceptance to publication is undertaken in 2.8 days (median values for papers published in this journal in the first half of 2025).
Journal Rank: CiteScore - Q2 (Electrical and Electronic Engineering)
Recognition of Reviewers: reviewers who provide timely, thorough peer-review reports receive vouchers entitling them to a discount on the APC of their next publication in any MDPI journal, in appreciation of the work done.
Journal Cluster of Electronic Engineering and Hardware Systems: Chips, Electronics, Hardware, Journal of Low Power Electronics and Applications, Microelectronics and Microwave.

Impact Factor: 1.8 (2024); 5-Year Impact Factor: 1.6 (2024)

Imprint Information Journal Flyer Open Access ISSN: 2079-9268

Latest Articles

13 pages, 1281 KiB

Open AccessArticle

Fast Energy Recovery During Motor Braking: Analysis and Simulation

by Lin Xu, Wengan Li, Zenglong Zhao and Fanyi Meng

J. Low Power Electron. Appl. 2025, 15(3), 49; https://doi.org/10.3390/jlpea15030049 - 22 Aug 2025

At present, environmental pollution is becoming more and more serious, and the energy problem is becoming more prominent. Energy-braking recovery can collect the mechanical energy lost in the traditional braking process and convert it into electricity or other forms of energy for vehicle [...] Read more.

At present, environmental pollution is becoming more and more serious, and the energy problem is becoming more prominent. Energy-braking recovery can collect the mechanical energy lost in the traditional braking process and convert it into electricity or other forms of energy for vehicle reuse, thus reducing carbon emissions, achieving energy saving and emission reduction, and promoting green development. Based on this, this paper studies the energy-braking recovery method. The study focuses specifically on the recovery of energy during vehicle braking triggered by brake-signal activation, without addressing alternative deceleration strategies under braking conditions. The proposed energy-braking recovery scheme is evaluated primarily through simulation, with the analysis grounded in practical application scenarios and leveraging existing technologies. Firstly, the principle of energy-braking recovery is introduced, and the method of estimating the State on Charge (SOC) of the battery and controlling the motor speed is determined. Then, the simulation model of the energy brake recovery system is built with MATLAB R2023b (MathWorks, Natick, MA, USA), and the design ideas and specific structures of the three modules of the simulation model are introduced in detail. Finally, the results of the simulated motor speed and SOC value of the battery are analysed, and it is confirmed that they meet the requirements of the system and achieve close to the ideal effect. Full article

21 pages, 19398 KiB

Open AccessArticle

A Non-Isolated High Gain Step-Up DC/DC Converter Based on Coupled Inductor with Reduced Voltage Stresses

by Yuqing Yang, Song Xu, Wei Jiang and Seiji Hashimoto

J. Low Power Electron. Appl. 2025, 15(3), 48; https://doi.org/10.3390/jlpea15030048 - 22 Aug 2025

Hybrid electric vehicles (HEVs) have gained significant attention for their superior energy efficiency and are becoming a predominant mode of urban transportation. The DC/DC converter plays a critical role in HEV energy management systems, especially in matching the voltage levels between the battery [...] Read more.

Hybrid electric vehicles (HEVs) have gained significant attention for their superior energy efficiency and are becoming a predominant mode of urban transportation. The DC/DC converter plays a critical role in HEV energy management systems, especially in matching the voltage levels between the battery and DC bus. This paper proposes a novel high-gain DC/DC converter with a wide input voltage range based on coupled inductors. The innovation lies in the integration of a resonant cavity and the simultaneous realization of zero-voltage switching (ZVS) and zero-current switching (ZCS), effectively reducing both voltage/current stresses on the power switches and switching losses. Compared with conventional topologies, the proposed design achieves higher voltage gain without extreme duty cycles, improved conversion efficiency, and enhanced reliability. Detailed operating principles are analyzed, and design conditions for voltage stress reduction, gain extension, and soft switching are derived. The simulation model has been conducted in a PSIM environment, and a 300 W experimental prototype, implemented using a dsPIC33FJ64GS606 digital controller, has been established and demonstrates 93% peak efficiency at a 10 times voltage gain. The performance and practical feasibility of the proposed topology have been evaluated by both simulation and experiments. Full article

(This article belongs to the Topic Advanced Integrated Circuit Design and Application)

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18 pages, 1423 KiB

Open AccessArticle

Design of a Power-Aware Reconfigurable and Parameterizable Pseudorandom Pattern Generator for BIST-Based Applications

by Geethu Remadevi Somanathan, Ujarla Harshavardhan Reddy and Ramesh Bhakthavatchalu

J. Low Power Electron. Appl. 2025, 15(3), 47; https://doi.org/10.3390/jlpea15030047 - 15 Aug 2025

This paper presents a power-aware Reconfigurable Parameterizable Pseudorandom Pattern Generator (RP-PRPG) for a number of applications, including built in self-testing (BIST) and cryptography. Linear Feedback Shift Registers (LFSRs) are broadly utilized in pattern generation due to their efficiency and simplicity. However, the diversity [...] Read more.

This paper presents a power-aware Reconfigurable Parameterizable Pseudorandom Pattern Generator (RP-PRPG) for a number of applications, including built in self-testing (BIST) and cryptography. Linear Feedback Shift Registers (LFSRs) are broadly utilized in pattern generation due to their efficiency and simplicity. However, the diversity of generated patterns, as well as their power consumption, improves through circuit modifications. This work explores enhancements to LFSR structures to achieve broader range of patterns with reduced power consumption for BIST-based applications. The proposed circuit constructed on the LFSR platform can be programmed to generate patterns with varying degrees of different LFSR configurations. Diverse set of patterns of any circuit arrangement can be created using any characteristic polynomial and by utilizing the reseeding capacity of the circuit. The circuit combines a double-tier linear feedback circuit with zero forcing methods, resulting in more than 70% transition reduction, thus significantly lowering power dissipation. The behaviour of the proposed circuit is assessed for characteristic polynomials with degrees ranging from 4 to 128 using various Linear Feedback Shift Register (LFSR) topologies. For reconfigurable HDL and ASIC synthesis, the power-aware RP-PRPG can be used to generate an efficient set of stream ciphers as well as applications involving the scan-for-test protocol. Full article

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20 pages, 2103 KiB

Open AccessArticle

Federated Multi-Stage Attention Neural Network for Multi-Label Electricity Scene Classification

by Lei Zhong, Xuejiao Jiang, Jialong Xu, Kaihong Zheng, Min Wu, Lei Gao, Chao Ma, Dewen Zhu and Yuan Ai

J. Low Power Electron. Appl. 2025, 15(3), 46; https://doi.org/10.3390/jlpea15030046 - 5 Aug 2025

Privacy-sensitive electricity scene classification requires robust models under data localization constraints, making federated learning (FL) a suitable framework. Existing FL frameworks face two critical challenges in multi-label electricity scene classification: (1) Label correlations and their strengths significantly impact classification performance. (2) Electricity scene [...] Read more.

Privacy-sensitive electricity scene classification requires robust models under data localization constraints, making federated learning (FL) a suitable framework. Existing FL frameworks face two critical challenges in multi-label electricity scene classification: (1) Label correlations and their strengths significantly impact classification performance. (2) Electricity scene data and labels show distributional inconsistencies across regions. However, current FL frameworks lack explicit modeling of label correlation strengths, and locally trained regional models naturally capture these differences, leading to regional differences in their model parameters. In this scenario, the server’s standard single-stage aggregation often over-averages the global model’s parameters, reducing its discriminative ability. To address these issues, we propose FMMAN, a federated multi-stage attention neural network for multi-label electricity scene classification. The main contributions of this FMMAN lie in label correlation learning and the stepwise model aggregation. It splits the client–server interaction into multiple stages: (1) Clients train models locally to encode features and label correlation strengths after receiving the server’s initial model. (2) The server clusters these locally trained models into K groups to ensure that models within a group have more consistent parameters and generates K prototype models via intra-group aggregation to reduce over-averaging. The K models are then distributed back to the clients. (3) Clients refine their models using the K prototypes with contrastive group-specific consistency regularization to further mitigate over-averaging, and sends the refined model back to the server. (4) Finally, the server aggregates the models into a global model. Experiments on multi-label benchmarks verify that FMMAN outperforms baseline methods. Full article

(This article belongs to the Special Issue Advances in Low Power Neuromorphic Computing: Models, Algorithms, and Applications)

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18 pages, 2514 KiB

Open AccessArticle

Event-Triggered Model Predictive Control of Buck Converter with Disturbances: Design and Experimentation

by Ziyuan Yang, Shengquan Li, Kaiwen Cao, Donglei Chen, Juan Li and Wei Cao

J. Low Power Electron. Appl. 2025, 15(3), 45; https://doi.org/10.3390/jlpea15030045 - 1 Aug 2025

Considering the challenges posed by traditional continuous control set model predictive control (CCS-MPC) calculations, this paper proposes an event-triggered-based model predictive control (ET-MPC). First, a novel tracking error state-space model is proposed to improve tracking performance. Second, a reduced-order extended state observer (RESO) [...] Read more.

Considering the challenges posed by traditional continuous control set model predictive control (CCS-MPC) calculations, this paper proposes an event-triggered-based model predictive control (ET-MPC). First, a novel tracking error state-space model is proposed to improve tracking performance. Second, a reduced-order extended state observer (RESO) is designed to estimate and compensate for the total disturbances, thereby effectively improving robustness against the variations of the load resistance and reference voltage. At the same time, RESO significantly reduces computational complexity and accelerates the convergence speed of state estimation. Subsequently, an event trigger mechanism is introduced to enhance the MPC with a threshold function for the converter status. Finally, the reduced-order extended state observer-based model predictive control (RESO-MPC) is compared with the proposed ET-MPC through experiments. The ripple voltage of ET-MPC is within 2%, and the computational burden is reduced by more than 57%, verifying the effectiveness of the proposed ET-MPC. Full article

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12 pages, 2575 KiB

Open AccessArticle

Simulation of Propagation Characteristics and Field Distribution in Cylindrical Photonic Crystals Composed of Near-Zero Materials and Metal

by Zhihao Xu, Dan Zhang, Rongkang Xuan, Shenxiang Yang and Na Wang

J. Low Power Electron. Appl. 2025, 15(3), 44; https://doi.org/10.3390/jlpea15030044 - 31 Jul 2025

This study investigates the propagation characteristics and field distribution of photonic crystals composed of epsilon-near-zero (ENZ) materials and metal cylinders. The research reveals that the cutoff frequency of the photonic crystal formed by combining metal cylinders with an ENZ background is independent of [...] Read more.

This study investigates the propagation characteristics and field distribution of photonic crystals composed of epsilon-near-zero (ENZ) materials and metal cylinders. The research reveals that the cutoff frequency of the photonic crystal formed by combining metal cylinders with an ENZ background is independent of the volume fraction of the metal cylinders and exhibits a stop-band profile within the measured frequency range. This unique behavior is attributed to the scattering of long-wavelength light when the wavelength approaches the effective wavelength range of the ENZ material. Taking advantage of this feature, the study selectively filters specific wavelength ranges from the mid-frequency band by varying the ratio of cylinder radius to lattice constant (R/a). Decreasing the R/a ratio enables the design of waveguide devices that operate over a broader guided wavelength range within the intermediate-frequency band. The findings emphasize the importance of the interaction between light and ENZ materials in shaping the transmission characteristics of photonic crystal structures. Full article

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13 pages, 2428 KiB

Open AccessArticle

A Novel Low-Power Bipolar DC–DC Converter with Voltage Self-Balancing

by Yangfan Liu, Qixiao Li and Zhongxuan Wang

J. Low Power Electron. Appl. 2025, 15(3), 43; https://doi.org/10.3390/jlpea15030043 - 24 Jul 2025

Bipolar power supply can effectively reduce line losses and optimize power transmission. This paper proposes a low-power bipolar DC–DC converter with voltage self-balancing, which not only achieves bipolar output but also automatically balances the inter-pole voltage under load imbalance conditions without requiring additional [...] Read more.

Bipolar power supply can effectively reduce line losses and optimize power transmission. This paper proposes a low-power bipolar DC–DC converter with voltage self-balancing, which not only achieves bipolar output but also automatically balances the inter-pole voltage under load imbalance conditions without requiring additional voltage balancing control. This paper first elaborates on the derivation process of the proposed converter, then analyzes its working principles and performance characteristics. A 400 W experimental prototype is built to validate the correctness of the theoretical analysis and the voltage self-balancing capability. Finally, loss analysis and conclusions are presented. Full article

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17 pages, 493 KiB

Open AccessArticle

Microstrip Line Modeling Taking into Account Dispersion Using a General-Purpose SPICE Simulator

by Vadim Kuznetsov

J. Low Power Electron. Appl. 2025, 15(3), 42; https://doi.org/10.3390/jlpea15030042 - 22 Jul 2025

XSPICE models for a generic transmission line, a microstrip line, and coupled microstrips are presented. The developed models extend general-purpose circuit simulation tools using RF circuits design features. The models could be used for circuit simulation in frequency, DC, and time domains for [...] Read more.

XSPICE models for a generic transmission line, a microstrip line, and coupled microstrips are presented. The developed models extend general-purpose circuit simulation tools using RF circuits design features. The models could be used for circuit simulation in frequency, DC, and time domains for any active or passive RF or microwave schematic (including microwave monolithic integrated circuits—MMICs) involving transmission lines. The presented models could be used with any circuit simulation backend supporting XSPICE extensions and could be integrated without patching the core simulator code. The presented XSPICE models for microstrip lines take into account the frequency dependency of characteristic impedance and dispersion. The models were designed using open-source circuit simulation software. This study provides a practical example of the low-noise RF amplifier (LNA) design with Ngspice simulation backend using the proposed models. Full article

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23 pages, 4087 KiB

Open AccessArticle

Low-Voltage Ride Through Capability Analysis of a Reduced-Size DFIG Excitation Utilized in Split-Shaft Wind Turbines

by Rasoul Akbari and Afshin Izadian

J. Low Power Electron. Appl. 2025, 15(3), 41; https://doi.org/10.3390/jlpea15030041 - 21 Jul 2025

Split-shaft wind turbines decouple the turbine’s shaft from the generator’s shaft, enabling several modifications in the drivetrain. One of the significant achievements of a split-shaft drivetrain is the reduction in size of the excitation circuit. The grid-side converter is eliminated, and the rotor-side [...] Read more.

Split-shaft wind turbines decouple the turbine’s shaft from the generator’s shaft, enabling several modifications in the drivetrain. One of the significant achievements of a split-shaft drivetrain is the reduction in size of the excitation circuit. The grid-side converter is eliminated, and the rotor-side converter can safely reduce its size to a fraction of a full-size excitation. Therefore, this low-power-rated converter operates at low voltage and handles regular operations well. However, fault conditions may expose weaknesses in the converter and push it to its limits. This paper investigates the effects of the reduced-size rotor-side converter on the voltage ride-through capabilities required from all wind turbines. Four different protection circuits, including the active crowbar, active crowbar along a resistor–inductor circuit (C-RL), series dynamic resistor (SDR), and new-bridge fault current limiter (NBFCL), are employed, and their effects are investigated and compared. Wind turbine controllers are also utilized to reduce the impact of faults on the power electronic converters. One effective method is to store excess energy in the generator’s rotor. The proposed low-voltage ride-through strategies are simulated in MATLAB Simulink (2022b) to validate the results and demonstrate their effectiveness and functionality. Full article

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16 pages, 2270 KiB

Open AccessArticle

Performance Evaluation of FPGA, GPU, and CPU in FIR Filter Implementation for Semiconductor-Based Systems

by Muhammet Arucu and Teodor Iliev

J. Low Power Electron. Appl. 2025, 15(3), 40; https://doi.org/10.3390/jlpea15030040 - 21 Jul 2025

This study presents a comprehensive performance evaluation of field-programmable gate array (FPGA), graphics processing unit (GPU), and central processing unit (CPU) platforms for implementing finite impulse response (FIR) filters in semiconductor-based digital signal processing (DSP) systems. Utilizing a standardized FIR filter designed with [...] Read more.

This study presents a comprehensive performance evaluation of field-programmable gate array (FPGA), graphics processing unit (GPU), and central processing unit (CPU) platforms for implementing finite impulse response (FIR) filters in semiconductor-based digital signal processing (DSP) systems. Utilizing a standardized FIR filter designed with the Kaiser window method, we compare computational efficiency, latency, and energy consumption across the ZYNQ XC7Z020 FPGA, Tesla K80 GPU, and Arm-based CPU, achieving processing times of 0.004 s, 0.008 s, and 0.107 s, respectively, with FPGA power consumption of 1.431 W and comparable energy profiles for GPU and CPU. The FPGA is 27 times faster than the CPU and 2 times faster than the GPU, demonstrating its suitability for low-latency DSP tasks. A detailed analysis of resource utilization and scalability underscores the FPGA’s reconfigurability for optimized DSP implementations. This work provides novel insights into platform-specific optimizations, addressing the demand for energy-efficient solutions in edge computing and IoT applications, with implications for advancing sustainable DSP architectures. Full article

(This article belongs to the Topic Advanced Integrated Circuit Design and Application)

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17 pages, 4316 KiB

Open AccessArticle

A Coverage Path Planning Method with Energy Optimization for UAV Monitoring Tasks

by Zhengqiang Xiong, Chang Han, Xiaoliang Wang and Li Gao

J. Low Power Electron. Appl. 2025, 15(3), 39; https://doi.org/10.3390/jlpea15030039 - 9 Jul 2025

Coverage path planning solves the problem of moving an effector over all points within a specific region with effective routes. Most existing studies focus on geometric constraints, often overlooking robot-specific features, like the available energy, weight, maximum speed, sensor resolution, etc. This paper [...] Read more.

Coverage path planning solves the problem of moving an effector over all points within a specific region with effective routes. Most existing studies focus on geometric constraints, often overlooking robot-specific features, like the available energy, weight, maximum speed, sensor resolution, etc. This paper proposes a coverage path planning algorithm for Unmanned Aerial Vehicles (UAVs) that minimizes energy consumption while satisfying a set of other requirements, such as coverage and observation resolution. To deal with these issues, we propose a novel energy-optimal coverage path planning framework for monitoring tasks. Firstly, the 3D terrain’s spatial characteristics are digitized through a combination of parametric modeling and meshing techniques. To accurately estimate actual energy expenditure along a segmented trajectory, a power estimation module is introduced, which integrates dynamic feasibility constraints into the energy computation. Utilizing a Digital Surface Model (DSM), a global energy consumption map is generated by constructing a weighted directed graph over the terrain. Subsequently, an energy-optimal coverage path is derived by applying a Genetic Algorithm (GA) to traverse this map. Extensive simulation results validate the superiority of the proposed approach compared to existing methods. Full article

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16 pages, 5447 KiB

Open AccessArticle

A Gate Driver for Crosstalk Suppression of eGaN HEMT Power Devices

by Longsheng Zhang, Kaihong Wang, Shilong Guo and Binxin Zhu

J. Low Power Electron. Appl. 2025, 15(3), 38; https://doi.org/10.3390/jlpea15030038 - 6 Jul 2025

The eGaN HEMT power devices face serious crosstalk problems when applied to high-frequency bridge circuits, thereby limiting the switching performance of these devices. To address this issue, a gate driver is proposed in this paper that can suppress both positive and negative crosstalk [...] Read more.

The eGaN HEMT power devices face serious crosstalk problems when applied to high-frequency bridge circuits, thereby limiting the switching performance of these devices. To address this issue, a gate driver is proposed in this paper that can suppress both positive and negative crosstalk of eGaN HEMT power devices, offering the advantages of simple control and easy integration. The basic idea is to suppress positive crosstalk by constructing a negative voltage capacitor, and to suppress negative crosstalk by reducing the impedance of the gate loop. To verify the capability of the proposed gate driver, double-pulse and synchronous Buck test platforms are constructed. The experimental results clearly demonstrate that the proposed gate driver reduces the positive and negative crosstalk spikes by 2.03 V and 1.54 V, respectively, ensuring that the positive and negative crosstalk spikes fall within a safe operating range. Additionally, the turn-off speed of the device is enhanced, leading to a reduction in switching loss. Full article

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29 pages, 2379 KiB

Open AccessArticle

An Analog Architecture and Algorithm for Efficient Convolutional Neural Network Image Computation

by Jennifer Hasler and Praveen Raj Ayyappan

J. Low Power Electron. Appl. 2025, 15(3), 37; https://doi.org/10.3390/jlpea15030037 - 25 Jun 2025

This article presents an energy-efficient IC architecture implementation of an analog image-processing ML system, where the primary issue is analog architecture development for existing energy-efficient analog computing devices. An architecture is developed for image classification, transforming a typical imager input into a classified [...] Read more.

This article presents an energy-efficient IC architecture implementation of an analog image-processing ML system, where the primary issue is analog architecture development for existing energy-efficient analog computing devices. An architecture is developed for image classification, transforming a typical imager input into a classified result using a particular NN algorithm, a convolutional NN (ConvNN). These efforts show the need to continue to develop energy-efficient analog architectures alongside efficient analog circuits to fully exploit the opportunities of analog computing for system application. Full article

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13 pages, 31731 KiB

Open AccessArticle

Optimized Coupling Coil Geometry for High Wireless Power Transfer Efficiency in Mobile Devices

by Fahad M. Alotaibi

J. Low Power Electron. Appl. 2025, 15(2), 36; https://doi.org/10.3390/jlpea15020036 - 17 Jun 2025

Wireless Power Transfer (WPT) enables efficient, contactless charging for mobile devices by eliminating mechanical connectors and wiring, thereby enhancing user experience and device longevity. However, conventional WPT systems remain prone to performance issues such as coil misalignment, resonance instability, and thermal losses. Addressing [...] Read more.

Wireless Power Transfer (WPT) enables efficient, contactless charging for mobile devices by eliminating mechanical connectors and wiring, thereby enhancing user experience and device longevity. However, conventional WPT systems remain prone to performance issues such as coil misalignment, resonance instability, and thermal losses. Addressing these challenges involves designing coil geometries that operate at lower resonant frequencies to strengthen magnetic coupling and decrease resistance. This work introduces a WPT system with a performance-driven coil design aimed at maximizing magnetic coupling and mutual inductance between the transmitting (Tx) and receiving (Rx) coils in mobile devices. Due to the nonlinear behavior of magnetic flux and the high computational cost of simulations, exploring the full design space for coils using ANSYS Maxwell becomes impractical. To address this complexity, a machine learning (ML)-based optimization framework is developed to efficiently navigate the design space. The framework integrates a hybrid sequential neural network and multivariate regression model to optimize coil winding and ferrite core geometry. The optimized structure achieves a mutual inductance of 12.52

μ

H with a conventional core, outperforming many existing ML models. Finite element simulations and experimental results validate the robustness of the method, which offers a scalable solution for efficient wireless charging in compact, misalignment-prone environments. Full article

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19 pages, 8803 KiB

Open AccessArticle

An Accurate and Low-Complexity Offset Calibration Methodology for Dynamic Comparators

by Juan Cuenca, Benjamin Zambrano, Esteban Garzón, Luis Miguel Prócel and Marco Lanuzza

J. Low Power Electron. Appl. 2025, 15(2), 35; https://doi.org/10.3390/jlpea15020035 - 2 Jun 2025

Dynamic comparators play an important role in electronic systems, requiring high accuracy, low power consumption, and minimal offset voltage. This work proposes an accurate and low-complexity offset calibration design based on a capacitive load approach. It was designed using a 65 nm CMOS [...] Read more.

Dynamic comparators play an important role in electronic systems, requiring high accuracy, low power consumption, and minimal offset voltage. This work proposes an accurate and low-complexity offset calibration design based on a capacitive load approach. It was designed using a 65 nm CMOS technology and comprehensively evaluated under Monte Carlo simulations and PVT variations. The proposed scheme was built using MIM capacitors and transistor-based capacitors, and it includes Verilog-based calibration algorithms. The proposed offset calibration is benchmarked, in terms of precision, calibration time, energy consumption, delay, and area, against prior calibration techniques: current injection via gate biasing by a charge pump circuit and current injection via parallel transistors. The evaluation of the offset calibration schemes relies on Analog/Mixed-Signal (AMS) simulations, ensuring accurate evaluation of digital and analog domains. The charge pump method achieved the best Energy-Delay Product (EDP) at the cost of lower long-term accuracy, mainly because of its capacitor leakage. The proposed scheme demonstrated superior performance in offset reduction, achieving a one-sigma offset of 0.223 mV while maintaining precise calibration. Among the calibration algorithms, the window algorithm performs better than the accelerated calibration. This is mainly because the window algorithm considers noise-induced output oscillations, ensuring consistent calibration across all designs. This work provides insights into the trade-offs between energy, precision, and area in dynamic comparator designs, offering strategies to enhance offset calibration. Full article

(This article belongs to the Special Issue Analog/Mixed-Signal Integrated Circuit Design)

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25 pages, 5557 KiB

Open AccessArticle

A Comprehensive Analysis of Losses and Efficiency in a Buck ZCS Quasi-Resonant DC/DC Converter

by Nikolay Hinov and Tsvetana Grigorova

J. Low Power Electron. Appl. 2025, 15(2), 34; https://doi.org/10.3390/jlpea15020034 - 2 Jun 2025

Cited by 1

As power electronics continue to advance, the demand for highly efficient and low-loss DC/DC converters has grown significantly. This article comprehensively analyses ZCS quasi-resonant switch cell losses and efficiency in buck L-type zero-current switching (ZCS) quasi-resonant DC/DC converters. The main part of the [...] Read more.

As power electronics continue to advance, the demand for highly efficient and low-loss DC/DC converters has grown significantly. This article comprehensively analyses ZCS quasi-resonant switch cell losses and efficiency in buck L-type zero-current switching (ZCS) quasi-resonant DC/DC converters. The main part of the study includes a comparative analysis of conduction losses in semiconductor switches of conventional PWM buck converters and zero-current switching (ZCS) quasi-resonant buck converters (L-type), utilizing both specific and generalized design equations. Novel coefficients are introduced that enable the evaluation of static power losses in the classical buck converter compared to those in L-type ZCS buck quasi-resonant converters under identical conditions. The article also discusses design considerations aimed at minimizing static losses. An L-type half-mode zero-current switching (ZCS) buck quasi-resonant DC/DC converter (QRC) is implemented to verify the analytical results. Various simulations were conducted using PSpice in the Texas Instruments simulation environment, along with experimental studies at different switching frequencies and load conditions. The proposed methodology integrates both analytical and simulation approaches to analyze energy losses and key parameters influencing the converter’s efficiency. The obtained results show that the relative error between the analytical, simulation, and experimental results is below 5%. Full article

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18 pages, 5430 KiB

Open AccessArticle

Elbow Joint Angle Estimation Using a Low-Cost and Low-Power Single Inertial Device for Daily Home-Based Self-Rehabilitation

by Manon Fourniol, Rémy Vauché, Guillaume Rao, Eric Watelain and Edith Kussener

J. Low Power Electron. Appl. 2025, 15(2), 33; https://doi.org/10.3390/jlpea15020033 - 19 May 2025

In the context of aging populations, it has become necessary to develop new methods and devices for the daily home-based self-rehabilitation of elderly people. To this end, this paper proposes and evaluates the use of an easy-to-use single battery-powered device including a 3D [...] Read more.

In the context of aging populations, it has become necessary to develop new methods and devices for the daily home-based self-rehabilitation of elderly people. To this end, this paper proposes and evaluates the use of an easy-to-use single battery-powered device including a 3D accelerometer and a 3D gyroscope, where light algorithms, such as the complementary filter and the Kalman filter, are implemented to estimate the elbow joint angle. During experiments, a robotic arm and a human arm were used to obtain an error interval for each tested algorithm; the robotic arm allows for reproducible movements and reproducible results, which allows us to independently verify the impact of parameters such as the sensor’s movement speed on the algorithm precision. The experimental results show that the algorithm that uses only accelerometer data is one of the most relevant since it allows us to obtain a Root Mean Square Error between 1.83° and 5.52° at a sensor data rate of 100 Hz, which is similar to the results obtained using the data fusion algorithms tested. Nevertheless, it has a lower power consumption since it requires only 58 cycles when using an ARM Cortex-M4 processor (which is lower than that of the other data fusion algorithms tested by a factor of at least two), and it does not necessitate the additional sensor required by the other data fusion algorithms tested (such as a gyroscope or a magnetometer). The algorithm using only accelerometer data also seems to be the algorithm with the lowest power consumption and should be preferred. Moreover, its power consumption can be reduced by more than the increase in the error when reducing the rate of the data output by the sensor. In this work, a reduction in the data rate from 100 Hz to 10 Hz increased the RMSE by a factor of 1.8 but could reduce the power consumption associated with the sensor and the algorithm’s computation by a factor of 10. Finally, the experimental results show that the higher the speed of the sensor’s motion, the higher the error obtained using only accelerometer data. Nevertheless, the algorithm that uses only accelerometer data remains well suited to rehabilitation exercises or mobility evaluations since the speed of the sensor’s movement is also moderate. Full article

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12 pages, 2371 KiB

Open AccessCommunication

A 0.8 V Low-Power Wide-Tuning-Range CMOS VCO for 802.11ac and IoT C-Band Applications

by Jung-Jen Hsu, Yao-Chian Lin and Stephen J. H. Yang

J. Low Power Electron. Appl. 2025, 15(2), 32; https://doi.org/10.3390/jlpea15020032 - 16 May 2025

This paper presents a 0.8 V low-power CMOS voltage-controlled oscillator (VCO) with a wide tuning range, fabricated using a TSMC 0.18 μm process. The proposed design incorporates body-biasing techniques and an optimized varactor structure to achieve a tuning range of 1124 MHz (5.829–4.705 [...] Read more.

This paper presents a 0.8 V low-power CMOS voltage-controlled oscillator (VCO) with a wide tuning range, fabricated using a TSMC 0.18 μm process. The proposed design incorporates body-biasing techniques and an optimized varactor structure to achieve a tuning range of 1124 MHz (5.829–4.705 GHz) and low phase noise of −117.6 dBc/Hz at a 1 MHz offset. Operating at an ultra-low supply voltage of 0.8 V, the VCO consumes only 3.4 mW, demonstrating excellent power efficiency. A buffer circuit is also employed to enhance output symmetry and suppress flicker noise without introducing additional control complexity. With a figure-of-merit (FOM) of −188.6 dBc/Hz and a wide tuning range of 22.2%, the proposed VCO is well-suited for modern low-power communication systems, including 802.11ac, 5G transceivers, satellite links, and compact IoT devices. Full article

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17 pages, 869 KiB

Open AccessArticle

Impact of Mother Wavelet Choice on Fast Wavelet Transform Performances for Integrated ST Segment Monitoring

by Béatrice Guénégo, Caroline Lelandais-Perrault, Emilie Avignon-Meseldzija, Gérard Sou and Philippe Bénabès

J. Low Power Electron. Appl. 2025, 15(2), 31; https://doi.org/10.3390/jlpea15020031 - 12 May 2025

The ST segment of an ECG signal is a feature that changes in the event of cardiac ischemia, a condition that is an early warning sign of myocardial infarction. Being able to monitor this feature in real time would be highly beneficial for [...] Read more.

The ST segment of an ECG signal is a feature that changes in the event of cardiac ischemia, a condition that is an early warning sign of myocardial infarction. Being able to monitor this feature in real time would be highly beneficial for preventing recurrent heart attacks. However, to be worn daily, such a monitoring device must be extremely miniaturized, down to the scale of a single integrated circuit. Currently, it is possible to integrate a heart rate detector, but, to our knowledge, no existing work presents a chip capable of detecting ST segment deviation. This is mainly because accurate ST segment measurement requires low-distortion signal processing, as specified in the International Electrotechnical Commission (IEC) standard. At the same time, the system is required to filter out baseline wander, whose frequency components may partially overlap with those of the ST segment. In this study, we relied on wavelet-based analysis and reconstruction to compare several wavelet types. We optimized their hyperparameters to minimize implementation complexity while satisfying the low-distortion constraints. We also propose an ASIC-oriented architecture and evaluate its post-layout performance in terms of area and power consumption. The post-layout results indicate that the Daubechies wavelet db3 offers the best trade-off among the evaluated configurations. It exhibits an area utilization of

1.18

mm² and a post-layout power consumption of

4.89

μ

W, while preserving the ST segment in compliance with the IEC standard, thanks in particular to its effective baseline wandering filtering of

6.9

dB. These results demonstrate the feasibility of embedding automatic ST segment extraction on-chip. Full article

(This article belongs to the Topic Advanced Integrated Circuit Design and Application)

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14 pages, 9820 KiB

Open AccessArticle

Design and Analysis of an Ultra-Wideband High-Precision Active Phase Shifter in 0.18 μm SiGe BiCMOS Technology

by Hao Jiang, Zenglong Zhao, Nengxu Zhu and Fanyi Meng

J. Low Power Electron. Appl. 2025, 15(2), 30; https://doi.org/10.3390/jlpea15020030 - 7 May 2025

This paper presents an active phase shifter for phased array system applications, implemented using 0.18 μm SiGe BiCMOS technology. The phase shifter circuit consists of a wideband quadrature signal generator, a vector modulator, an input balun, and an output balun. To enhance the [...] Read more.

This paper presents an active phase shifter for phased array system applications, implemented using 0.18 μm SiGe BiCMOS technology. The phase shifter circuit consists of a wideband quadrature signal generator, a vector modulator, an input balun, and an output balun. To enhance the bandwidth, a polyphase filter is employed as the quadrature signal generator, and a two-stage RC-CR filter with a highly symmetrical miniaturized layout is cascaded to create multiple resonant points, thus extending the phase shifter’s bandwidth to cover the required range. The gain of the variable-gain amplifier within the vector modulator is adjustable by varying the tail current, thereby enlarging the range of selectable points, improving phase-shifting accuracy, and reducing gain fluctuations. The measurement results show that the proposed active phase shifter achieves an RMS phase error of less than 2° and a gain variation ranging from −1.2 dB to 0.1 dB across a 20 GHz to 30 GHz bandwidth at room temperature. The total chip area is 0.4 mm², with a core area of 0.165 mm², and consumes 19.5 mW of power from a 2.5 V supply. Full article

(This article belongs to the Topic Advanced Integrated Circuit Design and Application)

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