Journal of Low Power Electronics and Applications

13 pages, 2575 KiB

Open AccessArticle

Simulation of Propagation Characteristics and Field Distribution in Cylindrical Photonic Crystals Composed of Near-Zero Materials and Metal

by Zhihao Xu, Dan Zhang, Rongkang Xuan, Shenxiang Yang and Na Wang

J. Low Power Electron. Appl. 2025, 15(3), 44; https://doi.org/10.3390/jlpea15030044 (registering DOI) - 31 Jul 2025

Abstract

This study investigates the propagation characteristics and field distribution of photonic crystals composed of epsilon-near-zero (ENZ) materials and metal cylinders. The research reveals that the cutoff frequency of the photonic crystal formed by combining metal cylinders with an ENZ background is independent of [...] Read more.

This study investigates the propagation characteristics and field distribution of photonic crystals composed of epsilon-near-zero (ENZ) materials and metal cylinders. The research reveals that the cutoff frequency of the photonic crystal formed by combining metal cylinders with an ENZ background is independent of the volume fraction of the metal cylinders and exhibits a stop-band profile within the measured frequency range. This unique behavior is attributed to the scattering of long-wavelength light when the wavelength approaches the effective wavelength range of the ENZ material. Taking advantage of this feature, the study selectively filters specific wavelength ranges from the mid-frequency band by varying the ratio of cylinder radius to lattice constant (R/a). Decreasing the R/a ratio enables the design of waveguide devices that operate over a broader guided wavelength range within the intermediate-frequency band. The findings emphasize the importance of the interaction between light and ENZ materials in shaping the transmission characteristics of photonic crystal structures. Full article

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13 pages, 2428 KiB

Open AccessArticle

A Novel Low-Power Bipolar DC–DC Converter with Voltage Self-Balancing

by Yangfan Liu, Qixiao Li and Zhongxuan Wang

J. Low Power Electron. Appl. 2025, 15(3), 43; https://doi.org/10.3390/jlpea15030043 - 24 Jul 2025

Abstract

Bipolar power supply can effectively reduce line losses and optimize power transmission. This paper proposes a low-power bipolar DC–DC converter with voltage self-balancing, which not only achieves bipolar output but also automatically balances the inter-pole voltage under load imbalance conditions without requiring additional [...] Read more.

Bipolar power supply can effectively reduce line losses and optimize power transmission. This paper proposes a low-power bipolar DC–DC converter with voltage self-balancing, which not only achieves bipolar output but also automatically balances the inter-pole voltage under load imbalance conditions without requiring additional voltage balancing control. This paper first elaborates on the derivation process of the proposed converter, then analyzes its working principles and performance characteristics. A 400 W experimental prototype is built to validate the correctness of the theoretical analysis and the voltage self-balancing capability. Finally, loss analysis and conclusions are presented. Full article

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17 pages, 493 KiB

Open AccessArticle

Microstrip Line Modeling Taking into Account Dispersion Using a General-Purpose SPICE Simulator

by Vadim Kuznetsov

J. Low Power Electron. Appl. 2025, 15(3), 42; https://doi.org/10.3390/jlpea15030042 - 22 Jul 2025

Abstract

XSPICE models for a generic transmission line, a microstrip line, and coupled microstrips are presented. The developed models extend general-purpose circuit simulation tools using RF circuits design features. The models could be used for circuit simulation in frequency, DC, and time domains for [...] Read more.

XSPICE models for a generic transmission line, a microstrip line, and coupled microstrips are presented. The developed models extend general-purpose circuit simulation tools using RF circuits design features. The models could be used for circuit simulation in frequency, DC, and time domains for any active or passive RF or microwave schematic (including microwave monolithic integrated circuits—MMICs) involving transmission lines. The presented models could be used with any circuit simulation backend supporting XSPICE extensions and could be integrated without patching the core simulator code. The presented XSPICE models for microstrip lines take into account the frequency dependency of characteristic impedance and dispersion. The models were designed using open-source circuit simulation software. This study provides a practical example of the low-noise RF amplifier (LNA) design with Ngspice simulation backend using the proposed models. Full article

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23 pages, 4087 KiB

Open AccessArticle

Low-Voltage Ride Through Capability Analysis of a Reduced-Size DFIG Excitation Utilized in Split-Shaft Wind Turbines

by Rasoul Akbari and Afshin Izadian

J. Low Power Electron. Appl. 2025, 15(3), 41; https://doi.org/10.3390/jlpea15030041 - 21 Jul 2025

Abstract

Split-shaft wind turbines decouple the turbine’s shaft from the generator’s shaft, enabling several modifications in the drivetrain. One of the significant achievements of a split-shaft drivetrain is the reduction in size of the excitation circuit. The grid-side converter is eliminated, and the rotor-side [...] Read more.

Split-shaft wind turbines decouple the turbine’s shaft from the generator’s shaft, enabling several modifications in the drivetrain. One of the significant achievements of a split-shaft drivetrain is the reduction in size of the excitation circuit. The grid-side converter is eliminated, and the rotor-side converter can safely reduce its size to a fraction of a full-size excitation. Therefore, this low-power-rated converter operates at low voltage and handles regular operations well. However, fault conditions may expose weaknesses in the converter and push it to its limits. This paper investigates the effects of the reduced-size rotor-side converter on the voltage ride-through capabilities required from all wind turbines. Four different protection circuits, including the active crowbar, active crowbar along a resistor–inductor circuit (C-RL), series dynamic resistor (SDR), and new-bridge fault current limiter (NBFCL), are employed, and their effects are investigated and compared. Wind turbine controllers are also utilized to reduce the impact of faults on the power electronic converters. One effective method is to store excess energy in the generator’s rotor. The proposed low-voltage ride-through strategies are simulated in MATLAB Simulink (2022b) to validate the results and demonstrate their effectiveness and functionality. Full article

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16 pages, 2270 KiB

Open AccessArticle

Performance Evaluation of FPGA, GPU, and CPU in FIR Filter Implementation for Semiconductor-Based Systems

by Muhammet Arucu and Teodor Iliev

J. Low Power Electron. Appl. 2025, 15(3), 40; https://doi.org/10.3390/jlpea15030040 - 21 Jul 2025

Abstract

This study presents a comprehensive performance evaluation of field-programmable gate array (FPGA), graphics processing unit (GPU), and central processing unit (CPU) platforms for implementing finite impulse response (FIR) filters in semiconductor-based digital signal processing (DSP) systems. Utilizing a standardized FIR filter designed with [...] Read more.

This study presents a comprehensive performance evaluation of field-programmable gate array (FPGA), graphics processing unit (GPU), and central processing unit (CPU) platforms for implementing finite impulse response (FIR) filters in semiconductor-based digital signal processing (DSP) systems. Utilizing a standardized FIR filter designed with the Kaiser window method, we compare computational efficiency, latency, and energy consumption across the ZYNQ XC7Z020 FPGA, Tesla K80 GPU, and Arm-based CPU, achieving processing times of 0.004 s, 0.008 s, and 0.107 s, respectively, with FPGA power consumption of 1.431 W and comparable energy profiles for GPU and CPU. The FPGA is 27 times faster than the CPU and 2 times faster than the GPU, demonstrating its suitability for low-latency DSP tasks. A detailed analysis of resource utilization and scalability underscores the FPGA’s reconfigurability for optimized DSP implementations. This work provides novel insights into platform-specific optimizations, addressing the demand for energy-efficient solutions in edge computing and IoT applications, with implications for advancing sustainable DSP architectures. Full article

(This article belongs to the Topic Advanced Integrated Circuit Design and Application)

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17 pages, 4316 KiB

Open AccessArticle

A Coverage Path Planning Method with Energy Optimization for UAV Monitoring Tasks

by Zhengqiang Xiong, Chang Han, Xiaoliang Wang and Li Gao

J. Low Power Electron. Appl. 2025, 15(3), 39; https://doi.org/10.3390/jlpea15030039 - 9 Jul 2025

Abstract

Coverage path planning solves the problem of moving an effector over all points within a specific region with effective routes. Most existing studies focus on geometric constraints, often overlooking robot-specific features, like the available energy, weight, maximum speed, sensor resolution, etc. This paper [...] Read more.

Coverage path planning solves the problem of moving an effector over all points within a specific region with effective routes. Most existing studies focus on geometric constraints, often overlooking robot-specific features, like the available energy, weight, maximum speed, sensor resolution, etc. This paper proposes a coverage path planning algorithm for Unmanned Aerial Vehicles (UAVs) that minimizes energy consumption while satisfying a set of other requirements, such as coverage and observation resolution. To deal with these issues, we propose a novel energy-optimal coverage path planning framework for monitoring tasks. Firstly, the 3D terrain’s spatial characteristics are digitized through a combination of parametric modeling and meshing techniques. To accurately estimate actual energy expenditure along a segmented trajectory, a power estimation module is introduced, which integrates dynamic feasibility constraints into the energy computation. Utilizing a Digital Surface Model (DSM), a global energy consumption map is generated by constructing a weighted directed graph over the terrain. Subsequently, an energy-optimal coverage path is derived by applying a Genetic Algorithm (GA) to traverse this map. Extensive simulation results validate the superiority of the proposed approach compared to existing methods. Full article

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16 pages, 5447 KiB

Open AccessArticle

A Gate Driver for Crosstalk Suppression of eGaN HEMT Power Devices

by Longsheng Zhang, Kaihong Wang, Shilong Guo and Binxin Zhu

J. Low Power Electron. Appl. 2025, 15(3), 38; https://doi.org/10.3390/jlpea15030038 - 6 Jul 2025

Abstract

The eGaN HEMT power devices face serious crosstalk problems when applied to high-frequency bridge circuits, thereby limiting the switching performance of these devices. To address this issue, a gate driver is proposed in this paper that can suppress both positive and negative crosstalk [...] Read more.

The eGaN HEMT power devices face serious crosstalk problems when applied to high-frequency bridge circuits, thereby limiting the switching performance of these devices. To address this issue, a gate driver is proposed in this paper that can suppress both positive and negative crosstalk of eGaN HEMT power devices, offering the advantages of simple control and easy integration. The basic idea is to suppress positive crosstalk by constructing a negative voltage capacitor, and to suppress negative crosstalk by reducing the impedance of the gate loop. To verify the capability of the proposed gate driver, double-pulse and synchronous Buck test platforms are constructed. The experimental results clearly demonstrate that the proposed gate driver reduces the positive and negative crosstalk spikes by 2.03 V and 1.54 V, respectively, ensuring that the positive and negative crosstalk spikes fall within a safe operating range. Additionally, the turn-off speed of the device is enhanced, leading to a reduction in switching loss. Full article

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29 pages, 2379 KiB

Open AccessArticle

An Analog Architecture and Algorithm for Efficient Convolutional Neural Network Image Computation

by Jennifer Hasler and Praveen Raj Ayyappan

J. Low Power Electron. Appl. 2025, 15(3), 37; https://doi.org/10.3390/jlpea15030037 - 25 Jun 2025

Abstract

This article presents an energy-efficient IC architecture implementation of an analog image-processing ML system, where the primary issue is analog architecture development for existing energy-efficient analog computing devices. An architecture is developed for image classification, transforming a typical imager input into a classified [...] Read more.

This article presents an energy-efficient IC architecture implementation of an analog image-processing ML system, where the primary issue is analog architecture development for existing energy-efficient analog computing devices. An architecture is developed for image classification, transforming a typical imager input into a classified result using a particular NN algorithm, a convolutional NN (ConvNN). These efforts show the need to continue to develop energy-efficient analog architectures alongside efficient analog circuits to fully exploit the opportunities of analog computing for system application. Full article

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13 pages, 31731 KiB

Open AccessArticle

Optimized Coupling Coil Geometry for High Wireless Power Transfer Efficiency in Mobile Devices

by Fahad M. Alotaibi

J. Low Power Electron. Appl. 2025, 15(2), 36; https://doi.org/10.3390/jlpea15020036 - 17 Jun 2025

Abstract

Wireless Power Transfer (WPT) enables efficient, contactless charging for mobile devices by eliminating mechanical connectors and wiring, thereby enhancing user experience and device longevity. However, conventional WPT systems remain prone to performance issues such as coil misalignment, resonance instability, and thermal losses. Addressing [...] Read more.

Wireless Power Transfer (WPT) enables efficient, contactless charging for mobile devices by eliminating mechanical connectors and wiring, thereby enhancing user experience and device longevity. However, conventional WPT systems remain prone to performance issues such as coil misalignment, resonance instability, and thermal losses. Addressing these challenges involves designing coil geometries that operate at lower resonant frequencies to strengthen magnetic coupling and decrease resistance. This work introduces a WPT system with a performance-driven coil design aimed at maximizing magnetic coupling and mutual inductance between the transmitting (Tx) and receiving (Rx) coils in mobile devices. Due to the nonlinear behavior of magnetic flux and the high computational cost of simulations, exploring the full design space for coils using ANSYS Maxwell becomes impractical. To address this complexity, a machine learning (ML)-based optimization framework is developed to efficiently navigate the design space. The framework integrates a hybrid sequential neural network and multivariate regression model to optimize coil winding and ferrite core geometry. The optimized structure achieves a mutual inductance of 12.52

μ

H with a conventional core, outperforming many existing ML models. Finite element simulations and experimental results validate the robustness of the method, which offers a scalable solution for efficient wireless charging in compact, misalignment-prone environments. Full article

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19 pages, 8803 KiB

Open AccessArticle

An Accurate and Low-Complexity Offset Calibration Methodology for Dynamic Comparators

by Juan Cuenca, Benjamin Zambrano, Esteban Garzón, Luis Miguel Prócel and Marco Lanuzza

J. Low Power Electron. Appl. 2025, 15(2), 35; https://doi.org/10.3390/jlpea15020035 - 2 Jun 2025

Abstract

Dynamic comparators play an important role in electronic systems, requiring high accuracy, low power consumption, and minimal offset voltage. This work proposes an accurate and low-complexity offset calibration design based on a capacitive load approach. It was designed using a 65 nm CMOS [...] Read more.

Dynamic comparators play an important role in electronic systems, requiring high accuracy, low power consumption, and minimal offset voltage. This work proposes an accurate and low-complexity offset calibration design based on a capacitive load approach. It was designed using a 65 nm CMOS technology and comprehensively evaluated under Monte Carlo simulations and PVT variations. The proposed scheme was built using MIM capacitors and transistor-based capacitors, and it includes Verilog-based calibration algorithms. The proposed offset calibration is benchmarked, in terms of precision, calibration time, energy consumption, delay, and area, against prior calibration techniques: current injection via gate biasing by a charge pump circuit and current injection via parallel transistors. The evaluation of the offset calibration schemes relies on Analog/Mixed-Signal (AMS) simulations, ensuring accurate evaluation of digital and analog domains. The charge pump method achieved the best Energy-Delay Product (EDP) at the cost of lower long-term accuracy, mainly because of its capacitor leakage. The proposed scheme demonstrated superior performance in offset reduction, achieving a one-sigma offset of 0.223 mV while maintaining precise calibration. Among the calibration algorithms, the window algorithm performs better than the accelerated calibration. This is mainly because the window algorithm considers noise-induced output oscillations, ensuring consistent calibration across all designs. This work provides insights into the trade-offs between energy, precision, and area in dynamic comparator designs, offering strategies to enhance offset calibration. Full article

(This article belongs to the Special Issue Analog/Mixed-Signal Integrated Circuit Design)

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25 pages, 5557 KiB

Open AccessArticle

A Comprehensive Analysis of Losses and Efficiency in a Buck ZCS Quasi-Resonant DC/DC Converter

by Nikolay Hinov and Tsvetana Grigorova

J. Low Power Electron. Appl. 2025, 15(2), 34; https://doi.org/10.3390/jlpea15020034 - 2 Jun 2025

Cited by 1

Abstract

As power electronics continue to advance, the demand for highly efficient and low-loss DC/DC converters has grown significantly. This article comprehensively analyses ZCS quasi-resonant switch cell losses and efficiency in buck L-type zero-current switching (ZCS) quasi-resonant DC/DC converters. The main part of the [...] Read more.

As power electronics continue to advance, the demand for highly efficient and low-loss DC/DC converters has grown significantly. This article comprehensively analyses ZCS quasi-resonant switch cell losses and efficiency in buck L-type zero-current switching (ZCS) quasi-resonant DC/DC converters. The main part of the study includes a comparative analysis of conduction losses in semiconductor switches of conventional PWM buck converters and zero-current switching (ZCS) quasi-resonant buck converters (L-type), utilizing both specific and generalized design equations. Novel coefficients are introduced that enable the evaluation of static power losses in the classical buck converter compared to those in L-type ZCS buck quasi-resonant converters under identical conditions. The article also discusses design considerations aimed at minimizing static losses. An L-type half-mode zero-current switching (ZCS) buck quasi-resonant DC/DC converter (QRC) is implemented to verify the analytical results. Various simulations were conducted using PSpice in the Texas Instruments simulation environment, along with experimental studies at different switching frequencies and load conditions. The proposed methodology integrates both analytical and simulation approaches to analyze energy losses and key parameters influencing the converter’s efficiency. The obtained results show that the relative error between the analytical, simulation, and experimental results is below 5%. Full article

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18 pages, 5430 KiB

Open AccessArticle

Elbow Joint Angle Estimation Using a Low-Cost and Low-Power Single Inertial Device for Daily Home-Based Self-Rehabilitation

by Manon Fourniol, Rémy Vauché, Guillaume Rao, Eric Watelain and Edith Kussener

J. Low Power Electron. Appl. 2025, 15(2), 33; https://doi.org/10.3390/jlpea15020033 - 19 May 2025

Abstract

In the context of aging populations, it has become necessary to develop new methods and devices for the daily home-based self-rehabilitation of elderly people. To this end, this paper proposes and evaluates the use of an easy-to-use single battery-powered device including a 3D [...] Read more.

In the context of aging populations, it has become necessary to develop new methods and devices for the daily home-based self-rehabilitation of elderly people. To this end, this paper proposes and evaluates the use of an easy-to-use single battery-powered device including a 3D accelerometer and a 3D gyroscope, where light algorithms, such as the complementary filter and the Kalman filter, are implemented to estimate the elbow joint angle. During experiments, a robotic arm and a human arm were used to obtain an error interval for each tested algorithm; the robotic arm allows for reproducible movements and reproducible results, which allows us to independently verify the impact of parameters such as the sensor’s movement speed on the algorithm precision. The experimental results show that the algorithm that uses only accelerometer data is one of the most relevant since it allows us to obtain a Root Mean Square Error between 1.83° and 5.52° at a sensor data rate of 100 Hz, which is similar to the results obtained using the data fusion algorithms tested. Nevertheless, it has a lower power consumption since it requires only 58 cycles when using an ARM Cortex-M4 processor (which is lower than that of the other data fusion algorithms tested by a factor of at least two), and it does not necessitate the additional sensor required by the other data fusion algorithms tested (such as a gyroscope or a magnetometer). The algorithm using only accelerometer data also seems to be the algorithm with the lowest power consumption and should be preferred. Moreover, its power consumption can be reduced by more than the increase in the error when reducing the rate of the data output by the sensor. In this work, a reduction in the data rate from 100 Hz to 10 Hz increased the RMSE by a factor of 1.8 but could reduce the power consumption associated with the sensor and the algorithm’s computation by a factor of 10. Finally, the experimental results show that the higher the speed of the sensor’s motion, the higher the error obtained using only accelerometer data. Nevertheless, the algorithm that uses only accelerometer data remains well suited to rehabilitation exercises or mobility evaluations since the speed of the sensor’s movement is also moderate. Full article

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12 pages, 2371 KiB

Open AccessCommunication

A 0.8 V Low-Power Wide-Tuning-Range CMOS VCO for 802.11ac and IoT C-Band Applications

by Jung-Jen Hsu, Yao-Chian Lin and Stephen J. H. Yang

J. Low Power Electron. Appl. 2025, 15(2), 32; https://doi.org/10.3390/jlpea15020032 - 16 May 2025

Abstract

This paper presents a 0.8 V low-power CMOS voltage-controlled oscillator (VCO) with a wide tuning range, fabricated using a TSMC 0.18 μm process. The proposed design incorporates body-biasing techniques and an optimized varactor structure to achieve a tuning range of 1124 MHz (5.829–4.705 [...] Read more.

This paper presents a 0.8 V low-power CMOS voltage-controlled oscillator (VCO) with a wide tuning range, fabricated using a TSMC 0.18 μm process. The proposed design incorporates body-biasing techniques and an optimized varactor structure to achieve a tuning range of 1124 MHz (5.829–4.705 GHz) and low phase noise of −117.6 dBc/Hz at a 1 MHz offset. Operating at an ultra-low supply voltage of 0.8 V, the VCO consumes only 3.4 mW, demonstrating excellent power efficiency. A buffer circuit is also employed to enhance output symmetry and suppress flicker noise without introducing additional control complexity. With a figure-of-merit (FOM) of −188.6 dBc/Hz and a wide tuning range of 22.2%, the proposed VCO is well-suited for modern low-power communication systems, including 802.11ac, 5G transceivers, satellite links, and compact IoT devices. Full article

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17 pages, 869 KiB

Open AccessArticle

Impact of Mother Wavelet Choice on Fast Wavelet Transform Performances for Integrated ST Segment Monitoring

by Béatrice Guénégo, Caroline Lelandais-Perrault, Emilie Avignon-Meseldzija, Gérard Sou and Philippe Bénabès

J. Low Power Electron. Appl. 2025, 15(2), 31; https://doi.org/10.3390/jlpea15020031 - 12 May 2025

Abstract

The ST segment of an ECG signal is a feature that changes in the event of cardiac ischemia, a condition that is an early warning sign of myocardial infarction. Being able to monitor this feature in real time would be highly beneficial for [...] Read more.

The ST segment of an ECG signal is a feature that changes in the event of cardiac ischemia, a condition that is an early warning sign of myocardial infarction. Being able to monitor this feature in real time would be highly beneficial for preventing recurrent heart attacks. However, to be worn daily, such a monitoring device must be extremely miniaturized, down to the scale of a single integrated circuit. Currently, it is possible to integrate a heart rate detector, but, to our knowledge, no existing work presents a chip capable of detecting ST segment deviation. This is mainly because accurate ST segment measurement requires low-distortion signal processing, as specified in the International Electrotechnical Commission (IEC) standard. At the same time, the system is required to filter out baseline wander, whose frequency components may partially overlap with those of the ST segment. In this study, we relied on wavelet-based analysis and reconstruction to compare several wavelet types. We optimized their hyperparameters to minimize implementation complexity while satisfying the low-distortion constraints. We also propose an ASIC-oriented architecture and evaluate its post-layout performance in terms of area and power consumption. The post-layout results indicate that the Daubechies wavelet db3 offers the best trade-off among the evaluated configurations. It exhibits an area utilization of

1.18

mm² and a post-layout power consumption of

4.89

μ

W, while preserving the ST segment in compliance with the IEC standard, thanks in particular to its effective baseline wandering filtering of

6.9

dB. These results demonstrate the feasibility of embedding automatic ST segment extraction on-chip. Full article

(This article belongs to the Topic Advanced Integrated Circuit Design and Application)

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14 pages, 9820 KiB

Open AccessArticle

Design and Analysis of an Ultra-Wideband High-Precision Active Phase Shifter in 0.18 μm SiGe BiCMOS Technology

by Hao Jiang, Zenglong Zhao, Nengxu Zhu and Fanyi Meng

J. Low Power Electron. Appl. 2025, 15(2), 30; https://doi.org/10.3390/jlpea15020030 - 7 May 2025

Abstract

This paper presents an active phase shifter for phased array system applications, implemented using 0.18 μm SiGe BiCMOS technology. The phase shifter circuit consists of a wideband quadrature signal generator, a vector modulator, an input balun, and an output balun. To enhance the [...] Read more.

This paper presents an active phase shifter for phased array system applications, implemented using 0.18 μm SiGe BiCMOS technology. The phase shifter circuit consists of a wideband quadrature signal generator, a vector modulator, an input balun, and an output balun. To enhance the bandwidth, a polyphase filter is employed as the quadrature signal generator, and a two-stage RC-CR filter with a highly symmetrical miniaturized layout is cascaded to create multiple resonant points, thus extending the phase shifter’s bandwidth to cover the required range. The gain of the variable-gain amplifier within the vector modulator is adjustable by varying the tail current, thereby enlarging the range of selectable points, improving phase-shifting accuracy, and reducing gain fluctuations. The measurement results show that the proposed active phase shifter achieves an RMS phase error of less than 2° and a gain variation ranging from −1.2 dB to 0.1 dB across a 20 GHz to 30 GHz bandwidth at room temperature. The total chip area is 0.4 mm², with a core area of 0.165 mm², and consumes 19.5 mW of power from a 2.5 V supply. Full article

(This article belongs to the Topic Advanced Integrated Circuit Design and Application)

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14 pages, 16692 KiB

Open AccessArticle

A New Type of DC-DC Buck Converter with Soft Start Function and Reduced Voltage Stress

by Xin Wang, Zishuo Li, Zhen Lin and Fanyi Meng

J. Low Power Electron. Appl. 2025, 15(2), 29; https://doi.org/10.3390/jlpea15020029 - 7 May 2025

Abstract

This paper introduces a novel topology called the dual-path step-down converter with auxiliary switches to minimize voltage stress and enable wide voltage conversion ranges. The proposed dual-path step-down converter with auxiliary switches, which uses an inductor and flying capacitor as power conversion components, [...] Read more.

This paper introduces a novel topology called the dual-path step-down converter with auxiliary switches to minimize voltage stress and enable wide voltage conversion ranges. The proposed dual-path step-down converter with auxiliary switches, which uses an inductor and flying capacitor as power conversion components, helps to reduce the voltage stress on the power switches. By adding auxiliary switches, the proposed topology achieves the same voltage conversion ratio range as that of a conventional buck converter. Additionally, soft-start technology is incorporated to reduce the initial inrush current. Furthermore, this paper introduces a system-level design procedure for DC-DC converters. Designed for low-power applications with lithium-ion (Li-ion) batteries, the proposed converter steps down the battery voltage to 1.2 V. With a 380 nH inductor and a 5 µF output capacitor, the converter attains a peak efficiency of 90% under the conditions of 2.7 V to 1.2 V conversion. Full article

(This article belongs to the Topic Application of Innovative Power Electronic Technologies, 2nd Edition)

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14 pages, 3868 KiB

Open AccessArticle

Analytical Implementation of Electron–Phonon Scattering in a Schottky Barrier CNTFET Model

by Ibrahim L. Abdalla, Fatma A. Matter, Ahmed A. Afifi, Mohamed I. Ibrahem, Hesham F. A. Hamed and Eslam S. El-Mokadem

J. Low Power Electron. Appl. 2025, 15(2), 28; https://doi.org/10.3390/jlpea15020028 - 2 May 2025

Abstract

This paper elaborates on the proposal of a new analytical model for a non-ballistic transport scenario for Schottky barrier carbon nanotube field effect transistors (SB-CNTFETs). The non-ballistic transport scenario depends on incorporating the effects of acoustic phonon (A-Ph) and optical phonon (O-Ph) electron [...] Read more.

This paper elaborates on the proposal of a new analytical model for a non-ballistic transport scenario for Schottky barrier carbon nanotube field effect transistors (SB-CNTFETs). The non-ballistic transport scenario depends on incorporating the effects of acoustic phonon (A-Ph) and optical phonon (O-Ph) electron scattering mechanisms. The analytical model is rooted in the solution of the Landauer integral equation, which is modified to account for non-ballistic transport through a set of approximations applied to the Wentzel–Kramers–Brillouin (WKB) transmission probability and the Fermi–Dirac distribution function. Our proposed model was simulated to evaluate the total current and transconductance, considering scenarios both with and without the electron–phonon scattering effect. The simulation results revealed a substantial decrease of approximately 78.6% in both total current and transconductance due to electron–phonon scattering. In addition, we investigated the impact of acoustic phonon (A-Ph) and optical phonon (O-Ph) scattering on the drain current under various conditions, including different temperatures, gate lengths, and nanotube chiralities. This comprehensive analysis helps in understanding how these parameters influence device performance. Compared with experimental data, the model’s simulation results demonstrate a high degree of agreement. Furthermore, our fully analytical model achieves a significantly faster runtime, clocking in at around 2.726 s. This validation underscores the model’s accuracy and reliability in predicting the behavior of SB-CNTFETs under non-ballistic conditions. Full article

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15 pages, 1313 KiB

Open AccessArticle

mTanh: A Low-Cost Inkjet-Printed Vanishing Gradient Tolerant Activation Function

by Shahrin Akter and Mohammad Rafiqul Haider

J. Low Power Electron. Appl. 2025, 15(2), 27; https://doi.org/10.3390/jlpea15020027 - 2 May 2025

Abstract

Inkjet-printed circuits on flexible substrates are rapidly emerging as a key technology in flexible electronics, driven by their minimal fabrication process, cost-effectiveness, and environmental sustainability. Recent advancements in inkjet-printed devices and circuits have broadened their applications in both sensing and computing. Building on [...] Read more.

Inkjet-printed circuits on flexible substrates are rapidly emerging as a key technology in flexible electronics, driven by their minimal fabrication process, cost-effectiveness, and environmental sustainability. Recent advancements in inkjet-printed devices and circuits have broadened their applications in both sensing and computing. Building on this progress, this work has developed a nonlinear computational element coined as mTanh to serve as an activation function in neural networks. Activation functions are essential in neural networks as they introduce nonlinearity, enabling machine learning models to capture complex patterns. However, widely used functions such as Tanh and sigmoid often suffer from the vanishing gradient problem, limiting the depth of neural networks. To address this, alternative functions like ReLU and Leaky ReLU have been explored, yet these also introduce challenges such as the dying ReLU issue, bias shifting, and noise sensitivity. The proposed mTanh activation function effectively mitigates the vanishing gradient problem, allowing for the development of deeper neural network architectures without compromising training efficiency. This study demonstrates the feasibility of mTanh as an activation function by integrating it into an Echo State Network to predict the Mackey–Glass time series signal. The results show that mTanh performs comparably to Tanh, ReLU, and Leaky ReLU in this task. Additionally, the vanishing gradient resistance of the mTanh function was evaluated by implementing it in a deep multi-layer perceptron model for Fashion MNIST image classification. The study indicates that mTanh enables the addition of 3–5 extra layers compared to Tanh and sigmoid, while exhibiting vanishing gradient resistance similar to ReLU. These results highlight the potential of mTanh as a promising activation function for deep learning models, particularly in flexible electronics applications. Full article

(This article belongs to the Special Issue Advancements in Low-Power Ubiquitous Sensing, Computing, and Communication Interfaces for IoT: Circuits, Systems, and Applications)

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10 pages, 2701 KiB

Open AccessArticle

Ultra-Thin Al₂O₃ Grown by PEALD for Low-Power Molybdenum Disulfide Field-Effect Transistors

by Shiwei Sun, Dinghao Ma, Boxi Ye, Guanshun Liu, Nanting Luo and Hao Huang

J. Low Power Electron. Appl. 2025, 15(2), 26; https://doi.org/10.3390/jlpea15020026 - 30 Apr 2025

Abstract

The lack of ultra-thin, controllable dielectric layers poses challenges for reducing power consumption in 2D FETs. In this study, plasma-enhanced atomic layer deposition was employed to fabricate a highly reliable, ultra-thin aluminum oxide (Al₂O₃) dielectric layer with a thickness [...] Read more.

The lack of ultra-thin, controllable dielectric layers poses challenges for reducing power consumption in 2D FETs. In this study, plasma-enhanced atomic layer deposition was employed to fabricate a highly reliable, ultra-thin aluminum oxide (Al₂O₃) dielectric layer with a thickness of 4 nm. The Al₂O₃ film grown on highly conductive silicon substrates demonstrated a maximum breakdown field of 5.98 MV/cm and a leakage current density as low as 2.48 × 10⁻⁷ A/cm² at 1 MV/cm. MoS₂ FETs incorporating this Al₂O₃ gate dielectric exhibited high-performance n-type characteristics at a low operating voltage of 1 V, achieving a subthreshold swing (SS) of 65 mV/dec, a threshold voltage (V_th) of −0.96 V, a high carrier mobility (μ) of 34.85 cm²·V⁻¹·s⁻¹, and an on/off current ratio exceeding 10⁶. These results highlight the potential of Al₂O₃ in enabling low-power 2D electronic devices for post-Moore applications. Full article

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Journal of Low Power Electronics and Applications

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