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Cryptography, Volume 5, Issue 3

2021 September - 10 articles

Cover Story: With the continuous scaling of CMOS technology, static power begins to dominate the power consumption of nanometer integrated circuits. In recent years, attacks exploiting static power (AESP) have been shown to be really effective in recovering secret keys from nanometer CMOS circuits, therefore representing a serious threat to cryptographic systems. In this work, we analyze the effectiveness of the standard-cell delay-based precharge logic (SC-DDPL) style in counteracting static power side-channel attacks, with experimental results on FPGA implementations. We show that SC-DDPL implementation allows a great improvement of all security metrics not only with respect to standard CMOS implementation, but also with respect to other state-of-the-art countermeasures such as WDDL and MDPL. View this paper.
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Cryptography - ISSN 2410-387X
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