A Reconfigurable 1x2 Photonic Digital Switch Controlled by an Externally Induced Metasurface

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

In this article, the authors discuss a method to utilize MMI structures in amorphous silicon in conjunction with so-called electrically induced metasurfaces in order to create ‘photonic logic gates’. The authors perform beam propagation and FDTD simulations to show that different configurations of the ‘MOS pixels’ lead to different logic gates. Furthermore, they create a large dataset of simulated results and use machine learning to classify the spatial patterns with the logic gate output showing at the end a demonstration of a cascaded switch. 

 

The idea that the authors propose is interesting and has merit. Simulation results are presented clearly. However, I have some reservations about the execution of the work. 

 

My main issue is that the machine learning algorithm is performed on the images of the simulation rather than the spatial pattern of the pixels. This doesn’t seem very helpful to me given that one does not have access to the simulation results when trying to implement this, but the spatial pattern. In other words, if one has a spatial pattern, one would first need to simulate it and then, using the simulation results, predict with the machine learning algorithm which logic gate it represents. In principle, if you already have to have the simulation results, you could just look at the images to see what the switching output of that particular result is. I think the work would be more impactful if the machine learning was used directly as a design tool.   

 

I would also like to point out that the use of the term ‘logic gate’ and ‘4-bit register’ from the authors is rather misleading because a logic gate technically is a device that takes two inputs of the same kind and gives one input of that kind based on some defined truth table. In this case, rather than a logic gate, I think the authors are describing a switch, which is also an important component in PICs, but this terminology can be misleading. Similarly, 'register' implies some kind of memory device, which is not the case for what the authors describe in this work. It can be more appropriately described as a cascaded switch perhaps.

 

The authors could also improve their presentation slightly by staying consistent with their acronyms (e.g. PIC in the introduction is redefined multiple times); as well as in the machine learning part by not including screenshots when describing the network architecture.

 

In conclusion, I do not believe the work should be published in its current state; however, I think the authors can consider rethinking the machine learning implementation to have the work be suitable for publication.

Author Response

Reviewer 1

We appreciate the time and effort that the reviewers have dedicated to providing a  valuable feedback on our manuscript and we are grateful for their insightful comments. We have been able to incorporate changes to reflect most of the suggestions and highlighted the changes within the manuscript.

 

In this article, the authors discuss a method to utilize MMI structures in amorphous silicon in conjunction with so-called electrically induced metasurfaces in order to create ‘photonic logic gates’. The authors perform beam propagation and FDTD simulations to show that different configurations of the ‘MOS pixels’ lead to different logic gates. Furthermore, they create a large dataset of simulated results and use machine learning to classify the spatial patterns with the logic gate output showing at the end a demonstration of a cascaded switch. The idea that the authors propose is interesting and has merit. Simulation results are presented clearly. However, I have some reservations about the execution of the work. 

 

My main issue is that the machine learning algorithm is performed on the images of the simulation rather than the spatial pattern of the pixels. This doesn’t seem very helpful to me given that one does not have access to the simulation results when trying to implement this, but the spatial pattern. In other words, if one has a spatial pattern, one would first need to simulate it and then, using the simulation results, predict with the machine learning algorithm which logic gate it represents. In principle, if you already have to have the simulation results, you could just look at the images to see what the switching output of that particular result is. I think the work would be more impactful if machine learning was used directly as a design tool.   

 

Answer:

The authors thank the reviewer for having put in light the low clarity of the discussion. The machine learning contribution is in the definition of the relationship between images and output, according to its most common use. The images used are of two kinds; the first is a B&W geometric representation of the input patterns, aiming at defining directly the relationship between pattern and output. The second kind are obtained after simulations, representing, the internal EM field, but in a one to one relationship with the pattern it generated. The results presented in the paper show that the learning phase is more effective in the second case. As a final result, the relationship between the input pattern and the output is defined, requiring no more simulations unless a deeper learning phase is desired. A clarification about this approach has been included in the manuscript in the abstract, im  linen 337-345,ll.ine  396,  448-461

  

I would also like to point out that the use of the term ‘logic gate’ and ‘4-bit register’ from the authors is rather misleading because a logic gate technically is a device that takes two inputs of the same kind and gives one input of that kind based on some defined truth table. In this case, rather than a logic gate, I think the authors are describing a switch, which is also an important component in PICs, but this terminology can be misleading. Similarly, 'register' implies some kind of memory device, which is not the case for what the authors describe in this work. It can be more appropriately described as a cascaded switch perhaps.

Answer:

We Thanks the reviewer for this correct consideration, we agree that some confusion can arise from the use of these terms. As a matter of facts, we plan as a future work to address similar structures with multiple input/output ports using the same method. Anyway, this manuscript use only the 1x2 function as a proof of concept for the method, so, we have changed the term “gate” to “digital optical switch” along the entire document, including in the title. This terminology is in agreement to the classic literature. We made a reference to some example [16,17}.  More recently other authors have called these kind of structures “function programmable waveguide engine (FPWE)”. We have inserted a new reference for this work (REF 19).

 

The authors could also improve their presentation slightly by staying consistent with their acronyms (e.g. PIC in the introduction is redefined multiple times); as well as in the machine learning part by not including screenshots when describing the network architecture.

Answer:

Thanks for detecting these repetitions, we have removed them and PIC is defined only once  in the introduction. Also, other acronyms (BPM, FDTD, MOS, ASICs, MMI) have been explicitly defined. A new figure for the network architecture has been inserted replacing the MATLAB screenshot.

 

In conclusion, I do not believe the work should be published in its current state; however, I think the authors can consider rethinking the machine learning implementation to have the work be suitable for publication.

We sincerely thank the accurate reading that reviewer has made of our manuscript and his/her effort to understand the research content. We hope that the new revised version may be able to fix the flaws detected.  

 

Reviewer 2 Report

Comments and Suggestions for Authors

# Review Suggestions for the Manuscript "A reconfigurable 1x2 photonic logic gate controlled by an externally induced metasurface"

 

The manuscript presents an interesting study on a reconfigurable 1x2 photonic logic gate controlled by an electrically controlled metasurface. The combination of MMI couplers and the metasurface concept shows potential for programmable photonic integrated circuits. However, there are several areas that need improvement for better clarity and scientific rigor.

 

1. - Provide more detailed comparisons between the proposed approach and existing similar devices in terms of performance metrics such as switching speed, power consumption, and integration complexity. This will help readers better understand the advantages of the presented work.

 - Cite more recent and relevant works in the field of programmable photonic integrated circuits to strengthen the background and motivation section.

2. - Include more experimental data or references regarding the thermo-optic coefficient measurement of a-Si:H to support the stated values.

 - Discuss in more depth the limitations of the electro-optic effect-based phase shifters and how the proposed metaMMI overcomes these limitations.

3. - Elaborate on the design process of the MMI dimensions and the choice of the MOS array configuration. Provide more theoretical analysis or simulation results justifying these choices.

 - Explain in more detail the approximation of the refractive index change due to charge accumulation and its potential errors or uncertainties.

4. - Describe the BeamProp method used for simulation in more detail, including its assumptions and limitations.

 - Discuss the significance of choosing 3 or 5 levels for power discretization and how it affects the accuracy and reliability of the results.

5. - Provide more information about the training process of the machine learning network, such as the number of training samples, the ratio of training to testing data, and the choice of hyperparameters.

 - Analyze the potential sources of errors in the machine learning classification and discuss possible ways to improve the accuracy further.

6. - Explain the physical meaning and implications of the error metric used in more detail.

 - Validate the statistical analysis results with more experimental or simulation data.

7. - Provide more details about the optimization process of the metasurfaces, including the objective function and the optimization algorithms used.

 - Discuss the scalability of the proposed approach for larger and more complex photonic circuits.

 

Overall, the manuscript has potential but requires significant revisions to enhance its scientific value and readability. Addressing these suggestions will help the authors present a more comprehensive and convincing study. 

Author Response

 

The manuscript presents an interesting study on a reconfigurable 1x2 photonic logic gate controlled by an electrically controlled metasurface. The combination of MMI couplers and the metasurface concept shows potential for programmable photonic integrated circuits. However, there are several areas that need improvement for better clarity and scientific rigor.

 We appreciate the time and effort that the reviewers have dedicated to providing a  valuable feedback on our manuscript and we are grateful for their insightful comments. We have been able to incorporate changes to reflect most of the suggestions and highlighted the changes within the manuscript.

 

1. - Provide more detailed comparisons between the proposed approach and existing similar devices in terms of performance metrics such as switching speed, power consumption, and integration complexity. This will help readers better understand the advantages of the presented work.

 - Cite more recent and relevant works in the field of programmable photonic integrated circuits to strengthen the background and motivation section.

We thank the reviewer for this comment. We have added a short discussion of some works about programmable PICs, that present an approach like the one discussed in our manuscript. 7 new references have been added [16-22].  The new text can be found in lines 66-79

2. - Include more experimental data or references regarding the thermo-optic coefficient measurement of a-Si:H to support the stated values.

We thank the reviewer for this comment. A discussion about the thermo-optic coefficient models and experiments has been added, including a figure where a-Si:H is compared to c-Si. The new text can be found in lines 143-184)

2A- Discuss in more depth the limitations of the electro-optic effect-based phase shifters and how the proposed metaMMI overcomes these limitations.

We thank the reviewer for this comment. A short discussion, including 2 more references [58,59], about the electro-optic effect and the metaMMI  has been added. The new text can be found in lines 244-276)

3. - Elaborate on the design process of the MMI dimensions and the choice of the MOS array configuration. Provide more theoretical analysis or simulation results justifying these choices.

We thank the reviewer for this comment. A short discussion about this point can be found in  line 189-211, 321-323 and 330-334

3A  - Explain in more detail the approximation of the refractive index change due to charge accumulation and its potential errors or uncertainties.

We thank the reviewer for this comment. A short discussion about the electro-optic effect and the metaMMI  has been added joining the answer to comment 2, including a new figure to better support the discussion.  The new text can be found in lines 244-276)

4. - Describe the BeamProp method used for simulation in more detail, including its assumptions and limitations.

Thanks for pointing out this missing discussion, once the database has been created by simulation means, we agree it is important to explain more in detail the possible limitation of the methos used. We added this explanation in lines 351-365

4A- Discuss the significance of choosing 3 or 5 levels for power discretization and how it affects the accuracy and reliability of the results.

We thank the reviewer for this comment. A discussion about the 3 and 5 levels approach has been added. The new text can be found in lines 380-391)

 

5. - Provide more information about the training process of the machine learning network, such as the number of training samples, the ratio of training to testing data, and the choice of hyperparameters.

Thanks for having noticed that such parameters were not explicated. Now such data have been reported. The input data size is 10⁵, 60% of which is used for training, 20% for validation in the training algorithm and 20% in the test phase. These fractions correspond to the most adopted partition and described as well balanced between the necessity of a large amount of data in the learning phase and a sufficiently large amount of test samples. This text has been added in lines 427-431

5A  - Analyze the potential sources of errors in the machine learning classification and discuss possible ways to improve accuracy further.

The use of machine learning for model definition in this case follows the most classical approach for image classification. This means that quality of the results depends on the same generic reasons of an AI based modelling: quality and meaningfully of the images, presence of common features for same class, size of the input data for training. The only independent changes it is possible to introduce is in the input set size. A text about this has been added in line 452-475, including the new figure 16.

6. - Explain the physical meaning and implications of the error metric used in more detail.

We thank the reviewer for this comment. The error metric adopted is a simple component wise comparison reporting 0 if both components have the same value 0 or 1, while yielding 1 once they are different, with the sign according to the matrix where the 1 is present, holding the same sign as in the difference expression. Conversely, it is possible to read directly the matrix based difference as a component wise comparison. In the mean square error expression, the sign is neglected, and the square error corresponds to a xor operation. From a statistical point of view, the error gives the (binary) probability that corresponding entries have different values. Once an average operation is performed, the values change from {0,1} to [0,1], yielding a probability value of entries differences. Small improvement in the explanation has been added to lines 500-502.

6A - Validate the statistical analysis results with more experimental or simulation data.

We thank the reviewer for this comment. A discussion about the validation of the statistical data have been added. The new text can be found in lines 528-538

7. - Provide more details about the optimization process of the metasurfaces, including the objective function and the optimization algorithms used.

We thank the reviewer for this comment.  The layout of the metasurface has been tailored to be able to produce output configurations for all the classes in analysis. So, the number of array elements, their size and position has been chosen in order to allocate  10% of the total number of simulated results in the most asymmetric classes (1,0) and (0,1). This new text can be found in lines 330-334

7A- Discuss the scalability of the proposed approach for larger and more complex photonic circuits.

We thank the reviewer for this comment. A comment about scalability has been added in the conclusions.

 

Overall, the manuscript has potential but requires significant revisions to enhance its scientific value and readability. Addressing these suggestions will help the authors present a more comprehensive and convincing study. 

Reviewer 3 Report

Comments and Suggestions for Authors

1. There are lots of typos that needs to be corrected. For example: The a,b,c,d is not at the bottom of the picture in Figure 8. The ‘onserve’ in line 187. ‘2×105 RSOFT simulation runs’ in line 251. The ‘0,5’ in line 240

2. There are two Figure 10 in your manuscript.

3. English abbreviations should be writen the full name when they first appears. E.g.: BPM and FDTD.

4. Figure 9 should be reorganized. It might be more appropriate to table it on the right.

5. Figure 8 Blurred.

6. In lines 239-241, ‘So, we have the level 0 representing the dark state (power between 0 and 0,5), the level 1 representing the light state (power higher than 0.35) and an intermediate level 2 (power between 0.5 and 0.35).’ Contradictory statement.

7. In lines 232-234, ‘Using the model and the layout described in section 2, it has been produced a database with 10⁵ simulations, obtained using the BeamProp method. Each simulation run has a different configuration of the ON-OFF distribution state of the electric contacts.’ There are little combination of the ON-OFF distribution state. How do you generate that much data?

8. In lines 289-292,’Power in the channel is subdivided in three levels (0, 1, and 2). Precision of the classification is 90%. Accuracy is 97%. 0 should be intended as “light off”, 1 as “light on”, while 2 represents an intermediate value. The four combinations of interest are (0,0); (1,0);(1,0); (1,1).’ What is the use of ‘2’? Where is it reflected?

9. Not sure what your logic gate does? You should give the true table of the 1x2 photonic logic gate.

Author Response

We thank the reviewer for his/her comments, highlighting unclear parts of the manuscript. We hope to have improved the paper and made it more robust, comprehensive and easier to understand by addressing these comments.

 

1. There are lots of typos that needs to be corrected. For example: The a,b,c,d is not at the bottom of the picture in Figure 8. The onserve in line 187.2×105 RSOFT simulation runs in line 251. The0,5 in line 240.

Thanks for pointing to these typos. We have corrected them.

 

2. There are two Figure 10 in your manuscript.

All the figures have been renumbered in order to eliminate this error. Also the text parts where the figures were discussed have been also updated to reflect the new numeration.

3. English abbreviations should be written the full name when they first appears. E.g.: BPM and FDTD.

BPM, FDTD MMI, MOS, ASICs have been written in full name in the beginning of the manuscript, when they appear the first time.

4. Figure 9 should be reorganized. It might be more appropriate to table it on the right.

Thanks for this comment. A new figure has been produced (now figure 14)

5. Figure 8 Blurred.

Thanks for pointing out this argument. As a matter of fact, the progressive blurring effect of the images is a visual characteristic of the ML analysis. Once this was not explained in the manuscript, to avoid any confusion on this point we have added a small text, explaining better the meaning of the blurring.  Lines 424-425.

 

6. In lines 239-241, ‘So, we have the level 0 representing the dark state (power between 0 and 0,5), the level 1 representing the light state (power higher than 0.35) and an intermediate level 2 (power between 0.5 and 0.35).’ Contradictory statement.

Thank you for pointing to this error, and for the attentive reading you made to our manuscript. We have corrected 0.5 to 0.05.

 

7. In lines 232-234, ‘Using the model and the layout described in section 2, it has been produced a database with 10⁵simulations, obtained using the BeamProp method. Each simulation run has a different configuration of the ON-OFF distribution state of the electric contacts.’ There are little combination of the ON-OFF distribution state. How do you generate that much data?

Thank you for pointing to this topic, which is central to the study. The array of the ON-OFF elements has a dimension of 3x20. So, the total number of possible configurations is 2⁶⁰ (roughly 10¹⁸). To avoid confusion it the readers, we made it more clear in lines 340-343.

 

8. In lines 289-292,’Power in the channel is subdivided in three levels (0, 1, and 2). Precision of the classification is 90%. Accuracy is 97%. 0 should be intended as “light off”, 1 as “light on”, while 2 represents an intermediate value. The four combinations of interest are (0,0); (1,0);(1,0); (1,1).’ What is the use of ‘2’? Where is it reflected?

The values “0” and “1” can be thought as the logical high and logical low in a binary logic family. The presence intermediate value “2”, which is the most commonly obtained, determine the non-usability of the configuration. Normally this result is obtained when we have some light intensity in the output, but not clearly enough do define a logical level.  We have added this clarification in the manuscript, lines 441-445

9. Not sure what your logic gate does? You should give the true table of the 1x2 photonic logic gate.

Thanks for this comment. Probably the term “logic gate” is not correct, so we have changed to digital optical switch, including in the title of the manuscript and supporting the new term with new rerferences [16-17]

Round 2

Reviewer 2 Report

Comments and Suggestions for Authors The careful editing of the manuscript improves its quality. I believe the manuscript is ready to be published as is.