Common-Ground-Type Single-Source High Step-Up Cascaded Multilevel Inverter for Transformerless PV Applications

Abstract

The cascaded multilevel inverter (CMI) is one type of common inverter in industrial applications. This type of inverter can be synthesized either as a symmetric configuration with several identical H-bridge (HB) cells or as an asymmetric configuration with non-identical HB cells. In photovoltaic (PV) applications with the CMI, the PV modules can be used to replace the isolated dc sources; however, this brings inter-module leakage currents. To tackle the issue, the single-source CMI is preferred. Furthermore, in a grid-tied PV system, the main constraint is the capacitive leakage current. This problem can be addressed by providing a common ground, which is shared by PV modules and the ac grid. This paper thus proposes a topology that fulfills the mentioned requirements and thus, CMI is a promising inverter with wide-ranging industrial uses, such as PV applications. The proposed CMI topology also features high boosting capability, fault current limiting, and a transformerless configuration. To demonstrate the capabilities of this CMI, simulations and experimental results are provided.

1. Introduction

Multilevel inverters (MIs) are attractive devices in many industrial applications. These devices can reduce the total harmonic distortion (THD), electromagnetic interference (EMI), dv/dt, switching frequency and voltage stress. One of the most regarded applications of MIs is PV application. The neutral point clamped converter (NPC) and cascaded multilevel inverter (CMI) are two types of multilevel inverters, which are popular in PV applications [1,2]. Between the two topologies, the CMI stands out for its modularity and high magnitude of the output voltage. However, this topology requires several isolated dc sources. This drawback not only calls for a complex control system, but also it gives rise to inter module leakage currents in grid-tied PV applications. The inter-module leakage currents result from differential-mode voltage (DMV) and common mode voltage (CMV) variations. In order to tackle the issue, several topologies are suggested in the literature [3,4,5]. One solution is using only one dc-source along with some passive components. Single-source CMIs are categorized into three types. (i) Topologies which use low frequency transformers instead of several isolated dc sources. These topologies are referred to as cascaded transformers multilevel inverters (CTMIs) [6,7,8,9]. (ii) Topologies which provide the isolated dc sources by adopting a high-frequency link and a single dc-source (HFLMI) [10,11]. (iii) A switched-capacitor (SC) based cascaded multilevel inverter (SC-CMI) [12,13]. The main advantage of CTMIs is their ability to provide galvanic isolation between the dc source and the load/grid. This is also the case when applying HFLMIs in PV applications, where the leakage current issue is addressed. On the contrary, CTMIs need several bulky and inefficient transformers. Although the transformer size in HFLMIs is reduced due to the use of a high frequency link, many rectifiers are required to convert the isolated high frequency voltages to the desired dc voltages. Thus, the reliability decreases and the cost increase in this topology. Alternatively, SC-CMIs employ several capacitors instead of the isolated dc sources. Therefore, the SC-CMI topologies have a compact size and lower cost. However, these kinds of multilevel inverters lack galvanic isolation.

Moreover, many attempts have been made to use isolated PV arrays as the isolated dc sources in grid-tied CMIs [14]. However, as illustrated in [15], the main constraint of these configurations is the capacitive leakage currents between the H-bridge (HB) cells and grid. Even using an interfacing transformer cannot address the mentioned problem, because inter-module leakage currents appear and circulate between the cascaded HB cells. In ref. [15], the mentioned problem was addressed by equipping each HB cell with additional ac and dc side filters. Apart from limiting various leakage currents, these filters are deemed to eliminate the EMI; however, equipping each cell with several filters increases the volume and cost of the inverter. In ref. [16], several level-double networks (LDN) are used as the auxiliary blocks to enhance the quality of the output voltage. This topology can also offer a common ground between the PV module and the grid, which results in the elimination of the leakage current. Although the suggested topology can eliminate the leakage current in PV applications, balancing of the capacitor voltage in the auxiliary cell is challenging. In another attempt, a two-stage inverter was suggested in [17], which can be regarded as a combination of the H5 and Highly Efficient and Reliable Inverter Concept (HERIC) topologies. When the output voltage is higher than the grid voltage, the inverter operates in the H5 mode; when the dc link voltage decreases, the inverter is switched to the two-stage HERIC mode. This inverter can properly deal with voltage variation. However, it uses a complicated structure and control approach. Moreover, a charge pump circuit was employed to eliminate the leakage in [18]. The topology is simple and compact, but it imposes a non-continuous current to the input side. Notably, in ref. [19] a comprehensive study was conducted to investigate the state-of-the-art inverters for grid-tied PV applications.

In light of the above, a single-source asymmetric CMI is proposed in this paper, which provides a common ground for ac and dc sides. This topology uses capacitors instead of the isolated dc sources in the HB cells. Each capacitor is independently charged through a charging switch. Since there is a common ground for ac and dc sides, the common mode voltage is zero; hence, this topology can totally eliminate the leakage current in grid-tied PV applications. Another merit of the proposed topology is the capability to boost the input dc voltage; this is also an advantage in many applications such as grid-tied transformerless PV and fuel cell systems. In addition to the mentioned features, the three-phase configuration of the proposed topology draws a continuous input current, which makes it feasible in battery, un-interruptible power supply, and PV applications. The proposed topology can exchange reactive power with the load and the grid as well. Furthermore, it can smoothly charge the capacitors, facilitate the protection, and avoid bulky and expensive transformers in the grid-tied mode. As mentioned, the main issue of the conventional CMI in PV applications is the inter-module leakage currents. However, the proposed topology can address this problem properly and effectively. Compared to the transformer-based single-source multilevel inverters, the proposed topology is smaller in size, lower in cost, and higher in efficiency. Additionally, considering that the SC-based single-source MIs mostly suffer from inrush currents, the proposed topology is, however, an inrush-current free CMI, being a promising converter in many industrial applications.

The rest of the paper is organized as follows: In Section 2, the structure and operation principle of the proposed topology are illustrated. In Section 3, the proposed MI is compared with state-of-the-art MI topology. In Section 4 the performance of the proposed topology in off-grid and grid-tied modes is investigated through simulations. Experimental tests are provided in Section 5, where a fifteen-level 0.55 kVA prototype is adopted to demonstrate the off-grid performance of the proposed topology. Moreover, a seven-level 1.5 kVA prototype is used to extract the grid-tied results. Finally, the overall work is concluded in Section 6.

2. Proposed Topology and Operation Principle

2.1. Conventional CMI in PV Systems

Many solutions are presented in the literature to improve the performance of the CMIs in PV systems. The main problem arises due to the parasitic capacitor in each HB cell that brings inter-module leakage currents [20,21]. These circulating currents cause power loss, EMI, and safety problems [15]. Figure 1a,b shows a grid-tied PV system with a three-cell CMI, and equivalent circuit of the CMV, DMV and leakage currents, respectively.

2.2. General Structure of the Proposed Topology

The proposed topology is synthesized with two parts, namely the main and charging parts. The main part is the conventional asymmetric CMI, in which the isolated dc sources are replaced with capacitors (C₁, C₂, …, C_n). The charging part is composed of a single dc source (e.g., a PV string, fuel-cell, and batteries), a charging inductor, a freewheeling diode and charging switches (S_c1, S_c2, …, S_cn). The general grid-tied configuration of the proposed topology (a configuration with n HB cells) is depicted in Figure 2. Where the main part is colored in black, the charging part is in blue.

As mentioned, the most undesirable phenomenon in an SC-based converter is the inrush currents that emerge in the charging stage of the capacitors. This phenomenon can adversely affect the charging switches and capacitors. In order to limit these currents, a charging inductor (L_ch) is connected in series with the dc source, as shown in Figure 2. This inductor can effectively limit the inrush currents. On the contrary, the mentioned inductor can cause voltage spikes and commutation problems in the charging switches. To avoid this and alleviate the EMI, the size of the charging inductor (L_ch) can be obtained as

$$L_{ch}=\frac{1}{{\left(4\pi f\right)}^2{C}_n}$$

(1)

where f and C_n are the output voltage frequency and equivalent capacitance of the capacitors.

It should be noted that a larger inductor can be used to further reduce the inrush currents. However, this increases the cost and volume of the inverter. A large inductor can also cause overvoltage across the capacitors. To avoid this, as shown in Figure 2, a freewheeling diode (D_f) is connected in parallel with the inductor.

In order to illustrate the operation principle of the proposed topology, a fifteen-level configuration, which is depicted in Figure 3, is exemplified.

Table 1. Operation states of components shown in Figure 3.

Levels	Main Switches	Charging Switches	Capacitors	Vout
	S11, S31, S12S32S13, S33	Sc1, Sc2,Sc2	C1, C2, C3
7	010101	100	C,D,D	7Vdc
6	000101	100	C,D,D	6Vdc
5	100101	010	D,C,D	5Vdc
4	000001	100	C,D,D	4Vdc
3	100001	010	D,C,D	3Vdc
2	001001	100	C,D,D	2Vdc
1	101001	001	D,DC	1Vdc
0	000000	100	C,F,F	0
−1	100000	010	D,C,D	−1Vdc
−2	001000	100	C,D,D	−2Vdc
−3	101000	001	D,D,C	−3Vdc
−4	000010	100	C,F,D	−4Vdc
−5	100010	010	D,C,D	−5Vdc
−6	001010	100	C,D,D	−6Vdc
−7	101010	000	D,D,D	−7Vdc

shows the switching pattern for each level and different states of the capacitors. It should be mentioned that in Table 1, “on” and “off” states of the switches are indicated by “1” and “0”. The capacitors in the proposed topology experience three states namely the charging, discharging, and floating states. In Table 1, “C”, “D”, and “F” denote the charging, discharging, and floating states of the capacitors. In addition, since the upper switches of the main part (S₁₁, S₃₁, S₁₂, S₃₂, S₁₃, and S₃₃) have complementary states with the lower switches (S₂₁, S₄₁, S₂₂, S₄₂, S₂₃, and S₄₃), only the states of the upper switches are indicated in Table 1 for simplicity.

To clarify, the equivalent circuits of the voltage levels are provided. Due to the page limit, only the positive voltage levels are demonstrated in Figure 4. The negative levels can be found by referring to Table 1. In Figure 4, the charging paths, the capacitors under charge and the load current paths are in red, blue, and dark blue, respectively.

2.3. Three-Phase Configuration

Continuity of the input current in many applications is of high importance. A continuous input current can facilitate the maximum power point tracking (MPPT) process in PV applications and prolong battery life span in storage systems. Referring to Table 1, it can be seen that a single-phase configuration of the proposed topology cannot guarantee a continuous input current because there is no possibility to connect the dc source to any of the capacitors when producing the highest negative voltage level (this is the case for a configuration with any number of voltage-levels). Since the input current is only interrupted in the highest negative voltage level, which is a short interval, this problem will not exist in a three-phase configuration. In such a configuration, when the input current is interrupted in one phase, there are always two paths in the other two phases for the current to flow. Figure 5 depicts the general three-phase configuration of the proposed topology. It is worth mentioning that in the three-phase configuration, the CMV is reduced but not totally eliminated. Thus, in a grid-tied PV application with the three-phase configuration, a limited leakage current is achieved. However, the inter-module leakage currents are totally cancelled out in this configuration.

2.4. Component Design

Referring to Figure 4 and Table 1, it is seen that during one cycle, the lower the dc voltage a HB cell contains, the longer time it resides in the charging mode. For example, as shown in Table 1, the first HB cell, which contains 1 pu voltage, resides in the charging mode for eight times. The number of being in the charging mode for the second and third HB cells is four and two, respectively. Thus, in an l-level structure, the number of being in the charging state for the nth HB cell is calculated as

$$Nc{h}_n=2^{\frac{\ln \left(l+1\right)}{ln2}-n}$$

(2)

In respect to this, an HB cell with a higher dc voltage will provides the load current for a longer time than others. Therefore, it experiences the highest voltage ripple. The highest voltage ripple of the nth HB cell ($\Delta v_n)$ is given as

$$\{\begin{array}{c}\Delta v_n=\frac{I_m\Delta t_n}{C_n}\\ \Delta t_n=T\left(l-Nc{h}_n\right)\end{array}$$

(3)

where I_m, T, and C_n are the maximum value of the load current, time duration of a cycle, and capacitance of the nth capacitor, respectively. This equation can be used to select a proper capacitor for the nth HB cell.

Considering Figure 2, the equivalent circuit of the capacitor experiencing the highest voltage ripple (C_n) is shown in Figure 6. Taking the parameters indicated in Figure 6 into account, the instantaneous voltage in the nth capacitor and the voltage of the mentioned capacitor at the end of a half cycle are, respectively, given as

$$v_{c_n}\left(t\right)=(2^{n-1})v_{dc}{}^{\frac{-t}{R{C}_n}}$$

(4)

$$v_{c_n}\left(T_d\right)=(2^{n-1})v_{dc}{}^{\frac{-T_d}{R{C}_n}}$$

(5)

The maximum voltage ripple in the nth capacitor can be given as

$$\Delta v_{c_n}=f{T}_d\left(\left(2^{n-1}\right)v_{dc}-v_{c_n}\left(T_d\right)\right)=f{T}_d\left(2^{n-1}\right)v_{dc}(1-e^{\frac{-T_d}{R{C}_n}})$$

(6)

As it is an asymmetric topology, the HB cells in the proposed topology include different dc voltage values. Considering v_dc as the input voltage, the voltage across the nth cell is given as

$$V_{c_n}=2^{n-1}{v}_{dc}$$

(7)

The voltage stress on the main and charging switches in the nth HB cell is equal to the voltage of capacitor in that HB cell.

The peak output voltage of an n-cell configuration is given as

$$v_m=v_{dc}{{\displaystyle \sum }}_{k=1}^n{2}^{k-1}$$

(8)

The number of switches of an l-level configuration of the proposed and conventional asymmetric CMI topologies is, respectively, indicated as

$$N_{sw}^P\frac{5\ln \left(\frac{l+1}{2}\right)}{ln2}$$

(9)

$$N_{sw}^C\frac{4\ln \left(\frac{l+1}{2}\right)}{ln2}$$

(10)

This implies that the proposed topology requires one extra switch in each cell (one charging switch for each cell).

The total voltage stresses of the switches in the proposed and the conventional asymmetric CMI topologies are, respectively, indicated as

$$TV{S}_p=\frac{5v_{dc}}{N_{sw}^P}{{\displaystyle \sum }}_{k=1}^{N_{sw}^p/5}{2}^{k-1}$$

(11)

$$TV{S}_c=\frac{4v_{dc}}{N_{sw}^c}{{\displaystyle \sum }}_{k=1}^{N_{sw}^c/4}{2}^{k-1}$$

(12)

Implying that the voltage stresses of the switches in both topologies are the same.

3. Benchmarking with Prior-Art Inverters

Several efforts have been done to make the CMI compatible with grid-tied PV applications [22,23,24,25,26,27,28,29]. The main difficulties with the CMI in PV applications are the leakage current and complicated MPPT [14]. Single-source CMIs facilitate the MPPT, but the leakage current problem remains. A transformer can solve the problem, however, transformers are not recommended in grid-tied PV applications due to extra power losses and additional costs. Therefore, as stated previously, the SC-based CMI can fulfill many requirements. The state-of-the-art PV MI topologies are compared with the proposed MI topology in this section to assess its pros and cons.

Table 2. Comparison.

Topology	Nsw	Nd	Nc	G	TSV	Coupled Inductor	Leakage Current Limiting
[22]	14	0	2	3	4.67	no	no
[23]	12	-	2	2	5.5	no	no
[24]	10	-	2	0.5	8	yes	yes
[25]	8	3	3	4	5.75	no	no
[26]	12	-	3	4	5.25	no	no
[27]	9	-	2	2	5.5	no	no
[28]	11	-	3	2	5	no	no
[29]	8	4	4	2	6	no	no
[Proposed]	10	0	2	3	5	no	yes

lists the main features of the considered MI topologies.

In table, N_sw, N_d, N_c, G, and TSV are the number of switches, diodes, capacitors, voltage gain, and the total standing voltage of the switches. The TSV is calculated as

$$TSV=\frac{{\sum }_{n=0}^{n=k}{V}_{s{w}_n}+{\sum }_{n=0}^{n=k}{V}_{s{d}_n}}{V_{out}}$$

(13)

The proposed topology and the topology in [29] can be scaled up to obtain higher voltage gains and levels. However, this is not the case for the other topologies. Since the proposed MI topology is a common-ground-type inverter and the topology in [24] is a mid-point-grounded topology, these two topologies can limit the leakage current in grid-tied PV applications. In this regard, the other topologies listed in Table 2 encounter serious problems. The main disadvantage of the MI topologies in [24] and [25] is that they require a complicated control approach to balance the voltages across the capacitors. The voltage balancing system of these topologies should sense the direction of the ac current and the capacitor voltage magnitude, and then the sensed values are processed though the processor to execute the right switching pattern to balance the voltage of the capacitors. However, this does not happen in the other topologies and the proposed one. Notably, the topologies in [23,25,27,28] suffer from high inrush currents in the charging stage of the capacitor. Owing to the controlled voltage balancing of the capacitors, the inrush current does not appear in the topologies in [24,25]. In the proposed topology and the topology in [29], the inrush current is limited through the charging inductor. As it is seen in Table 2, the proposed inverter has a fairly low TSV, high voltage gain and fewer components.

4. Simulation Results

In order to verify the performance of the proposed topology, both the single-phase and three-phase configurations are simulated under MATLAB/Simulink. The main parts in the considered configurations are assumed to be a fifteen-level CMI. The simulated models are tested under off-grid and grid-tied modes. In the off-grid mode, a general dc source supplies the load through the proposed topology.

4.1. Off-Grid Mode

As illustrated earlier, the three-phase and single-phase configurations only differ in the input current shapes. For this reason, mostly the single-phase configuration is investigated.

Table 3. Components of the off-grid model.

Component	Value	Component	Value
Vdc	46 V	Lch (3ϕ)	0.5 mH
Power rating	550 W	C1, C2, C3	3300 µF
Lch (ϕ)	1.8 mH	fsw	5 kHz
Reference voltage		311 V (peak), 50 Hz

shows the characteristics of the utilized components in the off-grid mode. Figure 7a shows the output and capacitor voltages under no-load condition. A fast Fourier transform (FFT) analysis of the output voltage is depicted in Figure 7b.

Furthermore, the output voltage, load current, and capacitor voltages, when supplying a purely resistive load of 0.55 kW, are shown in Figure 8a. As seen in Figure 8a, under this condition, the voltage across the capacitors is properly balanced through the charging circuit. Additionally, the capacitor currents along with the input current under the studied loading condition are shown in Figure 8b. It can be seen that the charging unit can properly limit the inrush current of the capacitors. However, the main demerit of the charging process is the discontinuity of the input current due to the absence of a path for the input current when developing the highest negative voltage level.

In order to demonstrate the ability of the proposed topology to provide reactive power, a resistive-inductive load of 0.5 kW + 0.35 kVar is connected. Figure 9a shows the output voltage and load current under the mentioned condition. As shown in Figure 9a, the proposed topology can satisfactorily supply the reactive power. Additionally, the voltage stress and current of the charging switches are shown in Figure 9b. According to Figure 9b, it is known that the charging switch in the last cells can tolerate the highest voltage stress.

As mentioned previously, a three-phase configuration of the proposed topology draws a continuous current from the input side. This is proven by considering a three-phase fifteen-level configuration, which supplies a balanced three-phase load under three loading cases (3.8 kW, 4.8 kW + 1.2 kVar, 3 kW + 1.2 kVar). The input current of the phases and the total input current under the mentioned loading condition are shown in Figure 10a. As it is seen in Figure 10a, the input current is a continuous current. Moreover, the output voltages together with the load current under the mentioned condition are shown in Figure 10b,c, respectively. When the freewheeling diode is removed, the capacitors are exposed to overvoltage at the initial instance. Soft starting strategies can be employed to avoid the overvoltage of the capacitors.

4.2. Grid-Tied Mode

Similar to the off-grid mode, a fifteen-level configuration of the proposed topology is used to deliver the desired powers to the grid. To this end, the ac components are transferred to the dq0 frame and two proportional-integral (PI) controllers are employed to control the active and reactive powers.

Table 4. Component of the grid-connected model.

Ki	42.3	Grid-side filter	2.8 mH + 30 mΩ
Kp	700	fsw	5 kHz
$V_{g_{\max }}$	320 V	Lch	1.8 mH
f	50 Hz	C1, C2, C3	3300 µF

shows the characteristics of the considered system.

The simulation results of the single-phase grid-connected model are shown in Figure 11. The desired (reference) and delivered active power to the grid is shown in Figure 11a. The reference of the active power can be obtained by the MPPT system in PV applications. The reference and developed reactive powers are exhibited in Figure 11b. As shown in Figure 11b, the proposed topology has succeeded to provide a bidirectional reactive power flow. The input current is depicted in Figure 11c. The output voltage of the inverter along with the injected current is exhibited in Figure 11d.

It should be pointed out that one of the significant features of the proposed MI topology is its ability to eliminate the leakage current in grid-tied PV systems without using any additional components.

Furthermore, the simulation results of a grid-connected three-phase model are demonstrated in Figure 12. The injected active and reactive powers to the grid are depicted in Figure 12a,b. As seen in Figure 12, the proposed MI has deservedly developed the desired powers.

As discussed previously, the three-phase configuration of the proposed topology draws a continuous current from the dc-link. Figure 13a shows the input current and proves this. In order to investigate the leakage current, a parasitic capacitor of 200 nF is considered between the negative pole of the dc-side and ac-ground, Figure 13b shows the leakage current. As shown in Figure 13b, the root mean square (RMS) value of the leakage current is in the acceptable range. However, it is possible to reduce this through the proper control and/or switching approaches. It is worth mentioning that since the proposed topology does not use PV modules inside the H-bridge cells, there are no inter-module leakage currents.

Furthermore the output voltage and the injected current are shown in Figure 14. It is to be noted that this paper is not aimed at designing a proper control system. It is possible to obtain a more accurate result through a precise control approach.

5. Experimental Results

5.1. Off-Gird Results

In order to validate the feasibility of the proposed topology, a laboratory-scale prototype is tested. Figure 15 depicts the employed prototype and

Table 5. Electrical parameters and component specifications.

Component	Specification	Electrical Parameter	Value
Main Switches	IRFP350	Resistive load	550 W
Charging switches	IRFP460	RL load	650 VA
Opto-coupler	TLP250	Vout(RMS)	220 v, 50 Hz
Capacitors	3300 µF	Vdc	47 V
Lch	2.8 mH	fsw	5 kHz
Diodes	FFPF20UP40S	# of HB cells	3 (15-level)

lists the utilized components. It should be noted that the level-shifted SPWM strategy is adopted to compute the switching signals.

Figure 16 exhibits the output voltage under the no-load condition and the FFT analysis of the voltage. As can be seen, the harmonics around the fundamental frequency have negligible magnitude, while the harmonics around the multiples of the switching frequency are of high amplitude. Since these harmonics are far away from the fundamental frequency, they can easily be eliminated using small filters.

The output voltage along with the load current, when the prototype supplies a purely resistive load of 550 W is shown in Figure 17a. In order to assess the voltage ripple of the capacitors, the ac components of the capacitor voltages are shown in Figure 17b–d. Additionally, the charging current of the capacitor under 550 W load is shown in Figure 17e. As it is seen, there is no sharp spike on the charging current of the capacitors, which implies that the charging inductor smoothen the charging currents.

In order to prove the capability of the proposed topology to provide reactive power, a resistive-inductive load of 500 W + 350 Var is then considered. Figure 18 exhibits the output voltage and load current under this condition. As can be seen, the proposed topology can supply the reactive power without any constraints.

5.2. Grid-Tied Results

In order to extract the grid-tied results a seven-level prototype with two cells is employed. The characteristic of the prototype and grid is listed in

Table 6. Component of the grid-connected model.

Main Switches	FQA14N30	Grid-side filter	1.73 mH
Charging switches	STP30NM30N	Switching frequency (fsw)	22 kHz
RMS grid voltage	220 V	Lch	1.6 mH
Grid frequency (f)	50 Hz	C1, C2	3300 µF

. In this test the sample based current control is used to inject the desired active and reactive powers to the grid.

Three scenarios are considered in grid-tied test. In the first scenario a pure active power of 1.5 kW is injected to the grid. The injected current and grid voltage under this condition are shown in Figure 19a. The FFT analysis of the injected current under the mentioned condition is shown in Figure 19b. Furthermore, the output voltage of the inverter along with the provided current is shown in Figure 19c.

In the second scenario the active power of 1.2 kW and reactive power of 0.9 kVar is injected to the grid and in the third scenario the active power of 1.2 kW is injected to the grid and reactive power of 0.9 kVar absorbed from the grid. The grid voltage together with the injected current to the grid is shown in Figure 20a,b.

The seven-level prototype for grid-tied application is exhibited in Figure 21.

6. Conclusions

In this paper, a single-source high step-up asymmetric power converter topology is proposed. The proposed topology offers several advantages in many industrial applications such as PV, fuel cell, etc. It is synthesized with two parts, namely, the main and charging parts. The main part is the same as the conventional asymmetric CMI with certain capacitors instead of the isolated dc sources. The charging part, however, consists of charging switches, a charging inductor, a freewheeling diode, and one dc source. The main feature of the proposed topology is to provide a common-ground for ac and dc sides, which eliminates the leakage current in grid-tied PV applications. It also has the ability to boost the input voltage. Thus, in the grid-tied PV applications, bulky and expensive transformers can be avoided. Moreover, it uses only one dc source, at the expense of using many switches, employing many switches can be considered as the main drawback of the proposed inverter. Simulations and experiments were performed to verify the effectiveness of the proposed topology. Through simulations, the performances of the suggested topology with single- and three-phase configuration, in both off-grid and grid-tied conditions, were assessed. In the experimental tests, the performance of the proposed topology was studied in the presence of a 550-VA load. Moreover, using a 1.5 kVA seven-level prototype the grid-tied results were provided. Both results have demonstrated the feasibility of the proposed multilevel inverter in terms of the ability to develop a boosted voltage of high quality using only one dc source.