Some Structures of Parallel VLSI-Oriented Processing Units for Implementation of Small Size Discrete Fractional Fourier Transforms
Abstract
1. Introduction
2. Preliminary Remarks
3. Algorithm and Processing Unit Structure for Small Size DFrFTs
3.1. Computing the Two-Point DFrFT
3.2. Computing the Three-Point DFrFT
3.3. Computing the Four-Point DFrFT
3.4. Computing the Five-Point DFrFT
3.5. Computing the 6-Point DFrFT
3.6. Computing th eSeven-Point DFrFT
4. Implementation Complexity
5. Discussion
Author Contributions
Funding
Conflicts of Interest
References
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Size N | Numbers of Arithmetic Blocks | |||||
---|---|---|---|---|---|---|
Naive Method | Proposed Algorithm | |||||
Multipliers | N-Input Adders | Multipliers | 2-Input Adders | 3-Input Adders | 4-Input Adders | |
2 | 4 | 2 | 3 | 3 | - | - |
3 | 9 | 3 | 5 | 7 | - | - |
4 | 16 | 4 | 10 | 7 | 2 | - |
5 | 25 | 5 | 11 | 18 | 1 | - |
6 | 36 | 6 | 18 | 20 | - | 2 |
7 | 49 | 7 | 19 | 24 | 6 | 1 |
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Cariow, A.; Papliński, J.; Majorkowska-Mech, D. Some Structures of Parallel VLSI-Oriented Processing Units for Implementation of Small Size Discrete Fractional Fourier Transforms. Electronics 2019, 8, 509. https://doi.org/10.3390/electronics8050509
Cariow A, Papliński J, Majorkowska-Mech D. Some Structures of Parallel VLSI-Oriented Processing Units for Implementation of Small Size Discrete Fractional Fourier Transforms. Electronics. 2019; 8(5):509. https://doi.org/10.3390/electronics8050509
Chicago/Turabian StyleCariow, Aleksandr, Janusz Papliński, and Dorota Majorkowska-Mech. 2019. "Some Structures of Parallel VLSI-Oriented Processing Units for Implementation of Small Size Discrete Fractional Fourier Transforms" Electronics 8, no. 5: 509. https://doi.org/10.3390/electronics8050509
APA StyleCariow, A., Papliński, J., & Majorkowska-Mech, D. (2019). Some Structures of Parallel VLSI-Oriented Processing Units for Implementation of Small Size Discrete Fractional Fourier Transforms. Electronics, 8(5), 509. https://doi.org/10.3390/electronics8050509