Next Article in Journal / Special Issue
An Efficient Hardware Accelerator for the MUSIC Algorithm
Previous Article in Journal
Shaping SiC MOSFET Voltage and Current Transitions by Intelligent Control for Reduced EMI Generation
Previous Article in Special Issue
Efficient-Scheduling Parallel Multiplier-Based Ring-LWE Cryptoprocessors
Article Menu

Export Article

Open AccessArticle

Some Structures of Parallel VLSI-Oriented Processing Units for Implementation of Small Size Discrete Fractional Fourier Transforms

West Pomeranian University of Technology Szczecin, Faculty of Computer Science and Information Technology, Zolnierska 49, 71-210 Szczecin, Poland
*
Authors to whom correspondence should be addressed.
Electronics 2019, 8(5), 509; https://doi.org/10.3390/electronics8050509
Received: 5 April 2019 / Revised: 19 April 2019 / Accepted: 2 May 2019 / Published: 8 May 2019
(This article belongs to the Special Issue VLSI Architecture Design for Digital Signal Processing)
  |  
PDF [1241 KB, uploaded 8 May 2019]
  |  

Abstract

Discrete orthogonal transforms such as the discrete Fourier transform, discrete cosine transform, discrete Hartley transform, etc., are important tools in numerical analysis, signal processing, and statistical methods. The successful application of transform techniques relies on the existence of efficient fast algorithms for their implementation. A special place in the list of transformations is occupied by the discrete fractional Fourier transform (DFrFT). In this paper, some parallel algorithms and processing unit structures for fast DFrFT implementation are proposed. The approach is based on the resourceful factorization of DFrFT matrices. Some parallel algorithms and processing unit structures for small size DFrFTs such as N = 2, 3, 4, 5, 6, and 7 are presented. In each case, we describe only the most important part of the structures of the processing units, neglecting the description of the auxiliary units and the control circuits. View Full-Text
Keywords: discrete fractional Fourier transform; VLSI-oriented algorithms; processing unit structure discrete fractional Fourier transform; VLSI-oriented algorithms; processing unit structure
Figures

Figure 1

This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
SciFeed

Share & Cite This Article

MDPI and ACS Style

Cariow, A.; Papliński, J.; Majorkowska-Mech, D. Some Structures of Parallel VLSI-Oriented Processing Units for Implementation of Small Size Discrete Fractional Fourier Transforms. Electronics 2019, 8, 509.

Show more citation formats Show less citations formats

Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Related Articles

Article Metrics

Article Access Statistics

1

Comments

[Return to top]
Electronics EISSN 2079-9292 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
Back to Top