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Electronics 2019, 8(1), 69; https://doi.org/10.3390/electronics8010069

A 2.5-GHz 1-V High Efficiency CMOS Power Amplifier IC with a Dual-Switching Transistor and Third Harmonic Tuning Technique

1
Department of Electrical Engineering, Universitas Indonesia, Depok 16424, Indonesia
2
Graduate School of Information, Production and Systems, Waseda University, Kitakyushu-shi 808-0135, Japan
*
Author to whom correspondence should be addressed.
Received: 29 October 2018 / Revised: 2 January 2019 / Accepted: 2 January 2019 / Published: 8 January 2019
(This article belongs to the Special Issue Nanoelectronic Materials, Devices and Modeling)
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Abstract

This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm. View Full-Text
Keywords: dual-switching transistor; third harmonic tuning; low voltage; high efficiency; CMOS power amplifier IC dual-switching transistor; third harmonic tuning; low voltage; high efficiency; CMOS power amplifier IC
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Kurniawan, T.A.; Yoshimasu, T. A 2.5-GHz 1-V High Efficiency CMOS Power Amplifier IC with a Dual-Switching Transistor and Third Harmonic Tuning Technique. Electronics 2019, 8, 69.

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