Kim, Y.K.; Lee, J.S.; Kim, G.; Park, T.; Kim, H.; Cho, Y.P.; Park, Y.J.; Lee, M.J.
Simulation Analysis in Sub-0.1 μm for Partial Isolation Field-Effect Transistors. Electronics 2018, 7, 227.
https://doi.org/10.3390/electronics7100227
AMA Style
Kim YK, Lee JS, Kim G, Park T, Kim H, Cho YP, Park YJ, Lee MJ.
Simulation Analysis in Sub-0.1 μm for Partial Isolation Field-Effect Transistors. Electronics. 2018; 7(10):227.
https://doi.org/10.3390/electronics7100227
Chicago/Turabian Style
Kim, Young Kwon, Jin Sung Lee, Geon Kim, Taesik Park, HuiJung Kim, Young Pyo Cho, Young June Park, and Myoung Jin Lee.
2018. "Simulation Analysis in Sub-0.1 μm for Partial Isolation Field-Effect Transistors" Electronics 7, no. 10: 227.
https://doi.org/10.3390/electronics7100227
APA Style
Kim, Y. K., Lee, J. S., Kim, G., Park, T., Kim, H., Cho, Y. P., Park, Y. J., & Lee, M. J.
(2018). Simulation Analysis in Sub-0.1 μm for Partial Isolation Field-Effect Transistors. Electronics, 7(10), 227.
https://doi.org/10.3390/electronics7100227