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Open AccessArticle

Simulation Analysis in Sub-0.1 μm for Partial Isolation Field-Effect Transistors

1
School of Electronics and Computer Engineering, Chonnam National University, Gwangju 500-757, Korea
2
Department of Electrical and Control Engineering, Mokpo National University, Jeollanam-do 534-729, Korea
3
School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea
4
The KEPCO Research Institute, Daejeon 305-760, Korea
*
Authors to whom correspondence should be addressed.
Electronics 2018, 7(10), 227; https://doi.org/10.3390/electronics7100227
Received: 20 September 2018 / Revised: 28 September 2018 / Accepted: 28 September 2018 / Published: 2 October 2018
(This article belongs to the Special Issue Nanoelectronic Materials, Devices and Modeling)
In this paper, we extensively analyzed the drain-induced barrier lowering (DIBL) and leakage current characteristics of the proposed partial isolation field-effect transistor (PiFET) structure. We then compared the PiFET with the conventional planar metal-oxide semiconductor field-effect transistor (MOSFET) and silicon on insulator (SOI) structures, even though they have the same doping profile. Two major features of the PiFET are potential condensation and potential modulation by a buried insulator. The potential modulation near the drain region can control the electric field in the overlapped region of the drain and gate, because it causes a high gate-fringing field. Therefore, we suggest guidelines with respect to the optimal PiFET structure. View Full-Text
Keywords: drain-induced barrier lowering (DIBL); gate-induced drain leakage (GIDL); silicon on insulator (SOI) drain-induced barrier lowering (DIBL); gate-induced drain leakage (GIDL); silicon on insulator (SOI)
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MDPI and ACS Style

Kim, Y.K.; Lee, J.S.; Kim, G.; Park, T.; Kim, H.; Cho, Y.P.; Park, Y.J.; Lee, M.J. Simulation Analysis in Sub-0.1 μm for Partial Isolation Field-Effect Transistors. Electronics 2018, 7, 227. https://doi.org/10.3390/electronics7100227

AMA Style

Kim YK, Lee JS, Kim G, Park T, Kim H, Cho YP, Park YJ, Lee MJ. Simulation Analysis in Sub-0.1 μm for Partial Isolation Field-Effect Transistors. Electronics. 2018; 7(10):227. https://doi.org/10.3390/electronics7100227

Chicago/Turabian Style

Kim, Young K.; Lee, Jin S.; Kim, Geon; Park, Taesik; Kim, HuiJung; Cho, Young P.; Park, Young J.; Lee, Myoung J. 2018. "Simulation Analysis in Sub-0.1 μm for Partial Isolation Field-Effect Transistors" Electronics 7, no. 10: 227. https://doi.org/10.3390/electronics7100227

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