Review Reports

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

Comments and Suggestions for Authors

A zero-voltage-switching (ZVS) synchronous buck converter employing digital hybrid control with variable slope compensation proposed by the author. However, there are still some issues that need to be explained in detail.

1. Figure 23. shows the efficiencies of the converter with and without the coupled inductor. However, the proposed was not compared to other control.  Need to be clarified in comparison table. 
2. The steady state performance need to be clarified in experimental results, due to the sharing of the digital hybrid control, what is the limitation in the inductor current or output current and voltage, better to show these waveforms.
3. Beside the steady-state performance is not presented, also the manuscript provides limited insight into the system’s dynamic and transient response, including load or input voltage changes. Incorporating a short analysis or simulation of these aspects would strengthen the control-related discussion.
4. The experimental section conducted tests under different operating conditions to verify the controller, there was limited discussion on the test. It is better to divide into subsection

 

Comments for author File: Comments.pdf

Author Response

Comment 1:

Figure 23 shows the efficiencies of the converter with and without the coupled inductor. However, the proposed method was not compared with other control techniques. This needs to be clarified in a comparison table.

Response:

Thank you for pointing this out. We agree with this comment. Therefore, we have added a new comparison table (Table 5) in the revised manuscript to clarify the positioning of the proposed method with respect to other representative buck converter control techniques reported in the literature. The comparison includes control strategy, soft-switching mechanism, reverse-recovery suppression capability, slope-compensation method, digital adaptivity, auxiliary circuit requirement, and reported efficiency.

In addition, the discussion associated with Figure 23 has been revised to clarify that the efficiency curves compare converters with and without the coupled inductor under identical circuit conditions, while the newly added Table 5 provides a broader comparison with existing control approaches. These revisions help to better highlight the advantages and contributions of the proposed method.

Revisions:

• Added Table 5 (Comparison with representative buck converter control techniques).
• Revised the discussion related to Figure 23 in Section 6.

(Page 26, Section 6, Table 5).

 

Comment 2:

The steady-state performance needs to be clarified in the experimental results. Due to the sharing of the digital hybrid control, what are the limitations in the inductor current or output current and voltage? It would be better to show these waveforms.

Response:

Thank you for this insightful comment. We agree that clarifying the steady-state performance and the limitations associated with the shared digital hybrid control is important.

In response, we have revised the experimental results section to more clearly emphasize the steady-state operating conditions of the proposed converter. Specifically, the steady-state inductor current and output current waveforms are already presented in Figures 12–15 (for the non-coupled inductor case) and Figures 15–22 (for the coupled-inductor case), where all operating points satisfy  and , confirming stable continuous conduction mode (CCM) operation under steady-state conditions.

In addition, the discussions associated with these figures have been expanded to explicitly clarify the current and voltage limitations imposed by the digital hybrid control. The maximum inductor current and output current are constrained by the peak current–mode control loop and the rated current of the power stage (5 A), while the output voltage regulation is maintained by the outer voltage loop. These limitations are inherently reflected in the steady-state waveforms shown in the experimental results.

Furthermore, the text has been revised to clarify that the proposed digital hybrid controller shares the same control architecture across different operating conditions, and stable steady-state performance is maintained by adaptive slope compensation and logic-based mode detection, without introducing additional current or voltage stress.

Revisions:

• Revised the discussion of experimental steady-state waveforms in Section 6.
• Clarified the steady-state current and voltage limitations imposed by the digital hybrid control.

(Please see Pages 16–17 for the text in Section 6.1 and Pages 17–23 for Figures 12–22).

 

Comment 3:

Besides the steady-state performance, the manuscript provides limited insight into the system’s dynamic and transient response, including load or input voltage changes. Incorporating a short analysis or simulation of these aspects would strengthen the control-related discussion.

Response:

We thank the reviewer for this important suggestion. We agree that, for a control architecture, the analysis of dynamic and transient responses is essential for a more comprehensive evaluation of system stability and control performance under load variations and input-voltage disturbances.

In this study, the dynamic characteristics of the proposed control strategy are partially reflected in the small-signal model and frequency-domain analysis presented in Section 5 (Slope Compensation). Through the small-signal inner-loop model of peak current–mode control (PCMC) (Figure 7) and the measured open-loop control-to-output Bode plots under different output voltages and input conditions (Figures 9–11), it can be observed that sufficient gain margin and phase margin are maintained over a wide operating range, thereby verifying the dynamic stability of the proposed control scheme from a control-theoretic perspective.

In addition, the measured inductor current, current-feedback signal, and slope-compensation signal presented in the experimental section (Figures 12–22(d)) show that the current inner loop converges rapidly under different input-voltage and load conditions, without exhibiting subharmonic oscillation or noticeable instability. These time-domain waveforms also indirectly demonstrate that the proposed variable slope-compensation mechanism can effectively suppress the growth of current perturbations and enhance transient stability compared with a fixed-slope design.

To address the reviewer’s comment, a supplementary discussion entitled “Dynamic and Transient Response Considerations” has been added to Section 6 of the revised manuscript. This discussion integrates the small-signal analysis and experimental observations to further clarify the dynamic behavior of the proposed control architecture under load and input-voltage variations. Considering that the main focus of this paper is on the auxiliary-branch ZVS mechanism and digital variable slope compensation for improving stability and efficiency, a detailed large-signal transient simulation and measurement study is left for future work.

Revisions:

The above supplementary discussion has been added to the revised manuscript in Section 6 (between Section 6.2 and Section 6.3).

(Please see Page 24, Section 6.2).

 

 

Comment 4:

The experimental section conducted tests under different operating conditions to verify the controller; however, there is limited discussion of these tests. It would be better to divide the section into subsections.

Response:

We thank the reviewer for this valuable suggestion. We agree that, although the original experimental section covered multiple operating conditions (different input voltages, output voltages, and load levels), the overall discussion structure could be further strengthened to improve technical clarity and readability.

Following the reviewer’s recommendation, the experimental section (Section 6) has been reorganized and subdivided into multiple subsections, in which different test objectives and operating conditions are clearly distinguished. Corresponding experimental observations and discussions have been added to each subsection. The revised structure is summarized as follows:

  ection 6.1: Steady-State and ZVS Verification without Coupled Inductor
This subsection focuses on the configuration without the coupled inductor and systematically investigates the effects of the auxiliary branch on suppressing the reverse-recovery current of the synchronous rectifier and achieving zero-voltage switching (ZVS) of the main switch under different input-voltage conditions. Detailed waveform analyses are provided based on Figures 12–14.

  Section 6.2: Steady-State and ZVS Verification with Coupled Inductor
This subsection presents experimental verification of the proposed converter with the coupled inductor under different output voltages (24 V, 48 V, and 96 V) and a wide input-voltage range. The influence of the coupled inductor on current continuity, ZVS operating conditions, and smoothing of the synchronous rectifier current is discussed with reference to Figures 15–22.

  Section 6.3: Efficiency Performance under Different Load Conditions
An additional subsection has been included to present and discuss efficiency comparisons under different load and input-voltage conditions. The efficiency differences between the configurations with and without the coupled inductor are highlighted based on Figures 23–25, demonstrating the performance advantages of the proposed approach in practical operating scenarios.

Revisions:

Through the above reorganization of the experimental section and the added supplementary discussions, the correspondence between the experimental results and the respective design objectives has been clarified. This improved structure helps readers better understand the specific aspects validated by each experiment under different operating conditions. The related revisions have been incorporated into Section 6 (Sections 6.1–6.3) of the revised manuscript..

(Page 15-25, Section 6)

(Please see Page 16, Section 6.1; Page 19, Section 6.2; and Page 24, Section 6.3).

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

This paper presents a well-structured and technical investigation into improving the performance of a synchronous buck converter. The integration of a ZVS auxiliary network, a coupled inductor for current shaping, and a digitally controlled variable slope compensation scheme addresses relevant issues of efficiency, reverse recovery, and stability. The experimental verification across a wide input range and multiple output levels is comprehensive and lends strong support to the claims. The manuscript is generally clear, though some sections could benefit from improved clarity and connective explanation. The work appears novel in its specific combination of techniques and its practical implementation.

Following are my comments:

• The introduction clearly outlines the problem of body diode reverse recovery in CCM. However, could the authors quantify the typical efficiency penalty or loss breakdown caused by this spike in a standard synchronous buck at their power/voltage levels? This would better justify the added circuit complexity.
• The manuscript mentions 13 operating modes within one switching period. While listing all may be cumbersome, could the authors briefly describe the key modes that are most critical to achieving ZVS and mitigating the diode current, referencing Figure 2? This would greatly aid reader understanding.
• The logic based on is explained, but what is the practical implementation and tuning of the 90% input voltage threshold? Is this ratio fixed in the digital controller, and how does it ensure robustness against noise?
• The digital hybrid control chip (PIC16F1769) handles voltage sensing and dynamic slope compensation. What is the specific control law or algorithm used to adjust m_s based on  V_in and V_o?
• Figure 8 shows a step-wise relationship; how are these intervals chosen? this ratio fixed in the digital controller, and how does it ensure robustness against noise?
• In the small-signal model : Figure 7and Eq. 15 to 21 , the analysis seems based on a conventional buck. To what extent does the presence of the active auxiliary branch and the coupled inductor modify this model? The authors state the coupled inductor is replaced by an equivalent single inductor for simplicity, is this a valid assumption for the stability analysis?
• Table 4 lists parasitic capacitances. Are these measured values or extracted from datasheets? Parasitics are crucial for the ZVS resonance; a note on how they were determined would be useful.
• The dead times and  are mentioned in Eq. (1). How are these dead times determined and implemented in the drive circuitry? Are they fixed, or adaptively controlled?
• The efficiency graphs show data points at specific loads such as 24W, 72W, 120W for 24V output. What about the efficiency at very light loads. Does the control scheme or auxiliary branch operation become less effective, impacting light-load efficiency?

 

Author Response

Dear Reviewer,

As the responses are relatively extensive, we have compiled our detailed replies in a separate Word document entitled “electronics-4104270-response2.docx”, which is attached to this submission. We kindly invite you to download the attached file for a complete review of our responses. Thank you very much for your time and valuable

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

The paper presents an approach for achieving ZVS operation of sync. Buck converter using an auxiliary circuit and control with slope compensation, My comments and questions are as follows:

1- The description of the operation modes, shown in Fig. 2, and key waveforms, Fig.3, are missing from the paper. A clear analysis must be included to explain the operation principles.

2- In the experimental results section, the comparisons are conducted between the proposed circuit and the circuit presented in Fig.1a. However, Does the proposed solution attains improved efficiency compared to the conventional sync. Buck ? Given that the WBG devices have a minimized recovery losses it is questionable that the proposed solution can attain improved efficiency.

3- The introduction and references need to be updated with more recent studies as most of the references are +30 years old which prevent from showcasing the novelty and motivations for the proposed circuit compared to the current state of the art.

4- A loss breakdown for the proposed circuit and conventional sync. Buck is recommended.

5- There are many typos like the duplicated text at the end of the Intro., the missing spaces after the symbols. The paper should be carefully revised to eliminate these typos.  

Author Response

Dear Reviewer,

As the responses are relatively extensive, we have compiled our detailed replies in a separate Word document entitled “electronics-4104270-response3.docx”, which is attached to this submission. We kindly invite you to download the attached file for a complete review of our responses. Thank you very much for your time and valuable

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

The revised paper is now satisfactory for publication. 

Reviewer 2 Report

Comments and Suggestions for Authors

The authors have addressed all my comments. I have no further comments.

 

Reviewer 3 Report

Comments and Suggestions for Authors

The revised version has addressed my comments and I have no further questions, Thank you.