Zero-Voltage-Switching Buck Converter Using Digital Hybrid Control with Variable Slope Compensation

Abstract

This paper proposes a zero-voltage-switching (ZVS) synchronous buck converter employing a digital hybrid control scheme with variable slope compensation. By using an auxiliary-switch network and a digital controller to sense voltage and current, the system can automatically adjust the slope-compensation parameters according to the input and output conditions, thereby enhancing stability over a wide operating range. The proposed method effectively suppresses the reverse-recovery current spike of the synchronous rectifier during continuous conduction mode (CCM) operation and enables the main switch to achieve ZVS, reducing switching loss and improving efficiency. A laboratory prototype with an input voltage range of 30–160 V and output voltage levels of 24 V, 48 V, and 96 V at 5 A is developed to verify the feasibility of the proposed architecture.

1. Introduction

Buck converters, known for their high efficiency and simple structure, are widely used in renewable energy systems, distributed power supplies, and electric vehicles. In conventional buck converters, a diode is used as the freewheeling device, which results in considerable conduction loss [1]. To improve efficiency, synchronous rectification techniques have been widely adopted in the literature [2,3,4]. However, synchronous-rectified buck converters operating in continuous conduction mode (CCM) still suffer from significant switching losses and current spikes caused by the reverse-recovery behavior of the body diode.

During CCM operation, the inductor current initially flows through the body diode of the synchronous switch. When the main switch is turned on, the body diode undergoes reverse recovery, generating a reverse-recovery current spike. This phenomenon not only increases the reverse-recovery loss of the body diode but also aggravates the switching loss of the main switch, thereby reducing the overall conversion efficiency and increasing electromagnetic interference (EMI), especially under high input-voltage conditions [5].

To mitigate switching losses and suppress diode reverse-recovery current, various soft-switching techniques have been proposed. Quasi-resonant converter topologies have been introduced to achieve soft switching; however, since the resonant components are placed in the main power path, the power switches are subjected to increased voltage and current stresses [6,7,8]. To overcome this limitation, zero-voltage-transition (ZVT) and zero-current-transition (ZCT) techniques have been proposed, in which the resonant loop is relocated to an auxiliary branch through an auxiliary switch network [9,10,11]. By employing auxiliary circuits, the main switch can operate under zero-voltage or zero-current switching conditions, effectively reducing the current fall rate of the diode, suppressing reverse-recovery spikes, and lowering device stress.

In recent years, various ZVS synchronous buck converters employing auxiliary branches and coupled inductors have been reported to further reduce switching loss while maintaining low voltage and current stress on the power devices [12,13,14]. These approaches demonstrate that auxiliary-assisted ZVS techniques are effective for improving the efficiency of high-voltage buck converters operating in CCM.

In addition to topology design, control strategies play a crucial role in determining the performance of DC–DC converters. Control methods can generally be categorized into voltage-mode control and current-mode control. Current-mode control offers advantages such as simple compensation design, inherent over-current protection, and effective current-sharing capability. Among various current-mode control schemes, peak current-mode control (PCMC) is particularly attractive because it provides cycle-by-cycle current limiting and fast transient response, making it advantageous over voltage-mode control [15]. However, it has been well documented that when PCMC operates in CCM with duty cycles exceeding 50%, subharmonic oscillations may occur, which can lead to instability and increased EMI [15,16,17,18,19,20,21,22,23]. To address this issue, slope-compensation techniques have been proposed and extensively studied. Recent studies have further investigated adaptive and automatic slope-compensation methods suitable for digital and hybrid current-mode controllers, enabling stable operation over wide operating ranges [2].

Building upon the ZVT synchronous buck topology reported in [10], this work addresses the auxiliary-branch resonance and current discontinuity issues observed at high switching frequencies. By introducing a coupled inductor to replace the auxiliary inductor, the stored energy in the diode can be released more rapidly, thereby improving the current continuity of the synchronous rectifier. In addition, a digital hybrid peak current-mode control scheme with adaptive slope compensation is implemented to ensure stable CCM operation. As a result, the proposed converter achieves reliable ZVS operation, suppresses diode reverse-recovery current, and improve efficiency using cost-effective silicon-based power devices. This study shows that, beyond device-level advancements, appropriate circuit topology and control strategy design are still critical for addressing switching losses and stability challenges in modern synchronous buck converters.

2. Circuit Analysis

Based on the topology presented in [10], Figure 1a, this work replaces the original non-coupled inductor with a series-coupled inductor to mitigate the non-ideal current in the auxiliary inductor $L_2$ caused by the parasitic capacitance $C_{QC}$ of the auxiliary switch. The control scheme employs a synchronous-rectification voltage-sensing circuit to generate the drive signals for the main switch $Q_A$, the synchronous rectifier $Q_B$, and the auxiliary switch $Q_C$. In addition, a digital hybrid control chip (PIC16F1769) is incorporated to measure the input and output voltages and dynamically adjust the slope-compensation parameter, thereby improving system stability and efficiency.

Time-Domain Analysis

Interval I ($t_0$–$t_1$):

As illustrated in Figure 2a and Figure 3, at $t=t_0$, the auxiliary switch $Q_C$ is turned on. During this interval, the auxiliary inductor current $i_{L2}\left(t\right)$ increases, thereby storing energy in the auxiliary inductor $L_2$. Meanwhile, diode $D_1$ becomes reverse-biased.

The current flowing through the coupled inductor winding $L_{11}$, denoted as $i_{L11}\left(t\right)$, decreases linearly, whereas the current through winding $L_{12}$, $i_{L12}\left(t\right)$, increases linearly. The current flowing through the parasitic body diode of the synchronous rectifier switch $Q_B$, denoted as $i_{QB}\left(t\right)$, gradually decreases as $i_{L2}\left(t\right)$ rises, which effectively mitigates the diode reverse-recovery current.

At $t=t_1$, the conditions $i_{L2}\left(t_1\right)=i_{L12}\left(t_1\right)$ and $i_{L11}\left(t_1\right)=i_{QB}\left(t_1\right)=0$ are satisfied. At the same time, $v_{ds,QA}\left(t_1\right)=V_{in}$ and $v_d\left(t_1\right)=0$. Consequently, the parasitic body diode of $Q_B$ is turned off under zero-current conditions, and Interval I ends.

Interval II ($t_1$–$t_2$):

As shown in Figure 2b and Figure 3, at $t=t_1$, the current flowing through the parasitic body diode of the synchronous rectifier switch $Q_B$, denoted as $i_{QB}\left(t_1\right)$, has decreased to zero, while the auxiliary switch $Q_C$ remains turned on. At this instant, the voltage across the parasitic capacitance of the main power switch $Q_A$ satisfies $v_{\{ds,QA\}}\left(t_1\right)=V_{in}$.

$$v_d(t_2)\approx \left[v_o+(V_{in}-v_o){\displaystyle \frac{L_1}{L_1+L_2}}\right]\times 0.9$$

(1)

During this interval, the auxiliary inductor $L_2$, the parasitic capacitance of the synchronous rectifier switch $C_{QB}$, and the parasitic capacitance of the main power switch $C_{QA}$ form a resonant loop. Consequently, the inductor current $i_{L2}\left(t\right)$ begins to charge and discharge the parasitic capacitances $C_{QB}$ and $C_{QA}$.

When the voltage $v_d\left(t\right)$ rises to approximately 90% of the preset input voltage, i.e., $v_d\left(t\right)\approx 0.9\hspace{0.17em}{V}_{in}$, the detection and logic circuitry turns off the auxiliary switch $Q_C$. At this moment, the voltage across the main power switch becomes $v_{\{ds,QA\}}\left(t_2\right)=0$.

Throughout this interval, the current through the coupled inductor winding $L_{11}$ continues to decrease, whereas the current through winding $L_{12}$ keeps increasing. Interval II therefore ends.

Interval III ($t_2$–$t_3$):

As illustrated in Figure 2c and Figure 3, at $t=t_2$, the auxiliary switch $Q_C$ is turned off, and the conditions $v_{ds,QA}\left(t_2\right)=0$ and $v_d\left(t_2\right)=V_{in}$ are satisfied. Under these conditions, turning on the main switch $Q_A$ achieves zero-voltage switching (ZVS), thereby effectively reducing the switching loss of the main power switch.

At this instant, the voltage across the parasitic capacitance of diode $D_1$ satisfies $v_{D1}\left(t_2\right)=V_{in}$. The inductor current $i_{L2}\left(t\right)$ subsequently charges and discharges the parasitic capacitances of the auxiliary switch $Q_C$ and diode $D_1$, namely $C_{QC}$ and $C_{D1}$, respectively. When the voltage across the parasitic capacitance of the auxiliary switch $C_{QC}$ is charged to $V_{in}$ and the voltage across the parasitic capacitance of diode $D_1$, $C_{D1}$, is discharged to zero, the current through the coupled inductor winding $L_{11}$ begins to increase, whereas the current through winding $L_{12}$ decreases. Interval III therefore ends.

Interval IV ($t_3$–$t_4$):

As shown in Figure 2d and Figure 3, at $t=t_3$, the voltage across the parasitic capacitance of the auxiliary switch $C_{QC}$ satisfies $v_{ds,QC}\left(t_3\right)=V_{in}$, while the voltage across the parasitic capacitance of diode $D_1$, $v_{D1}\left(t_3\right)$, decreases to zero, thereby turning on diode $D_1$.

At this instant, the inductor current $i_{L2}\left(t\right)$ flows through diode $D_1$. Since the voltage across the auxiliary inductor $L_2$, $v_{L2}\left(t\right)$, becomes negative, the inductor current $i_{L2}\left(t\right)$ decreases linearly. During this interval, the main power switch $Q_A$ remains turned on. The current $i_{L11}\left(t\right)$ continues to increase, resulting in energy being stored in the coupled inductor winding $L_{11}$, whereas the current $i_{L12}\left(t\right)$ continuously decreases.

When the current $i_{QA}\left(t\right)$ rises to equal the sum of the currents in the coupled inductor windings, i.e., $i_{L11}\left(t\right)+i_{L12}\left(t\right)$, Interval IV ends.

Interval V ($t_4$–$t_5$):

As illustrated in Figure 2e and Figure 3, at $t=t_4$, the main power switch $Q_A$ remains turned on. At this moment, the current through the main power switch satisfies $i_{QA}\left(t_4\right)=i_{L11}\left(t_4\right)$; therefore, the auxiliary inductor current $i_{L2}\left(t_4\right)=0$, and diode $D_1$ is turned off. During this interval, the current through the coupled inductor winding $L_{11}$ continues to increase, whereas the current through winding $L_{12}$ continues to decrease.

Since the voltage across the parasitic capacitance of the auxiliary switch $C_{QC}$ satisfies $v_{ds,QC}\left(t_4\right)=V_{in}$, the parasitic capacitance $C_{QC}$, the main power switch $Q_A$, and the auxiliary inductor $L_2$ form a resonant loop. The parasitic capacitance $C_{QC}$ discharges into the auxiliary inductor $L_2$, while the parasitic capacitance of diode $D_1$, $C_{D1}$, is charged. When the voltage across $C_{QC}$ is discharged to zero and the voltage across $C_{D1}$ is charged to $V_{in}$, Interval V ends.

Interval VI ($t_5$–$t_6$):

As shown in Figure 2f and Figure 3, at $t=t_5$, the main power switch $Q_A$ remains turned on, while the voltage across the parasitic capacitance of the auxiliary switch satisfies $v_{ds,QC}\left(t_5\right)=0$, and the voltage across the parasitic capacitance of diode $D_1$ satisfies $v_{D1}\left(t_5\right)=V_{in}$.

During this interval, the current through the coupled inductor winding $L_{11}$, $i_{L11}\left(t\right)$, decreases linearly, whereas the current through winding $L_{12}$, $i_{L12}\left(t\right)$, increases linearly. Due to the reverse direction of the auxiliary inductor current $i_{L2}\left(t\right)$, it flows through the parasitic body diode of the auxiliary switch $Q_C$. Since the voltage across the auxiliary inductor $L_2$ becomes positive, the inductor current $i_{L2}\left(t\right)$ begins to increase. When the auxiliary inductor current $i_{L2}\left(t\right)$ rises to zero, Interval VI ends.

Interval VII ($t_6$–$t_7$):

As shown in Figure 2h and Figure 3, at $t=t_7$, the main power switch $Q_A$ is turned off. Since the voltage across the parasitic capacitance of the synchronous rectifier switch $Q_B$, $v_d\left(t_7\right)$, equals $V_{in}$, the current through the coupled inductor winding $L_{11}$, $i_{L11}\left(t\right)$, discharges the parasitic capacitance $C_{QB}$ of the synchronous rectifier switch $Q_B$. Conversely, it charges the parasitic capacitance $C_{QA}$ of the main power switch $Q_A$.

This operating interval ends when the voltage across the parasitic capacitance $C_{QA}$ of the main power switch $Q_A$ is charged to $V_{in}$ and the voltage across the parasitic capacitance $C_{QB}$ of the synchronous rectifier switch $Q_B$ is discharged to zero, thereby concluding Interval VIII.

Interval IX ($t_8$–$t_9$):

As shown in Figure 2i and Figure 3, at $t=t_8$, the auxiliary inductor current satisfies $i_{L2}\left(t_8\right)=0$. At this instant, the drain–source voltage of the main power switch satisfies $v_{ds,QA}\left(t_8\right)=V_{in}$, and $v_d\left(t_8\right)=0$. The currents through the coupled inductor windings $L_{11}$ and $L_{12}$, denoted as $i_{L11}\left(t\right)$ and $i_{L12}\left(t\right)$, respectively, continue to flow through the parasitic body diode of the synchronous rectifier switch $Q_B$, thereby providing a freewheeling path.

Since the voltage across the parasitic capacitance of diode $D_1$, $v_{D1}\left(t_8\right)$, equals $V_{in}$, the parasitic capacitance $C_{D1}$ of diode $D_1$ and the auxiliary inductor $L_2$ form a resonant loop for discharging. Conversely, the parasitic capacitance $C_{QC}$ of the auxiliary switch $Q_C$ and the auxiliary inductor $L_2$ form another resonant loop for charging.

This interval ends when the voltage across the parasitic capacitance $C_{QC}$ of the auxiliary switch $Q_C$ is charged to $V_{in}$ and the voltage across the parasitic capacitance $C_{D1}$ of diode $D_1$ is discharged to zero, thereby concluding Interval IX.

Interval X ($t_9$–$t_{10}$):

As shown in Figure 2j and Figure 3, at $t=t_9$, the voltage across the parasitic capacitance of the auxiliary switch $Q_C$ satisfies $v_{ds,QC}\left(t_9\right)=V_{in}$, while the voltage across the parasitic capacitance of diode $D_1$ satisfies $v_{D1}\left(t_9\right)=0$. At this instant, diode $D_1$ becomes forward-biased, and the voltage across the auxiliary inductor $L_2$, $v_{L2}\left(t\right)$, is negative; therefore, the auxiliary inductor current $i_{L2}\left(t\right)$ decreases linearly.

During this interval, the current through the coupled inductor winding $L_{11}$ increases slightly, whereas the current through winding $L_{12}$ decreases marginally. The parasitic body diode of the synchronous rectifier switch $Q_B$ continues to provide a freewheeling path, and the current $i_{QB}\left(t\right)$ is equal to the current $i_{L11}\left(t\right)$.

Interval XI ($t_{10}$–$t_{11}$):

As shown in Figure 2k and Figure 3, at $t=t_{10}$, the voltage across the parasitic capacitance of diode $D_1$, $v_{D1}\left(t_{10}\right)$, approaches zero. Diode $D_1$ remains non-conducting, and the voltage across the auxiliary inductor $L_2$ is clamped to zero; therefore, the auxiliary inductor current $i_{L2}\left(t\right)$ remains constant.

During this interval, the coupled inductor windings $L_{11}$ and $L_{12}$ continue to release energy, while the parasitic body diode of the synchronous rectifier switch $Q_B$ maintains the freewheeling path.

Interval XII ($t_{11}$–$t_{12}$):

As shown in Figure 2l and Figure 3, at $t=t_{11}$, the synchronous rectifier switch $Q_B$ is turned on, and the current $i_{QB}\left(t\right)$ flows through the synchronous rectifier switch to provide the freewheeling path. Consequently, the parasitic body diode of the synchronous rectifier switch $Q_B$ is reverse-biased. The use of the synchronous rectifier switch mitigates the high conduction losses associated with the freewheeling diode in conventional buck converter topologies, thereby improving the overall efficiency of the converter.

Interval XIII ($t_{12}$–$t_{13}$):

As shown in Figure 2m and Figure 3, at the synchronous rectifier switch is turned off, and the current freewheels through the parasitic body diode of the synchronous rectifier switch. After the completion of Interval XIII, one full switching cycle is accomplished.

3. Voltage Detection Control Circuit Design

This architecture consists of a main switch, a synchronous rectifier switch, and an auxiliary switch. The detection circuit shown in Figure 4 determines whether the converter operates in continuous conduction mode (CCM) or discontinuous conduction mode (DCM), and the logic circuit generates the corresponding drive signals. In a conventional synchronous buck converter operating in CCM, when the synchronous rectifier switch is turned off, its body diode conducts the freewheeling current. When the main switch subsequently turns on, the body diode of the synchronous rectifier switch undergoes forced reverse recovery, resulting in a reverse-recovery current spike and additional switching losses. In the proposed circuit, CCM operation is automatically detected, and the auxiliary switch is activated prior to the turn-on of the main switch. The pulse width of the auxiliary switch is adaptively adjusted according to the load condition, as shown in Figure 5a, thereby increasing the auxiliary inductor current and smoothing the decay of the body-diode current of the synchronous rectifier switch. As a result, the reverse-recovery current spike is effectively suppressed. Owing to the corresponding charge–discharge relationship between the detection voltage and the drain–source voltage of the main switch, when rises to approximately 90% of the input voltage, zero-voltage-switching (ZVS) turn-on of the main switch is achieved.

$$v_{ZVS}=vo+(Vin-vo)·{\displaystyle \frac{Lt}{Lt+L2}}·0.9\cong 0.9·Vin$$

(2)

The ZVS threshold scales with the input voltage, allowing the converter to suppress diode reverse-recovery current spikes and achieve zero-voltage switching (ZVS) over a wide input-voltage range. When the converter operates in discontinuous conduction mode (DCM), the synchronous rectifier switch ${\mathrm{Q}}_{\mathrm{B}}$, which is a bidirectional device, must be turned off when its current $i_{QB}$ reaches zero to prevent reverse inductor current, which would otherwise degrade efficiency.

Although current sensing can be employed to detect the zero-current condition, the inclusion of a current sensor increases system cost. Therefore, the proposed architecture adopts a voltage-sensing approach. Because the accuracy of voltage detection is limited in high-voltage applications, the proposed circuit disables the drive signal of the synchronous rectifier switch $Q_B$ during DCM operation based on logic-based control. Similarly, since $i_{QB}$ has already decayed to zero before the main switch $Q_A$ turns on, reverse-recovery effects do not occur. Consequently, the auxiliary switch $Q_C$ is not driven during DCM operation.

4. Auxiliary Inductor Design

Based on the circuit analysis, the component parameters required to achieve zero-voltage switching (ZVS) under continuous conduction mode (CCM) operation over a wide input-voltage range are determined. The switching frequency is denoted as fs, the input voltage ranges from $V_{in,min}$ to $V_{in,max}$, the output voltage is $V_o$, and the rated output power is $P_{o,rate}$. As shown in Figure 3, one switching period $T_s$ consists of the turn-on interval $t_{on}$ and the turn-off time $t_{off}$. After subtracting the dead times $t_{d1}$ and $t_{d2}$ of the synchronous rectifier switches, the effective turn-off interval $t_A$ can be expressed as follows:

$$t_A=t_{off}-t_{d1}-t_{d2}$$

(3)

Dead-Time Implementation Considerations. In (3), the dead times are introduced to ensure non-overlapping operation between the main switch and the synchronous rectifier switch, thereby preventing shoot-through. In the proposed converter, the dead times are implemented as fixed values in the gate-driving and logic circuitry. Their durations are determined based on the switching delay characteristics of the power devices, the propagation delay of the driver circuits, and a safety margin under worst-case operating conditions. Although adaptive slope compensation is employed in the proposed digital hybrid control scheme, the dead times themselves are not dynamically adjusted. Since the zero-voltage-switching (ZVS) operation is mainly achieved through the auxiliary branch and current-shaping mechanism, the dead times only need to satisfy the basic non-overlap requirement and do not play a dominant role in determining the ZVS condition.

To ensure that the main switch achieves zero-voltage switching (ZVS), the auxiliary switch must remain turned on until the drain–source voltage across falls to zero. Therefore, the ZVS time must be less than or equal to the minimum available turn-off interval, which can be expressed as follows:

$$t_{ZVS}\le t_{A,min}$$

(4)

The minimum available turn-off interval $t_{A,min}$ can be expressed as

$$t_{A,min}=T_s-t_{on,max}-t_{d1}-t_{d2}$$

(5)

where $t_{on,max}$ is the maximum turn-on time.

From Figure 3, the zero-voltage switching time $t_{ZVS}$ can be expressed as

$$t_{ZVS}={(t}_1-t_0)+{(t}_2-t_1)$$

(6)

where $\left(t_1-t_0\right)+\left(t_2-t_1\right)$ is

$${\displaystyle \frac{L_2 · I_{o,rate}}{V_{in,min}}}+{\displaystyle \frac{\pi }{2}}\sqrt{L_2·{(C}_{QA}+C_{QB})}$$

(7)

Substituting (6) into (4) yields

$${\displaystyle \frac{L_2 · I_{o,rate}}{V_{in,min}}}+{\displaystyle \frac{\pi }{2}}\sqrt{L_2{·(C}_{QA}+C_{QB})}\le t_{A,min}$$

(8)

$I_{o,rate}$ is the rated load current. By rearranging (8), the maximum auxiliary inductance $L_2$ can be obtained as

$$L_2\le {\displaystyle \frac{2·A·B+\frac{{\pi }^2}{4} · C_r-\sqrt{{\left[-2·A·B-\frac{{\pi }^2}{4} · C_r\right]}^2-4·A^2·B^2}}{2·A^2}}$$

(9)

where $A={\displaystyle \frac{I_{o,rate}}{V_{in,min}}}$, $B=t_{A,min}$, and $C_r=C_{QA}+C_{QB}$.

5. Slope Compensation

Although peak current-mode control (PCMC) provides superior transient response and inherent overcurrent protection compared to average current-mode control or voltage-mode control, it is well known that when the duty ratio $D>0.5$, small perturbations in the inductor current within a single switching cycle tend to grow in subsequent cycles. After several switching periods, the pulse-width modulation (PWM) duty ratio alternates between high and low values, leading to subharmonic oscillation and potential converter instability.

When PCMC operates in continuous conduction mode (CCM), the inductor current remains non-zero and reaches a steady-state condition. In the proposed coupled inductor circuit, the zero-voltage transient interval prior to the turn-on of the main switch is relatively short. Therefore, for simplicity and without loss of generality, the coupled inductor is replaced by an equivalent uncoupled (single) inductor in the following small-signal analysis. As the input voltage energizes the inductor, the inductor current flows through the current-sensing circuit and increases linearly with a slope of $K_i{m}_1$, where $K_i$ denotes the feedback gain of the current sensor. When the sensed inductor current $i_L$ reaches the control signal $v_c$, the logic circuit turns off the main switch $Q_A$ and turns on the synchronous rectifier switch $Q_B$. Consequently, the energy stored in the inductor is transferred to the output, and the inductor current decreases linearly with a slope of $K_i{m}_2$. The rising and falling slopes of the inductor current, denoted as $m_1$ and $m_2$, respectively, can be expressed as follows:

$$m_1={\displaystyle \frac{v_{in-}{v}_o}{L}}\times K_i$$

(10)

$$m_2={\displaystyle \frac{v_o}{L}}\times K_i$$

(11)

When the duty ratio $D>0.5$, load variations introduce a disturbance $\Delta i_L$ in the inductor current. After one switching period $T_s$, this disturbance $\Delta i_L\left(T_s\right)$ grows and distorts the steady-state current waveform, leading to system instability. This relationship can be expressed as follows:

$$\Delta i_L\left(T_s\right)=\left({\displaystyle \frac{m_2}{m_1}}\right)\times \Delta i_L\left(0\right)=>{\displaystyle \frac{\Delta i_L\left(T_s\right)}{\Delta i_L\left(0\right)}}={\displaystyle \frac{m_2}{m_1}}=\alpha$$

(12)

It can be observed that when $\Delta i_L\left(0\right)<\Delta i_L\left(T_s\right)$, the disturbance grows by a factor $\alpha$ during each switching period. When the duty ratio $D>0.5$, $\alpha >1$, causing the disturbance to increase over successive cycles, ultimately leading to system instability.

To suppress the subharmonic oscillation that occurs in peak current-mode control when $D>0.5$, a compensation ramp with slope $-m_s$, synchronized with the switching frequency, is added, as shown in Figure 6. This compensation ramp modifies the disturbed inductor current waveform. With the introduction of $m_s$, the steady-state duty ratio $D$ remains unchanged; however, under oscillatory conditions, the expression for $\Delta i_L\left(T_s\right)$ must be modified as follows:

$${\displaystyle \frac{\Delta i_L\left(T_s\right)}{\Delta i_L\left(0\right)}}=-{\displaystyle \frac{m_2-m_s}{m_1+m_s}}=\sigma$$

(13)

The stability condition can be expressed as

$$\sigma =\left|{\displaystyle \frac{m_2-m_s}{m_1+m_s}}\right|<1$$

(14)

From Equation (14), it can be obtained that

$$m_s>-{\displaystyle \frac{1}{2}}(m_1-m_2)$$

(15)

Substituting Equations (10) and (11) into Equation (15) yields

$$m_s>(-0.5V_{in}+V_o){\displaystyle \frac{K_i}{L}}$$

(16)

Therefore, the slope of the compensation current must satisfy the condition given in Equation (16). This stability criterion is generally applicable to conventional slope-compensation schemes employed in peak current-mode controlled converters.

Based on the above discussion, the importance of slope compensation and appropriate parameter design becomes evident. A converter employing peak current-mode control (PCMC) remains stable only when the compensation slope is greater than or equal to one-half of the falling slope of the inductor current [16]. Since the required compensation slope depends on the inductance as well as the input and output voltages, a fixed compensation slope may degrade the system gain and dynamic performance. Consequently, to ensure stable operation over a wide input- and output-voltage range, the adoption of variable slope compensation is essential [5].

Since the auxiliary branch and coupled inductor mainly affect the short switching transition intervals associated with ZVS operation, their influence on the averaged inductor current dynamics is negligible in the low-frequency range of interest for small-signal stability analysis. The gain parameters used in the small-signal model of Figure 7 are summarized in

Table 1. Gain parameters of Figure 7 [21].

Gain Parameters	$\mathbf{Function} {\mathbf{G}}_{\mathbf{p}}\left(\mathbf{s}\right)$
$k_f$	$-{\displaystyle \frac{D{T}_s{R}_i}{L_1}}(1-{\displaystyle \frac{D}{2}})$
$k_r$	${\displaystyle \frac{{(1-D)}^2{T}_s{R}_i}{{2L}_1}}$
$F_m$	${\displaystyle \frac{1}{{(m}_1+m_s)T_s}}$
$H_e\left(s\right)$	$1+{\displaystyle \frac{s}{{\omega }_n{Q}_z}}+{\displaystyle \frac{s^2}{{{\omega }_n}^2}}$$, Q_z={\displaystyle \frac{-2}{\pi }}$$, {\omega }_n={\displaystyle \frac{\pi }{T_s}}$

.

Figure 7 illustrates the small-signal model of the peak current mode inner loop. Based on this model, the control-to-output transfer function $G_p\left(s\right)$ is derived as follows:

$$G_p\left(s\right)={\displaystyle \frac{{\widehat{V}}_o}{{\widehat{V}}_c}}\cong {\displaystyle \frac{R_o}{R_i}}\times {\displaystyle \frac{1}{1+\frac{R_o\times T_s}{L}\times \left[m_c\times \left(1-D\right)-0.5\right]}}\times F_p(s)\times F_h(s)$$

(17)

$$F_p\left(s\right)={\displaystyle \frac{1+s\times C\times R_c}{1+\frac{s}{{\omega }_p}}}$$

(18)

$$F_h\left(s\right)={\displaystyle \frac{1}{1+\frac{s}{{{\omega }_n\times Q}_p}\times \frac{s^2}{{{\omega }_n}^2}}}$$

(19)

$${\omega }_p={\displaystyle \frac{1}{C\times R_o}}+{\displaystyle \frac{T_s}{L\times C}}\times [m_c\left(1-D\right)-0.5]$$

(20)

$${\omega }_n={\displaystyle \frac{\pi }{T_s}}$$

(21)

$$Q_p={\displaystyle \frac{1}{\pi \times [m_c\times \left(1-D\right)-0.5]}}$$

(22)

$$m_c=1+{\displaystyle \frac{m_s}{m_1}}$$

(23)

Here, $F_p\left(s\right)$ represents the low-frequency component of the open-loop converter under peak current-mode control. As shown in Equation (18), it contains one zero and one pole. The term $F_h\left(s\right)$ represents the high-frequency component, which, according to Equation (19), includes two poles located around half of the switching frequency, thereby forming a second-order system. As reported in [11], the parameter $Q_p$ plays a critical role in shaping the mid- and high-frequency small-signal gain and phase characteristics. To suppress subharmonic oscillation and maintain a sufficient gain margin, $Q_p$ must remain positive to ensure system stability. Accordingly, $Q_p$ is typically designed within the range of 0.6 to 1.

Table 2. Parameters of the peak current-mode buck converter.

Value	Value
$V_{in} \left(\mathrm{V}\right)$	30–160
$V_o \left(\mathrm{V}\right)$	$24,48,96$
$I_o \left(\mathrm{A}\right)$	$5$
$f_s\left(\mathrm{k}\mathrm{H}\mathrm{z}\right)$	$100$
${\mathrm{L}}_t\left(\mathsf{\mu }\mathrm{H}\right)$	$127$
${\mathrm{C}}_o\left(\mathsf{\mu }\mathrm{F}\right)$	$440$
${\mathrm{R}}_c(\mathrm{m}\Omega )$	$30$
${\mathrm{k}}_i(\mathrm{A}/\mathrm{V})$	$0.4$

Table 2. Parameters of the peak current-mode buck converter.

Value	Value
$V_{in} \left(\mathrm{V}\right)$	30–160
$V_o \left(\mathrm{V}\right)$	$24,48,96$
$I_o \left(\mathrm{A}\right)$	$5$
$f_s\left(\mathrm{k}\mathrm{H}\mathrm{z}\right)$	$100$
${\mathrm{L}}_t\left(\mathsf{\mu }\mathrm{H}\right)$	$127$
${\mathrm{C}}_o\left(\mathsf{\mu }\mathrm{F}\right)$	$440$
${\mathrm{R}}_c(\mathrm{m}\Omega )$	$30$
${\mathrm{k}}_i(\mathrm{A}/\mathrm{V})$	$0.4$

The step-wise slope-compensation profile shown in Figure 8 can be regarded as a segmented approximation of the ideal continuous compensation function derived from the peak current-mode stability condition, providing a practical trade-off between implementation simplicity and wide-range stability.

Due to the segmented variable control employed for slope compensation in the hybrid digital control chip, an interval-based approach is adopted, as illustrated in Figure 8. According to Equation (22), the required slope compensation for achieving $Q_p\approx 1$ can be determined, enabling the optimal compensation value to be implemented within the control chip. As shown in Figure 9, Figure 10 and Figure 11, under different input-voltage conditions, when $Q_p\approx 1$ and $\sigma <1$, the peak current-mode inner loop remains stable.

6. Experimental Results

Two buck converters with a rated output current of 5 A were implemented in this study: a zero-voltage-switching (ZVS) synchronous buck converter without a coupled inductor and a ZVS synchronous buck converter with a coupled inductor. As shown in Figure 3, the maximum on-time is $t_{on,max}\approx 8\hspace{0.17em}\mathsf{\mu }\mathrm{s}$. Substituting this value into Equation (5) yields the minimum available off-time of $t_{A,min}=1.4\hspace{0.17em}\mathsf{\mu }\mathrm{s}$. According to Equation (9), the auxiliary inductor is required to satisfy $L_2\le 7.5\hspace{0.17em}\mathsf{\mu }\mathrm{H}$. In the prototype implementation, an auxiliary inductor of $L_2=3\hspace{0.17em}\mathsf{\mu }\mathrm{H}$ is selected. Substituting this value into Equation (6) gives $t_{ZVS}=0.65\hspace{0.17em}\mathsf{\mu }\mathrm{s}$, which satisfies the condition in Equation (4).

Table 3. Converter specifications and circuit component parameters.

Parameters	Value
$\mathrm{Input} \mathrm{voltage}, V_{in}$(V)	30–160
$\mathrm{Output} \mathrm{Voltage}, V_o\left(V\right)$	24, 48, 96
$\mathrm{Rated} \mathrm{Output} \mathrm{Current}, I_{o,rate}$(A)	5
$\mathrm{Switching} \mathrm{Frequency}, f_s\left(\mathrm{k}\mathrm{H}\mathrm{z}\right)$	100
$\mathrm{Filter} \mathrm{Inductor}, L_t\left(\mathsf{\mu }\mathrm{H}\right)$	127.6
$\mathrm{Filter} \mathrm{Inductor}, L_{11}$$, L_{12}$$, \mathrm{M}\left(\mathsf{\mu }\mathrm{H}\right)$	5.26, 85.3, 18.5
$\mathrm{Auxiliary} \mathrm{Inductor}, L_2\left(\mathsf{\mu }\mathrm{H}\right)$	3
$\mathrm{Filter} \mathrm{Capacitor}, C_o\left(\mathsf{\mu }\mathrm{F}\right)$	440

and

Table 4. Power device parameters.

Parameters	Value
$\mathrm{Power} \mathrm{Switch} Q_A$$, Q_C$	STW65N65DM2AG
$\mathrm{Diode} D_1$$, D_2$	IDW50E60
$\mathrm{Parasitic} \mathrm{Capacitance} C_{QA}$$, C_{QC}$$(p$F)	210
$\mathrm{Parasitic} \mathrm{Capacitance} C_{D1}$$, C_{D2}$$(n$F)	3

Note: The parasitic capacitance values listed in this table are extracted from the manufacturers’ datasheets under the relevant voltage conditions and are used as representative values for the ZVS resonance analysis.

list the converter specifications, circuit components, and power device parameters, respectively.

6.1. Steady-State and ZVS Verification Without Coupled Inductor

At the investigated power and voltage levels, the reverse-recovery current spike of the synchronous rectifier and the associated hard turn-on loss represent a dominant switching-loss component in a conventional synchronous buck converter operating in CCM, motivating the loss-mitigation strategy adopted in this work. Figure 12, Figure 13, Figure 14 and Figure 15 present the experimental results of the ZVS synchronous buck converter without a coupled inductor under input voltages of $V_{in}=30$, 40, and 160 V, with $V_o=24 \mathrm{V}$ and $I_{o,\mathrm{r}\mathrm{a}\mathrm{t}\mathrm{e}}=5 \mathrm{A}$. All operating conditions satisfy $i_{L1,\mathrm{a}\mathrm{v}\mathrm{g}}>0$ and $i_{L1,\mathrm{m}\mathrm{i}\mathrm{n}}>0$, indicating continuous conduction mode (CCM) operation.

Figure 12a, Figure 13a and Figure 14a show the auxiliary inductor current $i_{L2}$ and the diode current $i_{D1}$. Due to the small inductance of $L_2$, the diode parasitic capacitance induces a noticeable transient current, which becomes more pronounced at higher input voltages and results in a reduction in the synchronous rectifier current $i_{QB}$. At lower input voltages, this effect is less significant because of the smaller rising slope of $i_{L2}$.

Figure 12b and Figure 14b illustrate that the auxiliary switch $Q_C$ is activated prior to the turn-on of the main switch $Q_A$, forcing $i_{QB}$ to decay to zero. Subsequently, the drain–source voltage of $Q_B$ resonates to approximately $0.9V_{in}$, after which $Q_C$ is turned off. Figure 12c and Figure 14c confirm that the main switch $Q_A$ achieves zero-voltage switching (ZVS).

Figure 12d and Figure 14d show the error-amplifier output, slope-compensation signal, and current-feedback signal. The hybrid digital controller adaptively adjusts the slope-compensation parameter according to the input voltage. The compensation slope is approximately $0.061 \mathrm{V}/\mathsf{\mu }\mathrm{s}$ at $V_{in}=30 \mathrm{V}$ and $0.055 \mathrm{V}/\mathsf{\mu }\mathrm{s}$ at $V_{in}=40 \mathrm{V}$. At $V_{in}=160 \mathrm{V}$, slope compensation is unnecessary because the duty ratio is less than 0.5. Therefore, the minimum available slope of $0.025 \mathrm{V}/\mathsf{\mu }\mathrm{s}$ is adopted in the implementation.

6.2. Steady-State and ZVS Verification with Coupled Inductor

Figure 15 and Figure 22 present the experimental results of the ZVS synchronous buck converter with a coupled inductor. The tests were conducted at duty-cycle values of $D=0.8$, 0.6, and the minimum duty cycle. For an output voltage of $24 \mathrm{V}$, the input voltage ranges from 30 to 160 V; for $48 \mathrm{V}$, from 60 to 160 V; and for $96 \mathrm{V}$, from 120 to 160 V. The rated output current is $5 \mathrm{A}$ for all test cases. The measured waveforms include those of the main switch $Q_A$, synchronous rectifier switch $Q_B$, auxiliary switch $Q_C$, diode $D_1$, coupled inductor windings $L_{11}$ and $L_{12}$, and auxiliary inductor $L_2$. All operating points satisfy $i_{L1,\mathrm{a}\mathrm{v}\mathrm{g}}>0$ and $i_{L1,\mathrm{m}\mathrm{i}\mathrm{n}}>0$, indicating continuous conduction mode (CCM) operation. Figure 15a and Figure 22a show the auxiliary inductor current $i_{L2}$ and diode current $i_{D1}$. With the introduction of the coupled inductor, the current associated with the diode parasitic capacitance is diverted to $L_{11}$, thereby reducing the diode current prior to the turn-on of the auxiliary switch $Q_C$ and allowing the synchronous rectifier current to continue flowing. Figure 15b and Figure 22b show the current and voltage waveforms of the synchronous rectifier switch $Q_B$. Before the main switch $Q_A$ is turned on, the auxiliary switch $Q_C$ is activated first, causing $i_{L2}$ to increase and allowing $i_{QB}$ to smoothly decay to zero. Meanwhile, the drain–source voltage resonates from zero to approximately $0.9V_{in}$, after which $Q_C$ is turned off. Figure 15c and Figure 22c confirm that the main switch $Q_A$ achieves zero-voltage switching (ZVS).

Figure 15d and Figure 22d show the error-amplifier output, slope-compensation signal, and current-feedback signal. The hybrid digital controller automatically adjusts the slope-compensation parameter according to the input and output voltages. For a 24 V output, the slope-compensation values at input voltages of 30, 40, and 160 V are approximately 0.061, 0.055, and 0.025, respectively. For a 48 V output, the corresponding values at 60, 80, and 160 V are approximately 0.113, 0.10, and, respectively. For a 96 V output, the values at 120 and 160 V are approximately 0.235 and 0.213, respectively.

Dynamic and Transient Response Considerations. Although the experimental results presented in Section 6 mainly emphasize steady-state operation and zero-voltage-switching (ZVS) performance, the dynamic and transient behavior of the proposed converter can be reasonably assessed based on both the analytical framework and the measured control-related waveforms. As discussed in Section 5, the proposed control scheme is based on a peak current-mode control (PCMC) structure with adaptive slope compensation. The corresponding small-signal model and open-loop control-to-output Bode plots (Figure 7, Figure 9, Figure 10 and Figure 11) indicate that sufficient gain margin and phase margin are maintained over a wide range of input and output voltages, which implies a stable dynamic behavior of the inner current loop. From the experimental results, it can be observed that the measured inductor current, current-feedback signal, and slope-compensation signal (Figure 12, Figure 13, Figure 14, Figure 15, Figure 16, Figure 17, Figure 18, Figure 19, Figure 20, Figure 21 and Figure 22d) remain well regulated under different operating conditions. No subharmonic oscillation or abnormal current perturbation is observed, even at high duty ratios, indicating that the adaptive slope-compensation mechanism effectively suppresses current instability and enhances transient robustness compared with a fixed-slope design. It should be noted that the auxiliary branch and the coupled inductor structure mainly influence the short switching transition intervals associated with ZVS operation. Their impact on the low-frequency averaged dynamics of the power-stage is therefore limited. As a result, the dominant transient response of the proposed converter is primarily governed by the peak current-mode control loop and the output LC filter, which are similar to those of a conventional current-mode buck converter. Based on the above analytical and experimental observations, the proposed control strategy is expected to maintain stable and well-damped dynamic responses under load and input-voltage variations, while simultaneously achieving soft-switching operation and high conversion efficiency.

Figure 22. Coupled inductor zero-voltage-switching synchronous buck converter at $V_{\mathrm{in}}=160 \mathrm{V}$, $V_o=96 \mathrm{V}$, $P_o=480 \mathrm{W}$.

Figure 22. Coupled inductor zero-voltage-switching synchronous buck converter at $V_{\mathrm{in}}=160 \mathrm{V}$, $V_o=96 \mathrm{V}$, $P_o=480 \mathrm{W}$.

6.3. Efficiency Performance Under Different Load Conditions

This work builds upon the voltage detection control applied to a zero-voltage-switching (ZVS) synchronous buck converter reported in [10], where the efficiency of the proposed architecture was experimentally compared with that of a conventional buck converter. Based on the results presented in [10], the present study further extends the analysis by introducing a coupled inductor and conducting a comparative evaluation under identical circuit parameters. Figure 23 shows the efficiencies of the converter with and without the coupled inductor at an output voltage of 24 V and an input range of 30–160 V. With the coupled inductor, the efficiencies at full load (120 W), half load (72 W), and light load (24 W) are approximately 97.6%, 97.1%, and 96.3%, respectively. Figure 23 and Figure 24 present efficiency comparisons for output voltages of 48 V (input 60–160 V) and 96 V (input 120–160 V). From Figure 23, Figure 24 and Figure 25, it is evident that the converter with the coupled inductor achieves higher efficiency than the one without it. Compared with recently reported ZVS synchronous buck converters employing auxiliary-assisted soft-switching techniques, the proposed approach demonstrates a competitive or higher efficiency under similar operating conditions [22,23,24].

The efficiency performance of the proposed converter is evaluated and compared with the reference circuit shown in Figure 1a under identical power-stage components and operating conditions, in order to isolate the impact of the proposed auxiliary-assisted ZVS mechanism and coupled inductor implementation. Although wide-bandgap (WBG) power devices significantly reduce reverse-recovery losses compared to silicon devices, non-negligible switching losses still remain in conventional synchronous buck converters, particularly under high input-voltage operation. These losses are mainly associated with the hard turn-on of the main switch due to output-capacitance discharge and the residual reverse-recovery behavior of the synchronous rectifier body diode.

By shaping the synchronous rectifier current and enabling zero-voltage switching (ZVS) of the main switch through the auxiliary branch, the proposed converter mitigates both loss mechanisms. As a result, even when WBG devices are employed, the proposed converter achieves a consistent efficiency improvement of approximately 1–2% under medium- to heavy-load conditions, especially at higher input voltages, as shown in Figure 23, Figure 24 and Figure 25.

When the load is further reduced, the converter naturally transitions into discontinuous conduction mode (DCM). Under DCM operation, the voltage detection logic automatically disables both the auxiliary branch and the synchronous rectifier, preventing additional circulating or resonant losses. Consequently, the proposed control scheme does not penalize light-load or very light-load efficiency, and the auxiliary circuit operates only when its benefits are most effective.

A comparison between the proposed method and representative buck converter control techniques is provided in

Table 5. Comparison between the proposed method and representative buck converter control techniques.

Ref	Control Strategy	ZVS/Soft- Switching Method	Reverse- Recovery Suppression	Slope Compensation	Digital Adaptivity	Auxiliary Circuit	Efficiency (Reported)	Remarks
[9]	Analog PWM + ZVT	Fixed auxiliary resonant branch	Partial	Fixed (Analog)	No	Yes	~90–92%	Fixed timing, limited adaptability
[10]	Analog ZVS buck with voltage detection	Auxiliary switch- assisted ZVS	Good	Fixed	No	Yes	~91%	Increased circuit complexity
[11]	Analog PWM + ZCT	Zero- current transition	Moderate	Not required	No	Yes	~93–95%	ZVS sensitive to operating conditions
[17]	Analog PCMC	Hard switching	Poor	Fixed slope	No	No	~90–92%	Simple structure, reverse recovery remains
[18]	Digital PCMC	Hard switching	Poor	Fixed digital slope	Limited	No	~91–93%	No ZVS, subharmonic oscillation risk
This work	Digital hybrid PCMC	Coupled inductor- assisted ZVS	Excellent	Adaptive (variable)	Yes	Yes	Up to 97.6%	Wide-range stability, low-cost MCU

.

Table 6. Qualitative loss breakdown comparison between a conventional synchronous buck converter and the proposed converter.

Loss Component	Conventional Synchronous Buck	Proposed Converter
Main-switch turn-on loss	High (hard switching,$\mathrm{especially} \mathrm{at} \mathrm{high} V_{\mathrm{i}\mathrm{n}}$)	Significantly reduced (ZVS turn-on enabled by auxiliary branch)
Synchronous rectifier reverse-recovery loss	Significant under CCM operation	Suppressed by auxiliary-assisted current shaping
Output-capacitance discharge loss	Present	Reduced due to ZVS operation
Conduction loss (main and SR switches)	Comparable	Comparable
Auxiliary branch conduction and switching loss	Not applicable	Present but limited to short transition interval
Total switching- related loss	Dominant at medium– heavy load	Reduced compared with conventional buck

summarizes a qualitative loss-mechanism comparison derived from the analytical discussions in Section 2 and Section 5, the measured efficiency trends in Section 6, and established loss models for synchronous buck converters reported in the literature.

Figure 26 shows the implemented hardware prototype of the proposed zero-voltage-switching synchronous buck converter system used in the experimental verification.

7. Conclusions

This paper has presented a zero-voltage-switching (ZVS) synchronous buck converter based on a hybrid digital current-mode control scheme with adaptive slope compensation. By dynamically adjusting the compensation slope according to the sensed input and output voltages ($V_{in}$ and $V_o$), stable current-mode operation is maintained over a wide operating range, effectively suppressing subharmonic oscillations. To address the resolution limitations of digital slope compensation, the converter was designed to operate at a switching frequency of 100 kHz. Furthermore, the introduction of an auxiliary branch enables the induced current to naturally decay after the main switch $Q_A$ is turned off, thereby facilitating soft-switching operation and improving current waveform quality.

Experimental results confirm that, under identical component conditions, the coupled inductor configuration consistently achieves superior current characteristics and higher conversion efficiency compared to a non-coupled design. These results demonstrate the effectiveness of the proposed approach for enhancing stability and efficiency in digitally controlled ZVS buck converters. Future work will focus on extending the proposed control strategy to higher power levels and exploring its applicability to other converter topologies.