Review Reports

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

The novelty compared to existing AFC methods is not clear enough.

The measurement results lack sufficient evidence of long-term stability and PVT robustness.

The reported calibration time improvement over prior works is modest and needs more critical discussion.

Although chip fabrication results are shown, additional simulations under broader conditions would be necessary to fully support the claims.

Some statements about “fast and robust” performance feel overstated without stronger quantitative comparisons.

Author Response

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Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

In the manuscript, authors proposed a novel AFC circuit for PLL calibration, showing the merits of low power, fast speed, and high stability. Generally, the manuscript is clearly presented. The following issues should be addressed:

1. The references should be updated, reflecting the most recent research progress in the field.
2. The Introduction part should be reorganized. 
3. The calibration effect of the temperature on the frequency output should be supplemented. In application, the temperature influence is one of the key factors that should be corrected. In the manuscript, it seems all the results are based on the room temperature environment.

Author Response

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Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

1. The abstract is a bit short; it would be if the current issue can be discussed.
2. What is the effect of the cycle-slip to spur performance?
3. How to ensure the frequency tuning settle at the best noise if two tuning codes overlapped?
4. What is the jitter performance?
5. What is the target application for this PLL?
6. Would it be useful to use "synthesizer" rather than "PLL".
7. This a nicely written paper, with measurement results that validate the proposed method.

Author Response

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Author Response File: Author Response.pdf

Reviewer 4 Report

Comments and Suggestions for Authors

This article presents a technique of automatic frequency calibration for a fractional N PLL phase locked loop with a voltage controlled oscillator. These systems are crucial nowadays for sub-triggered systems to operate stable and with low noise, allowing a fast clock signal generation. References are correctly studied, but a report on current works would help, for example in the last 3-5 years, to show that the problem is of actual importance. Also, loop filtering techniques from 2022 optimized the loop designs. Finer frequency resolution and performance is better represented in latest research than in the one in the years 2000 or so.

In my opinion, the abstract should contain more word descriptive details and not all numbers at once.

The research work is pretty complex, but contains many notions, characteristics and block diagrams and not everything is clearly explained. It should become clear for all interested readers, independently of how comfortable they are with the subject.

In the introduction, when you refer to frequency  2⁵ – 2⁷, please add Hertz next to the numbers.

I don’t understand the idiom “1-2 code”, please explain it in the beginning somewhere.

Figures 1 and 2 define well the process, but maybe the explanations in the introductory part of the second chapter could be systemized somehow in a numbered or bulleted list, for a clearer highlight of the building steps.

Please try and read again the whole paper and verify that each acronym is explained the first time it is used and also each variable name detailed the first time it appears in the text. For instance the CP that first appears in figure 1 is nowhere explained as “charge pump”. Either we know, or we have to deduce from the CPPLL denomination that is explained. Same for values K_i, first time they appear where the explanation for figure 6 is. Unfortunately, lines are not numbered so it is hard for me to refer to certain lines or paragraphs in the text.

Please provide in the end a table with all acronym explanations, because they are a lot,  and if anyone missed their first explanation in the presentation, at least knows where to find them.

In chapters 3 and 4 everything is beautifully explained, the figures visually sustain and explain the work that was thorough and shows the necessary finesse of the timing control.

In figure 10.b on x-axis value range is missing, while on y-axis the measurement units miss. Even if they might be obvious and explained in the text, it is good to be thorough and write them down each time.

Regarding fig 15 and the ± 0.5% current mismatch, please insert in the text the corresponding calculus formula to rpove those values in respect to the signal values in figure 15.

It is not clear, in table 1 the performances are general to a cp or they especially refer to your concrete research?  In text it is mentioned just “The CPPLL performances”, please be more specific, to emphasize your contribution. Regarding this aspect, table 2 provides exactly this.

Congratulations for the meticulous work, block diagrams are very useful in understanding the circuits you designed and the characteristics prove the good results you obtained. Overall, it is a thorough, refined research. Just in the beginning the introductory parts should be a little clearer explained, to smoothly introduce the reader into the subject.

Author Response

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Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

All of the questions are well addressed.

Reviewer 2 Report

Comments and Suggestions for Authors

I am glad to see my concerns are addressed. It can be accepted in its current version.